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515 lines
28 KiB
515 lines
28 KiB
/********************************** (C) COPYRIGHT ******************************* |
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* File Name : ch32v30x_tim.h |
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* Author : WCH |
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* Version : V1.0.0 |
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* Date : 2021/06/06 |
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* Description : This file contains all the functions prototypes for the |
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* TIM firmware library. |
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. |
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* SPDX-License-Identifier: Apache-2.0 |
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*******************************************************************************/ |
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#ifndef __CH32V30x_TIM_H |
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#define __CH32V30x_TIM_H |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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#include "ch32v30x.h" |
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/* TIM Time Base Init structure definition */ |
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typedef struct |
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{ |
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uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock. |
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This parameter can be a number between 0x0000 and 0xFFFF */ |
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uint16_t TIM_CounterMode; /* Specifies the counter mode. |
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This parameter can be a value of @ref TIM_Counter_Mode */ |
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uint16_t TIM_Period; /* Specifies the period value to be loaded into the active |
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Auto-Reload Register at the next update event. |
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This parameter must be a number between 0x0000 and 0xFFFF. */ |
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uint16_t TIM_ClockDivision; /* Specifies the clock division. |
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This parameter can be a value of @ref TIM_Clock_Division_CKD */ |
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uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter |
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reaches zero, an update event is generated and counting restarts |
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from the RCR value (N). |
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This means in PWM mode that (N+1) corresponds to: |
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- the number of PWM periods in edge-aligned mode |
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- the number of half PWM period in center-aligned mode |
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This parameter must be a number between 0x00 and 0xFF. |
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@note This parameter is valid only for TIM1 and TIM8. */ |
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} TIM_TimeBaseInitTypeDef; |
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/* TIM Output Compare Init structure definition */ |
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typedef struct |
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{ |
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uint16_t TIM_OCMode; /* Specifies the TIM mode. |
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This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ |
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uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state. |
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This parameter can be a value of @ref TIM_Output_Compare_state */ |
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uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state. |
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This parameter can be a value of @ref TIM_Output_Compare_N_state |
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@note This parameter is valid only for TIM1 and TIM8. */ |
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uint16_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register. |
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This parameter can be a number between 0x0000 and 0xFFFF */ |
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uint16_t TIM_OCPolarity; /* Specifies the output polarity. |
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This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
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uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity. |
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This parameter can be a value of @ref TIM_Output_Compare_N_Polarity |
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@note This parameter is valid only for TIM1 and TIM8. */ |
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uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state. |
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This parameter can be a value of @ref TIM_Output_Compare_Idle_State |
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@note This parameter is valid only for TIM1 and TIM8. */ |
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uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state. |
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This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State |
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@note This parameter is valid only for TIM1 and TIM8. */ |
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} TIM_OCInitTypeDef; |
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/* TIM Input Capture Init structure definition */ |
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typedef struct |
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{ |
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uint16_t TIM_Channel; /* Specifies the TIM channel. |
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This parameter can be a value of @ref TIM_Channel */ |
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uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal. |
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This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
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uint16_t TIM_ICSelection; /* Specifies the input. |
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This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
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uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler. |
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This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
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uint16_t TIM_ICFilter; /* Specifies the input capture filter. |
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This parameter can be a number between 0x0 and 0xF */ |
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} TIM_ICInitTypeDef; |
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/* BDTR structure definition */ |
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typedef struct |
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{ |
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uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode. |
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This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ |
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uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state. |
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This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ |
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uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters. |
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This parameter can be a value of @ref Lock_level */ |
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uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the |
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switching-on of the outputs. |
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This parameter can be a number between 0x00 and 0xFF */ |
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uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not. |
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This parameter can be a value of @ref Break_Input_enable_disable */ |
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uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity. |
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This parameter can be a value of @ref Break_Polarity */ |
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uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not. |
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This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ |
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} TIM_BDTRInitTypeDef; |
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/* TIM_Output_Compare_and_PWM_modes */ |
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#define TIM_OCMode_Timing ((uint16_t)0x0000) |
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#define TIM_OCMode_Active ((uint16_t)0x0010) |
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#define TIM_OCMode_Inactive ((uint16_t)0x0020) |
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#define TIM_OCMode_Toggle ((uint16_t)0x0030) |
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#define TIM_OCMode_PWM1 ((uint16_t)0x0060) |
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#define TIM_OCMode_PWM2 ((uint16_t)0x0070) |
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/* TIM_One_Pulse_Mode */ |
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#define TIM_OPMode_Single ((uint16_t)0x0008) |
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#define TIM_OPMode_Repetitive ((uint16_t)0x0000) |
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/* TIM_Channel */ |
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#define TIM_Channel_1 ((uint16_t)0x0000) |
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#define TIM_Channel_2 ((uint16_t)0x0004) |
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#define TIM_Channel_3 ((uint16_t)0x0008) |
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#define TIM_Channel_4 ((uint16_t)0x000C) |
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/* TIM_Clock_Division_CKD */ |
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#define TIM_CKD_DIV1 ((uint16_t)0x0000) |
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#define TIM_CKD_DIV2 ((uint16_t)0x0100) |
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#define TIM_CKD_DIV4 ((uint16_t)0x0200) |
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/* TIM_Counter_Mode */ |
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#define TIM_CounterMode_Up ((uint16_t)0x0000) |
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#define TIM_CounterMode_Down ((uint16_t)0x0010) |
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#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) |
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#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) |
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#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) |
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/* TIM_Output_Compare_Polarity */ |
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#define TIM_OCPolarity_High ((uint16_t)0x0000) |
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#define TIM_OCPolarity_Low ((uint16_t)0x0002) |
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/* TIM_Output_Compare_N_Polarity */ |
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#define TIM_OCNPolarity_High ((uint16_t)0x0000) |
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#define TIM_OCNPolarity_Low ((uint16_t)0x0008) |
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/* TIM_Output_Compare_state */ |
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#define TIM_OutputState_Disable ((uint16_t)0x0000) |
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#define TIM_OutputState_Enable ((uint16_t)0x0001) |
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/* TIM_Output_Compare_N_state */ |
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#define TIM_OutputNState_Disable ((uint16_t)0x0000) |
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#define TIM_OutputNState_Enable ((uint16_t)0x0004) |
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/* TIM_Capture_Compare_state */ |
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#define TIM_CCx_Enable ((uint16_t)0x0001) |
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#define TIM_CCx_Disable ((uint16_t)0x0000) |
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/* TIM_Capture_Compare_N_state */ |
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#define TIM_CCxN_Enable ((uint16_t)0x0004) |
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#define TIM_CCxN_Disable ((uint16_t)0x0000) |
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/* Break_Input_enable_disable */ |
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#define TIM_Break_Enable ((uint16_t)0x1000) |
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#define TIM_Break_Disable ((uint16_t)0x0000) |
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/* Break_Polarity */ |
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#define TIM_BreakPolarity_Low ((uint16_t)0x0000) |
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#define TIM_BreakPolarity_High ((uint16_t)0x2000) |
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/* TIM_AOE_Bit_Set_Reset */ |
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#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) |
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#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) |
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/* Lock_level */ |
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#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) |
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#define TIM_LOCKLevel_1 ((uint16_t)0x0100) |
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#define TIM_LOCKLevel_2 ((uint16_t)0x0200) |
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#define TIM_LOCKLevel_3 ((uint16_t)0x0300) |
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/* OSSI_Off_State_Selection_for_Idle_mode_state */ |
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#define TIM_OSSIState_Enable ((uint16_t)0x0400) |
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#define TIM_OSSIState_Disable ((uint16_t)0x0000) |
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/* OSSR_Off_State_Selection_for_Run_mode_state */ |
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#define TIM_OSSRState_Enable ((uint16_t)0x0800) |
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#define TIM_OSSRState_Disable ((uint16_t)0x0000) |
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/* TIM_Output_Compare_Idle_State */ |
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#define TIM_OCIdleState_Set ((uint16_t)0x0100) |
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#define TIM_OCIdleState_Reset ((uint16_t)0x0000) |
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/* TIM_Output_Compare_N_Idle_State */ |
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#define TIM_OCNIdleState_Set ((uint16_t)0x0200) |
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#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) |
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/* TIM_Input_Capture_Polarity */ |
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#define TIM_ICPolarity_Rising ((uint16_t)0x0000) |
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#define TIM_ICPolarity_Falling ((uint16_t)0x0002) |
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#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) |
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/* TIM_Input_Capture_Selection */ |
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#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be |
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connected to IC1, IC2, IC3 or IC4, respectively */ |
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#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be |
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connected to IC2, IC1, IC4 or IC3, respectively. */ |
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#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ |
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/* TIM_Input_Capture_Prescaler */ |
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#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ |
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#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ |
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#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ |
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#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ |
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/* TIM_interrupt_sources */ |
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#define TIM_IT_Update ((uint16_t)0x0001) |
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#define TIM_IT_CC1 ((uint16_t)0x0002) |
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#define TIM_IT_CC2 ((uint16_t)0x0004) |
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#define TIM_IT_CC3 ((uint16_t)0x0008) |
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#define TIM_IT_CC4 ((uint16_t)0x0010) |
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#define TIM_IT_COM ((uint16_t)0x0020) |
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#define TIM_IT_Trigger ((uint16_t)0x0040) |
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#define TIM_IT_Break ((uint16_t)0x0080) |
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/* TIM_DMA_Base_address */ |
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#define TIM_DMABase_CR1 ((uint16_t)0x0000) |
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#define TIM_DMABase_CR2 ((uint16_t)0x0001) |
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#define TIM_DMABase_SMCR ((uint16_t)0x0002) |
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#define TIM_DMABase_DIER ((uint16_t)0x0003) |
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#define TIM_DMABase_SR ((uint16_t)0x0004) |
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#define TIM_DMABase_EGR ((uint16_t)0x0005) |
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#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) |
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#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) |
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#define TIM_DMABase_CCER ((uint16_t)0x0008) |
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#define TIM_DMABase_CNT ((uint16_t)0x0009) |
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#define TIM_DMABase_PSC ((uint16_t)0x000A) |
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#define TIM_DMABase_ARR ((uint16_t)0x000B) |
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#define TIM_DMABase_RCR ((uint16_t)0x000C) |
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#define TIM_DMABase_CCR1 ((uint16_t)0x000D) |
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#define TIM_DMABase_CCR2 ((uint16_t)0x000E) |
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#define TIM_DMABase_CCR3 ((uint16_t)0x000F) |
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#define TIM_DMABase_CCR4 ((uint16_t)0x0010) |
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#define TIM_DMABase_BDTR ((uint16_t)0x0011) |
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#define TIM_DMABase_DCR ((uint16_t)0x0012) |
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/* TIM_DMA_Burst_Length */ |
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#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) |
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#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) |
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#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) |
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#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) |
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#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) |
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#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) |
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#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) |
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#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) |
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#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) |
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#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) |
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#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) |
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#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) |
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#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) |
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#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) |
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#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) |
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#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) |
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#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) |
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#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) |
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/* TIM_DMA_sources */ |
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#define TIM_DMA_Update ((uint16_t)0x0100) |
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#define TIM_DMA_CC1 ((uint16_t)0x0200) |
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#define TIM_DMA_CC2 ((uint16_t)0x0400) |
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#define TIM_DMA_CC3 ((uint16_t)0x0800) |
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#define TIM_DMA_CC4 ((uint16_t)0x1000) |
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#define TIM_DMA_COM ((uint16_t)0x2000) |
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#define TIM_DMA_Trigger ((uint16_t)0x4000) |
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/* TIM_External_Trigger_Prescaler */ |
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#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) |
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#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) |
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#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) |
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#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) |
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/* TIM_Internal_Trigger_Selection */ |
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#define TIM_TS_ITR0 ((uint16_t)0x0000) |
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#define TIM_TS_ITR1 ((uint16_t)0x0010) |
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#define TIM_TS_ITR2 ((uint16_t)0x0020) |
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#define TIM_TS_ITR3 ((uint16_t)0x0030) |
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#define TIM_TS_TI1F_ED ((uint16_t)0x0040) |
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#define TIM_TS_TI1FP1 ((uint16_t)0x0050) |
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#define TIM_TS_TI2FP2 ((uint16_t)0x0060) |
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#define TIM_TS_ETRF ((uint16_t)0x0070) |
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/* TIM_TIx_External_Clock_Source */ |
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#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) |
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#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) |
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#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) |
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/* TIM_External_Trigger_Polarity */ |
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#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) |
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#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) |
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/* TIM_Prescaler_Reload_Mode */ |
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#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) |
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#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) |
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/* TIM_Forced_Action */ |
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#define TIM_ForcedAction_Active ((uint16_t)0x0050) |
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#define TIM_ForcedAction_InActive ((uint16_t)0x0040) |
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/* TIM_Encoder_Mode */ |
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#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) |
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#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) |
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#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) |
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/* TIM_Event_Source */ |
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#define TIM_EventSource_Update ((uint16_t)0x0001) |
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#define TIM_EventSource_CC1 ((uint16_t)0x0002) |
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#define TIM_EventSource_CC2 ((uint16_t)0x0004) |
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#define TIM_EventSource_CC3 ((uint16_t)0x0008) |
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#define TIM_EventSource_CC4 ((uint16_t)0x0010) |
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#define TIM_EventSource_COM ((uint16_t)0x0020) |
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#define TIM_EventSource_Trigger ((uint16_t)0x0040) |
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#define TIM_EventSource_Break ((uint16_t)0x0080) |
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/* TIM_Update_Source */ |
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#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow |
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or the setting of UG bit, or an update generation |
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through the slave mode controller. */ |
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#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ |
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/* TIM_Output_Compare_Preload_State */ |
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#define TIM_OCPreload_Enable ((uint16_t)0x0008) |
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#define TIM_OCPreload_Disable ((uint16_t)0x0000) |
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/* TIM_Output_Compare_Fast_State */ |
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#define TIM_OCFast_Enable ((uint16_t)0x0004) |
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#define TIM_OCFast_Disable ((uint16_t)0x0000) |
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/* TIM_Output_Compare_Clear_State */ |
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#define TIM_OCClear_Enable ((uint16_t)0x0080) |
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#define TIM_OCClear_Disable ((uint16_t)0x0000) |
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/* TIM_Trigger_Output_Source */ |
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#define TIM_TRGOSource_Reset ((uint16_t)0x0000) |
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#define TIM_TRGOSource_Enable ((uint16_t)0x0010) |
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#define TIM_TRGOSource_Update ((uint16_t)0x0020) |
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#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) |
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#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) |
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#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) |
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#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) |
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#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) |
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/* TIM_Slave_Mode */ |
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#define TIM_SlaveMode_Reset ((uint16_t)0x0004) |
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#define TIM_SlaveMode_Gated ((uint16_t)0x0005) |
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#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) |
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#define TIM_SlaveMode_External1 ((uint16_t)0x0007) |
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/* TIM_Master_Slave_Mode */ |
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#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) |
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#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) |
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/* TIM_Flags */ |
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#define TIM_FLAG_Update ((uint16_t)0x0001) |
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#define TIM_FLAG_CC1 ((uint16_t)0x0002) |
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#define TIM_FLAG_CC2 ((uint16_t)0x0004) |
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#define TIM_FLAG_CC3 ((uint16_t)0x0008) |
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#define TIM_FLAG_CC4 ((uint16_t)0x0010) |
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#define TIM_FLAG_COM ((uint16_t)0x0020) |
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#define TIM_FLAG_Trigger ((uint16_t)0x0040) |
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#define TIM_FLAG_Break ((uint16_t)0x0080) |
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#define TIM_FLAG_CC1OF ((uint16_t)0x0200) |
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#define TIM_FLAG_CC2OF ((uint16_t)0x0400) |
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#define TIM_FLAG_CC3OF ((uint16_t)0x0800) |
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#define TIM_FLAG_CC4OF ((uint16_t)0x1000) |
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/* TIM_Legacy */ |
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#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer |
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#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers |
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#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers |
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#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers |
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#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers |
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#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers |
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#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers |
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#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers |
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#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers |
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#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers |
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#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers |
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#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers |
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#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers |
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#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers |
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#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers |
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#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers |
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#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers |
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#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers |
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void TIM_DeInit(TIM_TypeDef* TIMx); |
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void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); |
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void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); |
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void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); |
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void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); |
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void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); |
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void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); |
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void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); |
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void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); |
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void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); |
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void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); |
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void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); |
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void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); |
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void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); |
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void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); |
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void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); |
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void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); |
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void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); |
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void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); |
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void TIM_InternalClockConfig(TIM_TypeDef* TIMx); |
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void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); |
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void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, |
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uint16_t TIM_ICPolarity, uint16_t ICFilter); |
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void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, |
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uint16_t ExtTRGFilter); |
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void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, |
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uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); |
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void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, |
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uint16_t ExtTRGFilter); |
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void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); |
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void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); |
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void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); |
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void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, |
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uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); |
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void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); |
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void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); |
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void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); |
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void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); |
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void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); |
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void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); |
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void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); |
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void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); |
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void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); |
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void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); |
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void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); |
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void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); |
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void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); |
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void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); |
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void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); |
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void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); |
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void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); |
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void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); |
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void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); |
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void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); |
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void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); |
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void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); |
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void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); |
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void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); |
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void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); |
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void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); |
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void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); |
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void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); |
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void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); |
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void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); |
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void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); |
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void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); |
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void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); |
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void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); |
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void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); |
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void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); |
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void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); |
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void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter); |
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void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload); |
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void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1); |
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void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2); |
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void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3); |
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void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4); |
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void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); |
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void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); |
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void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); |
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void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); |
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void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); |
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uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx); |
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uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx); |
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uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx); |
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uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx); |
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uint16_t TIM_GetCounter(TIM_TypeDef* TIMx); |
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uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); |
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FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); |
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void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); |
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ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); |
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void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); |
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#ifdef __cplusplus |
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} |
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#endif |
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#endif |
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