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143 lines
6.6 KiB
143 lines
6.6 KiB
/** |
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* @file debug_cm.h |
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* @brief Access to ARM DAP (Cortex-M) using CMSIS-DAP protocol |
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*/ |
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#ifndef DEBUG_CM_H |
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#define DEBUG_CM_H |
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#include "DAP.h" |
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// Abort Register definitions |
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#define DAPABORT 0x00000001 // DAP Abort |
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#define STKCMPCLR 0x00000002 // Clear STICKYCMP Flag (SW Only) |
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#define STKERRCLR 0x00000004 // Clear STICKYERR Flag (SW Only) |
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#define WDERRCLR 0x00000008 // Clear WDATAERR Flag (SW Only) |
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#define ORUNERRCLR 0x00000010 // Clear STICKYORUN Flag (SW Only) |
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// Debug Control and Status definitions |
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#define ORUNDETECT 0x00000001 // Overrun Detect |
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#define STICKYORUN 0x00000002 // Sticky Overrun |
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#define TRNMODE 0x0000000C // Transfer Mode Mask |
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#define TRNNORMAL 0x00000000 // Transfer Mode: Normal |
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#define TRNVERIFY 0x00000004 // Transfer Mode: Pushed Verify |
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#define TRNCOMPARE 0x00000008 // Transfer Mode: Pushed Compare |
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#define STICKYCMP 0x00000010 // Sticky Compare |
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#define STICKYERR 0x00000020 // Sticky Error |
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#define READOK 0x00000040 // Read OK (SW Only) |
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#define WDATAERR 0x00000080 // Write Data Error (SW Only) |
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#define MASKLANE 0x00000F00 // Mask Lane Mask |
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#define MASKLANE0 0x00000100 // Mask Lane 0 |
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#define MASKLANE1 0x00000200 // Mask Lane 1 |
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#define MASKLANE2 0x00000400 // Mask Lane 2 |
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#define MASKLANE3 0x00000800 // Mask Lane 3 |
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#define TRNCNT 0x001FF000 // Transaction Counter Mask |
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#define CDBGRSTREQ 0x04000000 // Debug Reset Request |
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#define CDBGRSTACK 0x08000000 // Debug Reset Acknowledge |
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#define CDBGPWRUPREQ 0x10000000 // Debug Power-up Request |
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#define CDBGPWRUPACK 0x20000000 // Debug Power-up Acknowledge |
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#define CSYSPWRUPREQ 0x40000000 // System Power-up Request |
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#define CSYSPWRUPACK 0x80000000 // System Power-up Acknowledge |
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// Debug Select Register definitions |
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#define CTRLSEL 0x00000001 // CTRLSEL (SW Only) |
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#define APBANKSEL 0x000000F0 // APBANKSEL Mask |
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#define APSEL 0xFF000000 // APSEL Mask |
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// Access Port Register Addresses |
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#define AP_CSW 0x00 // Control and Status Word |
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#define AP_TAR 0x04 // Transfer Address |
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#define AP_DRW 0x0C // Data Read/Write |
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#define AP_BD0 0x10 // Banked Data 0 |
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#define AP_BD1 0x14 // Banked Data 1 |
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#define AP_BD2 0x18 // Banked Data 2 |
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#define AP_BD3 0x1C // Banked Data 3 |
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#define AP_ROM 0xF8 // Debug ROM Address |
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#define AP_IDR 0xFC // Identification Register |
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// AP Control and Status Word definitions |
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#define CSW_SIZE 0x00000007 // Access Size: Selection Mask |
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#define CSW_SIZE8 0x00000000 // Access Size: 8-bit |
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#define CSW_SIZE16 0x00000001 // Access Size: 16-bit |
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#define CSW_SIZE32 0x00000002 // Access Size: 32-bit |
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#define CSW_ADDRINC 0x00000030 // Auto Address Increment Mask |
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#define CSW_NADDRINC 0x00000000 // No Address Increment |
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#define CSW_SADDRINC 0x00000010 // Single Address Increment |
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#define CSW_PADDRINC 0x00000020 // Packed Address Increment |
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#define CSW_DBGSTAT 0x00000040 // Debug Status |
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#define CSW_TINPROG 0x00000080 // Transfer in progress |
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#define CSW_HPROT 0x02000000 // User/Privilege Control |
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#define CSW_MSTRTYPE 0x20000000 // Master Type Mask |
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#define CSW_MSTRCORE 0x00000000 // Master Type: Core |
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#define CSW_MSTRDBG 0x20000000 // Master Type: Debug |
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#define CSW_RESERVED 0x01000000 // Reserved Value |
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// Core Debug Register Address Offsets |
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#define DBG_OFS 0x0DF0 // Debug Register Offset inside NVIC |
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#define DBG_HCSR_OFS 0x00 // Debug Halting Control & Status Register |
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#define DBG_CRSR_OFS 0x04 // Debug Core Register Selector Register |
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#define DBG_CRDR_OFS 0x08 // Debug Core Register Data Register |
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#define DBG_EMCR_OFS 0x0C // Debug Exception & Monitor Control Register |
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// Core Debug Register Addresses |
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#define DBG_HCSR (DBG_Addr + DBG_HCSR_OFS) |
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#define DBG_CRSR (DBG_Addr + DBG_CRSR_OFS) |
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#define DBG_CRDR (DBG_Addr + DBG_CRDR_OFS) |
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#define DBG_EMCR (DBG_Addr + DBG_EMCR_OFS) |
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// Debug Halting Control and Status Register definitions |
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#define C_DEBUGEN 0x00000001 // Debug Enable |
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#define C_HALT 0x00000002 // Halt |
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#define C_STEP 0x00000004 // Step |
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#define C_MASKINTS 0x00000008 // Mask Interrupts |
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#define C_SNAPSTALL 0x00000020 // Snap Stall |
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#define S_REGRDY 0x00010000 // Register R/W Ready Flag |
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#define S_HALT 0x00020000 // Halt Flag |
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#define S_SLEEP 0x00040000 // Sleep Flag |
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#define S_LOCKUP 0x00080000 // Lockup Flag |
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#define S_RETIRE_ST 0x01000000 // Sticky Retire Flag |
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#define S_RESET_ST 0x02000000 // Sticky Reset Flag |
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#define DBGKEY 0xA05F0000 // Debug Key |
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// Debug Exception and Monitor Control Register definitions |
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#define VC_CORERESET 0x00000001 // Reset Vector Catch |
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#define VC_MMERR 0x00000010 // Debug Trap on MMU Fault |
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#define VC_NOCPERR 0x00000020 // Debug Trap on No Coprocessor Fault |
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#define VC_CHKERR 0x00000040 // Debug Trap on Checking Error Fault |
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#define VC_STATERR 0x00000080 // Debug Trap on State Error Fault |
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#define VC_BUSERR 0x00000100 // Debug Trap on Bus Error Fault |
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#define VC_INTERR 0x00000200 // Debug Trap on Interrupt Error Fault |
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#define VC_HARDERR 0x00000400 // Debug Trap on Hard Fault |
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#define MON_EN 0x00010000 // Monitor Enable |
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#define MON_PEND 0x00020000 // Monitor Pend |
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#define MON_STEP 0x00040000 // Monitor Step |
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#define MON_REQ 0x00080000 // Monitor Request |
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#define TRCENA 0x01000000 // Trace Enable (DWT, ITM, ETM, TPIU) |
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// NVIC: Interrupt Controller Type Register |
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#define NVIC_ICT (NVIC_Addr + 0x0004) |
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#define INTLINESNUM 0x0000001F // Interrupt Line Numbers |
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// NVIC: CPUID Base Register |
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#define NVIC_CPUID (NVIC_Addr + 0x0D00) |
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#define CPUID_PARTNO 0x0000FFF0 // Part Number Mask |
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#define CPUID_REVISION 0x0000000F // Revision Mask |
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#define CPUID_VARIANT 0x00F00000 // Variant Mask |
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// NVIC: Application Interrupt/Reset Control Register |
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#define NVIC_AIRCR (NVIC_Addr + 0x0D0C) |
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#define VECTRESET 0x00000001 // Reset Cortex-M (except Debug) |
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#define VECTCLRACTIVE 0x00000002 // Clear Active Vector Bit |
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#define SYSRESETREQ 0x00000004 // Reset System (except Debug) |
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#define VECTKEY 0x05FA0000 // Write Key |
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// NVIC: Debug Fault Status Register |
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#define NVIC_DFSR (NVIC_Addr + 0x0D30) |
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#define HALTED 0x00000001 // Halt Flag |
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#define BKPT 0x00000002 // BKPT Flag |
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#define DWTTRAP 0x00000004 // DWT Match |
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#define VCATCH 0x00000008 // Vector Catch Flag |
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#define EXTERNAL 0x00000010 // External Debug Request |
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#endif
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