mirror of https://github.com/XIVN1987/DAPLink
XIVN1987
1 year ago
parent
f403988e4f
commit
0b46bf88eb
24 changed files with 86 additions and 1755 deletions
@ -1,90 +0,0 @@ |
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/**
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* @file SWD_flash.c |
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* @brief Program target flash through SWD |
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*/ |
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#include "swd_host.h" |
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#include "SWD_flash.h" |
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extern const program_target_t flash_algo; |
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error_t target_flash_init(uint32_t flash_start, uint32_t func) |
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{ |
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if(func == 0) |
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{ |
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if (0 == swd_set_target_state_hw(RESET_PROGRAM)) { |
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return ERROR_RESET; |
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} |
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// Download flash programming algorithm to target and initialise.
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if (0 == swd_write_memory(flash_algo.algo_start, (uint8_t *)flash_algo.algo_blob, flash_algo.algo_size)) { |
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return ERROR_ALGO_DL; |
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} |
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} |
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else |
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{ |
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if (0 != swd_flash_syscall_exec(&flash_algo.sys_call_s, flash_algo.init, flash_start, 0, func, 0)) { |
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return ERROR_INIT; |
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} |
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} |
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return ERROR_SUCCESS; |
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} |
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error_t target_flash_uninit(uint32_t func) |
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{ |
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if (0 != swd_flash_syscall_exec(&flash_algo.sys_call_s, flash_algo.init, func, 0, 0, 0)) { |
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return ERROR_UNINIT; |
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} |
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return ERROR_SUCCESS; |
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} |
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error_t target_flash_program_page(uint32_t addr, const uint8_t *buf, uint32_t size) |
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{ |
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while (size > 0) { |
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uint32_t write_size = size > flash_algo.program_buffer_size ? flash_algo.program_buffer_size : size; |
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// Write page to buffer
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if (!swd_write_memory(flash_algo.program_buffer, (uint8_t *)buf, write_size)) { |
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return ERROR_ALGO_DATA_SEQ; |
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} |
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// Run flash programming
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if (swd_flash_syscall_exec(&flash_algo.sys_call_s, |
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flash_algo.program_page, |
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addr, |
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flash_algo.program_buffer_size, |
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flash_algo.program_buffer, |
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0)) { |
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return ERROR_WRITE; |
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} |
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addr += write_size; |
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buf += write_size; |
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size -= write_size; |
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} |
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return ERROR_SUCCESS; |
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} |
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error_t target_flash_erase_sector(uint32_t addr) |
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{ |
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if (0 != swd_flash_syscall_exec(&flash_algo.sys_call_s, flash_algo.erase_sector, addr, 0, 0, 0)) { |
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return ERROR_ERASE_SECTOR; |
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} |
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return ERROR_SUCCESS; |
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} |
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error_t target_flash_erase_chip(void) |
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{ |
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error_t status = ERROR_SUCCESS; |
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if (0 != swd_flash_syscall_exec(&flash_algo.sys_call_s, flash_algo.erase_chip, 0, 0, 0, 0)) { |
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return ERROR_ERASE_ALL; |
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} |
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return status; |
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} |
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@ -1,38 +0,0 @@ |
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#ifndef __SWD_FLASH_H__ |
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#define __SWD_FLASH_H__ |
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#include <stdint.h> |
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typedef enum { |
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/* Shared errors */ |
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ERROR_SUCCESS = 0, |
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ERROR_FAILURE, |
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ERROR_INTERNAL, |
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/* Target flash errors */ |
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ERROR_RESET, |
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ERROR_ALGO_DL, |
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ERROR_ALGO_DATA_SEQ, |
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ERROR_INIT, |
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ERROR_UNINIT, |
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ERROR_SECURITY_BITS, |
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ERROR_UNLOCK, |
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ERROR_ERASE_SECTOR, |
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ERROR_ERASE_ALL, |
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ERROR_WRITE, |
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// Add new values here
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ERROR_COUNT |
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} error_t; |
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error_t target_flash_init(uint32_t flash_start, uint32_t func); |
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error_t target_flash_uninit(uint32_t func); |
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error_t target_flash_program_page(uint32_t addr, const uint8_t *buf, uint32_t size); |
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error_t target_flash_erase_sector(uint32_t addr); |
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error_t target_flash_erase_chip(void); |
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#endif // __SWD_FLASH_H__
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File diff suppressed because it is too large
Load Diff
@ -1,39 +0,0 @@ |
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#ifndef SWDHOST_CM_H |
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#define SWDHOST_CM_H |
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#include <stdint.h> |
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#include "flash_blob.h" |
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typedef enum { |
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RESET_HOLD, // Hold target in reset
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RESET_PROGRAM, // Reset target and setup for flash programming.
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RESET_RUN, // Reset target and run normally
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NO_DEBUG, // Disable debug on running target
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DEBUG, // Enable debug on running target
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HALT, // Halt the target without resetting it
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RUN // Resume the target without resetting it
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} TARGET_RESET_STATE; |
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uint8_t swd_init(void); |
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uint8_t swd_off(void); |
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uint8_t swd_init_debug(void); |
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uint8_t swd_read_dp(uint8_t adr, uint32_t *val); |
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uint8_t swd_write_dp(uint8_t adr, uint32_t val); |
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uint8_t swd_read_ap(uint32_t adr, uint32_t *val); |
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uint8_t swd_write_ap(uint32_t adr, uint32_t val); |
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uint8_t swd_read_memory(uint32_t address, uint8_t *data, uint32_t size); |
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uint8_t swd_write_memory(uint32_t address, uint8_t *data, uint32_t size); |
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uint8_t swd_flash_syscall_exec(const program_syscall_t *sysCallParam, uint32_t entry, uint32_t arg1, uint32_t arg2, uint32_t arg3, uint32_t arg4); |
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void swd_set_target_reset(uint8_t asserted); |
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uint8_t swd_set_target_state_hw(TARGET_RESET_STATE state); |
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uint8_t swd_set_target_state_sw(TARGET_RESET_STATE state); |
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uint8_t swd_read_word(uint32_t addr, uint32_t *val); |
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uint8_t swd_write_word(uint32_t addr, uint32_t val); |
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#endif |
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@ -1,147 +0,0 @@ |
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/**
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* @file debug_ca.h |
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* @brief Access to ARM DAP (Cortex-A) using CMSIS-DAP protocol |
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* |
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* DAPLink Interface Firmware |
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* Copyright (c) 2009-2016, ARM Limited, All Rights Reserved |
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* SPDX-License-Identifier: Apache-2.0 |
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* |
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* Licensed under the Apache License, Version 2.0 (the "License"); you may |
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* not use this file except in compliance with the License. |
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* You may obtain a copy of the License at |
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* |
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* http://www.apache.org/licenses/LICENSE-2.0
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* |
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* Unless required by applicable law or agreed to in writing, software |
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT |
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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* See the License for the specific language governing permissions and |
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* limitations under the License. |
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*/ |
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#ifndef DEBUG_CA_H |
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#define DEBUG_CA_H |
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#include "debug_cm.h" |
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// Debug registers
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#define DEBUG_REGSITER_BASE (0x80030000) |
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#define DBGDIDR (DEBUG_REGSITER_BASE + (0 * 4)) // Debug ID
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#define DBGWFAR (DEBUG_REGSITER_BASE + (6 * 4)) // Watchpoint Fault Address
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#define DBGVCR (DEBUG_REGSITER_BASE + (7 * 4)) // Vector Catch
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#define DBGECR (DEBUG_REGSITER_BASE + (9 * 4)) // Event Catch
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#define DBGDTRRX (DEBUG_REGSITER_BASE + (32 * 4)) // Host to Target Data Transfer
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#define DBGITR (DEBUG_REGSITER_BASE + (33 * 4)) // WO Instruction Transfer
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#define DBGDSCR (DEBUG_REGSITER_BASE + (34 * 4)) // Debug Status and Control
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#define DBGDTRTX (DEBUG_REGSITER_BASE + (35 * 4)) // Target to Host Data Transfer
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#define DBGDRCR (DEBUG_REGSITER_BASE + (36 * 4)) // Debug Run Control
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#define DBGEACR (DEBUG_REGSITER_BASE + (37 * 4)) // External Auxiliary Control
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#define DBGPCSR (DEBUG_REGSITER_BASE + (40 * 4)) // Program Counter Sampling
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#define DBGCIDSR (DEBUG_REGSITER_BASE + (41 * 4)) // Context ID Sampling
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#define DBGVIDSR (DEBUG_REGSITER_BASE + (42 * 4)) // Virtualization ID Sampling
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#define DBGBVR0 (DEBUG_REGSITER_BASE + (64 * 4)) // Breakpoint Value
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#define DBGBVR1 (DEBUG_REGSITER_BASE + (65 * 4)) // Breakpoint Value
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#define DBGBVR2 (DEBUG_REGSITER_BASE + (66 * 4)) // Breakpoint Value
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#define DBGBVR3 (DEBUG_REGSITER_BASE + (67 * 4)) // Breakpoint Value
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#define DBGBVR4 (DEBUG_REGSITER_BASE + (68 * 4)) // Breakpoint Value
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#define DBGBVR5 (DEBUG_REGSITER_BASE + (69 * 4)) // Breakpoint Value
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#define DBGBVR6 (DEBUG_REGSITER_BASE + (70 * 4)) // Breakpoint Value
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#define DBGBVR7 (DEBUG_REGSITER_BASE + (71 * 4)) // Breakpoint Value
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#define DBGBVR8 (DEBUG_REGSITER_BASE + (72 * 4)) // Breakpoint Value
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#define DBGBVR9 (DEBUG_REGSITER_BASE + (73 * 4)) // Breakpoint Value
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#define DBGBVR10 (DEBUG_REGSITER_BASE + (74 * 4)) // Breakpoint Value
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#define DBGBVR11 (DEBUG_REGSITER_BASE + (75 * 4)) // Breakpoint Value
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#define DBGBVR12 (DEBUG_REGSITER_BASE + (76 * 4)) // Breakpoint Value
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#define DBGBVR13 (DEBUG_REGSITER_BASE + (77 * 4)) // Breakpoint Value
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#define DBGBVR14 (DEBUG_REGSITER_BASE + (78 * 4)) // Breakpoint Value
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#define DBGBVR15 (DEBUG_REGSITER_BASE + (79 * 4)) // Breakpoint Value
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#define DBGBCR0 (DEBUG_REGSITER_BASE + (80 * 4)) // Breakpoint Control
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#define DBGBCR1 (DEBUG_REGSITER_BASE + (81 * 4)) // Breakpoint Control
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#define DBGBCR2 (DEBUG_REGSITER_BASE + (82 * 4)) // Breakpoint Control
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#define DBGBCR3 (DEBUG_REGSITER_BASE + (83 * 4)) // Breakpoint Control
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#define DBGBCR4 (DEBUG_REGSITER_BASE + (84 * 4)) // Breakpoint Control
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#define DBGBCR5 (DEBUG_REGSITER_BASE + (85 * 4)) // Breakpoint Control
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#define DBGBCR6 (DEBUG_REGSITER_BASE + (86 * 4)) // Breakpoint Control
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#define DBGBCR7 (DEBUG_REGSITER_BASE + (87 * 4)) // Breakpoint Control
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#define DBGBCR8 (DEBUG_REGSITER_BASE + (88 * 4)) // Breakpoint Control
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#define DBGBCR9 (DEBUG_REGSITER_BASE + (89 * 4)) // Breakpoint Control
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#define DBGBCR10 (DEBUG_REGSITER_BASE + (90 * 4)) // Breakpoint Control
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#define DBGBCR11 (DEBUG_REGSITER_BASE + (91 * 4)) // Breakpoint Control
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#define DBGBCR12 (DEBUG_REGSITER_BASE + (92 * 4)) // Breakpoint Control
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#define DBGBCR13 (DEBUG_REGSITER_BASE + (93 * 4)) // Breakpoint Control
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#define DBGBCR14 (DEBUG_REGSITER_BASE + (94 * 4)) // Breakpoint Control
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#define DBGBCR15 (DEBUG_REGSITER_BASE + (95 * 4)) // Breakpoint Control
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#define DBGWVR0 (DEBUG_REGSITER_BASE + (96 * 4)) // Watchpoint Value
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#define DBGWVR1 (DEBUG_REGSITER_BASE + (97 * 4)) // Watchpoint Value
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#define DBGWVR2 (DEBUG_REGSITER_BASE + (98 * 4)) // Watchpoint Value
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#define DBGWVR3 (DEBUG_REGSITER_BASE + (99 * 4)) // Watchpoint Value
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#define DBGWVR4 (DEBUG_REGSITER_BASE + (100 * 4)) // Watchpoint Value
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#define DBGWVR5 (DEBUG_REGSITER_BASE + (101 * 4)) // Watchpoint Value
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#define DBGWVR6 (DEBUG_REGSITER_BASE + (102 * 4)) // Watchpoint Value
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#define DBGWVR7 (DEBUG_REGSITER_BASE + (103 * 4)) // Watchpoint Value
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#define DBGWVR8 (DEBUG_REGSITER_BASE + (104 * 4)) // Watchpoint Value
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#define DBGWVR9 (DEBUG_REGSITER_BASE + (105 * 4)) // Watchpoint Value
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#define DBGWVR10 (DEBUG_REGSITER_BASE + (106 * 4)) // Watchpoint Value
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#define DBGWVR11 (DEBUG_REGSITER_BASE + (107 * 4)) // Watchpoint Value
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#define DBGWVR12 (DEBUG_REGSITER_BASE + (108 * 4)) // Watchpoint Value
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#define DBGWVR13 (DEBUG_REGSITER_BASE + (109 * 4)) // Watchpoint Value
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#define DBGWVR14 (DEBUG_REGSITER_BASE + (110 * 4)) // Watchpoint Value
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#define DBGWVR15 (DEBUG_REGSITER_BASE + (111 * 4)) // Watchpoint Value
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#define DBGWCR0 (DEBUG_REGSITER_BASE + (112 * 4)) // Watchpoint Control
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#define DBGWCR1 (DEBUG_REGSITER_BASE + (113 * 4)) // Watchpoint Control
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#define DBGWCR2 (DEBUG_REGSITER_BASE + (114 * 4)) // Watchpoint Control
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#define DBGWCR3 (DEBUG_REGSITER_BASE + (115 * 4)) // Watchpoint Control
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#define DBGWCR4 (DEBUG_REGSITER_BASE + (116 * 4)) // Watchpoint Control
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#define DBGWCR5 (DEBUG_REGSITER_BASE + (117 * 4)) // Watchpoint Control
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#define DBGWCR6 (DEBUG_REGSITER_BASE + (118 * 4)) // Watchpoint Control
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#define DBGWCR7 (DEBUG_REGSITER_BASE + (119 * 4)) // Watchpoint Control
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#define DBGWCR8 (DEBUG_REGSITER_BASE + (120 * 4)) // Watchpoint Control
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#define DBGWCR9 (DEBUG_REGSITER_BASE + (121 * 4)) // Watchpoint Control
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#define DBGWCR10 (DEBUG_REGSITER_BASE + (122 * 4)) // Watchpoint Control
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#define DBGWCR11 (DEBUG_REGSITER_BASE + (123 * 4)) // Watchpoint Control
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#define DBGWCR12 (DEBUG_REGSITER_BASE + (124 * 4)) // Watchpoint Control
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#define DBGWCR13 (DEBUG_REGSITER_BASE + (125 * 4)) // Watchpoint Control
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#define DBGWCR14 (DEBUG_REGSITER_BASE + (126 * 4)) // Watchpoint Control
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#define DBGWCR15 (DEBUG_REGSITER_BASE + (127 * 4)) // Watchpoint Control
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#define DBGBXVR0 (DEBUG_REGSITER_BASE + (144 * 4)) // Breakpoint Extended Valueb
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#define DBGBXVR1 (DEBUG_REGSITER_BASE + (145 * 4)) // Breakpoint Extended Valueb
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#define DBGBXVR2 (DEBUG_REGSITER_BASE + (146 * 4)) // Breakpoint Extended Valueb
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#define DBGBXVR3 (DEBUG_REGSITER_BASE + (147 * 4)) // Breakpoint Extended Valueb
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#define DBGBXVR4 (DEBUG_REGSITER_BASE + (148 * 4)) // Breakpoint Extended Valueb
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#define DBGBXVR5 (DEBUG_REGSITER_BASE + (149 * 4)) // Breakpoint Extended Valueb
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#define DBGBXVR6 (DEBUG_REGSITER_BASE + (150 * 4)) // Breakpoint Extended Valueb
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#define DBGBXVR7 (DEBUG_REGSITER_BASE + (151 * 4)) // Breakpoint Extended Valueb
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#define DBGBXVR8 (DEBUG_REGSITER_BASE + (152 * 4)) // Breakpoint Extended Valueb
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#define DBGBXVR9 (DEBUG_REGSITER_BASE + (153 * 4)) // Breakpoint Extended Valueb
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#define DBGBXVR10 (DEBUG_REGSITER_BASE + (154 * 4)) // Breakpoint Extended Valueb
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#define DBGBXVR11 (DEBUG_REGSITER_BASE + (155 * 4)) // Breakpoint Extended Valueb
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#define DBGBXVR12 (DEBUG_REGSITER_BASE + (156 * 4)) // Breakpoint Extended Valueb
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#define DBGBXVR13 (DEBUG_REGSITER_BASE + (157 * 4)) // Breakpoint Extended Valueb
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#define DBGBXVR14 (DEBUG_REGSITER_BASE + (158 * 4)) // Breakpoint Extended Valueb
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#define DBGBXVR15 (DEBUG_REGSITER_BASE + (159 * 4)) // Breakpoint Extended Valueb
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#define DBGOSLAR (DEBUG_REGSITER_BASE + (192 * 4)) // OS Lock Access
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#define DBGOSLSR (DEBUG_REGSITER_BASE + (193 * 4)) // OS Lock Status
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#define DBGPRCR (DEBUG_REGSITER_BASE + (196 * 4)) // Powerdown and Reset Control
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#define DBGPRSR (DEBUG_REGSITER_BASE + (197 * 4)) // Powerdown and Reset Status
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#define DBGITCTRL (DEBUG_REGSITER_BASE + (960 * 4)) // Integration Mode Control
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#define DBGCLAIMSET (DEBUG_REGSITER_BASE + (1000 * 4)) // Claim Tag Set
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#define DBGCLAIMCLR (DEBUG_REGSITER_BASE + (1001 * 4)) // Claim Tag Clear
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#define DBGLAR (DEBUG_REGSITER_BASE + (1004 * 4)) // Lock Access
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#define DBGLSR (DEBUG_REGSITER_BASE + (1005 * 4)) // Lock Status
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#define DBGAUTHSTATUS (DEBUG_REGSITER_BASE + (1006 * 4)) // Authentication Status
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#define DBGDEVID2 (DEBUG_REGSITER_BASE + (1008 * 4)) // Debug Device ID 2
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#define DBGDEVID1 (DEBUG_REGSITER_BASE + (1009 * 4)) // Debug Device ID 1
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#define DBGDEVID (DEBUG_REGSITER_BASE + (1010 * 4)) // Debug Device ID
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#define DBGDEVTYPE (DEBUG_REGSITER_BASE + (1011 * 4)) // Device Type
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#define DBGPID0 (DEBUG_REGSITER_BASE + (1012 * 4)) // Debug Peripheral ID
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#define DBGPID1 (DEBUG_REGSITER_BASE + (1013 * 4)) // Debug Peripheral ID
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#define DBGPID2 (DEBUG_REGSITER_BASE + (1014 * 4)) // Debug Peripheral ID
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#define DBGPID3 (DEBUG_REGSITER_BASE + (1015 * 4)) // Debug Peripheral ID
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#define DBGPID4 (DEBUG_REGSITER_BASE + (1016 * 4)) // Debug Peripheral ID
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#define DBGCID0 (DEBUG_REGSITER_BASE + (1020 * 4)) // Debug Component ID
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#define DBGCID1 (DEBUG_REGSITER_BASE + (1021 * 4)) // Debug Component ID
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#define DBGCID2 (DEBUG_REGSITER_BASE + (1022 * 4)) // Debug Component ID
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#define DBGCID3 (DEBUG_REGSITER_BASE + (1023 * 4)) // Debug Component ID
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#endif |
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@ -1,168 +0,0 @@ |
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/**
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* @file debug_cm.h |
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* @brief Access to ARM DAP (Cortex-M) using CMSIS-DAP protocol |
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* |
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* DAPLink Interface Firmware |
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* Copyright (c) 2009-2016, ARM Limited, All Rights Reserved |
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* SPDX-License-Identifier: Apache-2.0 |
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* |
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* Licensed under the Apache License, Version 2.0 (the "License"); you may |
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* not use this file except in compliance with the License. |
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* You may obtain a copy of the License at |
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* |
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* http://www.apache.org/licenses/LICENSE-2.0
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* |
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* Unless required by applicable law or agreed to in writing, software |
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT |
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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* See the License for the specific language governing permissions and |
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* limitations under the License. |
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*/ |
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#ifndef DEBUG_CM_H |
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#define DEBUG_CM_H |
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#include "DAP.h" |
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// SWD register access
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#define SWD_REG_AP (1) |
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#define SWD_REG_DP (0) |
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#define SWD_REG_R (1<<1) |
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#define SWD_REG_W (0<<1) |
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#define SWD_REG_ADR(a) (a & 0x0c) |
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// Abort Register definitions
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#define DAPABORT 0x00000001 // DAP Abort
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#define STKCMPCLR 0x00000002 // Clear STICKYCMP Flag (SW Only)
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#define STKERRCLR 0x00000004 // Clear STICKYERR Flag (SW Only)
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#define WDERRCLR 0x00000008 // Clear WDATAERR Flag (SW Only)
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#define ORUNERRCLR 0x00000010 // Clear STICKYORUN Flag (SW Only)
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// Debug Control and Status definitions
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#define ORUNDETECT 0x00000001 // Overrun Detect
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#define STICKYORUN 0x00000002 // Sticky Overrun
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#define TRNMODE 0x0000000C // Transfer Mode Mask
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#define TRNNORMAL 0x00000000 // Transfer Mode: Normal
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#define TRNVERIFY 0x00000004 // Transfer Mode: Pushed Verify
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#define TRNCOMPARE 0x00000008 // Transfer Mode: Pushed Compare
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#define STICKYCMP 0x00000010 // Sticky Compare
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#define STICKYERR 0x00000020 // Sticky Error
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#define READOK 0x00000040 // Read OK (SW Only)
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#define WDATAERR 0x00000080 // Write Data Error (SW Only)
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#define MASKLANE 0x00000F00 // Mask Lane Mask
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#define MASKLANE0 0x00000100 // Mask Lane 0
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#define MASKLANE1 0x00000200 // Mask Lane 1
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#define MASKLANE2 0x00000400 // Mask Lane 2
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#define MASKLANE3 0x00000800 // Mask Lane 3
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#define TRNCNT 0x001FF000 // Transaction Counter Mask
|
||||
#define CDBGRSTREQ 0x04000000 // Debug Reset Request
|
||||
#define CDBGRSTACK 0x08000000 // Debug Reset Acknowledge
|
||||
#define CDBGPWRUPREQ 0x10000000 // Debug Power-up Request
|
||||
#define CDBGPWRUPACK 0x20000000 // Debug Power-up Acknowledge
|
||||
#define CSYSPWRUPREQ 0x40000000 // System Power-up Request
|
||||
#define CSYSPWRUPACK 0x80000000 // System Power-up Acknowledge
|
||||
|
||||
// Debug Select Register definitions
|
||||
#define CTRLSEL 0x00000001 // CTRLSEL (SW Only)
|
||||
#define APBANKSEL 0x000000F0 // APBANKSEL Mask
|
||||
#define APSEL 0xFF000000 // APSEL Mask
|
||||
|
||||
// Access Port Register Addresses
|
||||
#define AP_CSW 0x00 // Control and Status Word
|
||||
#define AP_TAR 0x04 // Transfer Address
|
||||
#define AP_DRW 0x0C // Data Read/Write
|
||||
#define AP_BD0 0x10 // Banked Data 0
|
||||
#define AP_BD1 0x14 // Banked Data 1
|
||||
#define AP_BD2 0x18 // Banked Data 2
|
||||
#define AP_BD3 0x1C // Banked Data 3
|
||||
#define AP_ROM 0xF8 // Debug ROM Address
|
||||
#define AP_IDR 0xFC // Identification Register
|
||||
|
||||
// AP Control and Status Word definitions
|
||||
#define CSW_SIZE 0x00000007 // Access Size: Selection Mask
|
||||
#define CSW_SIZE8 0x00000000 // Access Size: 8-bit
|
||||
#define CSW_SIZE16 0x00000001 // Access Size: 16-bit
|
||||
#define CSW_SIZE32 0x00000002 // Access Size: 32-bit
|
||||
#define CSW_ADDRINC 0x00000030 // Auto Address Increment Mask
|
||||
#define CSW_NADDRINC 0x00000000 // No Address Increment
|
||||
#define CSW_SADDRINC 0x00000010 // Single Address Increment
|
||||
#define CSW_PADDRINC 0x00000020 // Packed Address Increment
|
||||
#define CSW_DBGSTAT 0x00000040 // Debug Status
|
||||
#define CSW_TINPROG 0x00000080 // Transfer in progress
|
||||
#define CSW_HPROT 0x02000000 // User/Privilege Control
|
||||
#define CSW_MSTRTYPE 0x20000000 // Master Type Mask
|
||||
#define CSW_MSTRCORE 0x00000000 // Master Type: Core
|
||||
#define CSW_MSTRDBG 0x20000000 // Master Type: Debug
|
||||
#define CSW_RESERVED 0x01000000 // Reserved Value
|
||||
|
||||
// Core Debug Register Address Offsets
|
||||
#define DBG_OFS 0x0DF0 // Debug Register Offset inside NVIC
|
||||
#define DBG_HCSR_OFS 0x00 // Debug Halting Control & Status Register
|
||||
#define DBG_CRSR_OFS 0x04 // Debug Core Register Selector Register
|
||||
#define DBG_CRDR_OFS 0x08 // Debug Core Register Data Register
|
||||
#define DBG_EMCR_OFS 0x0C // Debug Exception & Monitor Control Register
|
||||
|
||||
// Core Debug Register Addresses
|
||||
#define DBG_HCSR (DBG_Addr + DBG_HCSR_OFS) |
||||
#define DBG_CRSR (DBG_Addr + DBG_CRSR_OFS) |
||||
#define DBG_CRDR (DBG_Addr + DBG_CRDR_OFS) |
||||
#define DBG_EMCR (DBG_Addr + DBG_EMCR_OFS) |
||||
|
||||
// Debug Halting Control and Status Register definitions
|
||||
#define C_DEBUGEN 0x00000001 // Debug Enable
|
||||
#define C_HALT 0x00000002 // Halt
|
||||
#define C_STEP 0x00000004 // Step
|
||||
#define C_MASKINTS 0x00000008 // Mask Interrupts
|
||||
#define C_SNAPSTALL 0x00000020 // Snap Stall
|
||||
#define S_REGRDY 0x00010000 // Register R/W Ready Flag
|
||||
#define S_HALT 0x00020000 // Halt Flag
|
||||
#define S_SLEEP 0x00040000 // Sleep Flag
|
||||
#define S_LOCKUP 0x00080000 // Lockup Flag
|
||||
#define S_RETIRE_ST 0x01000000 // Sticky Retire Flag
|
||||
#define S_RESET_ST 0x02000000 // Sticky Reset Flag
|
||||
#define DBGKEY 0xA05F0000 // Debug Key
|
||||
|
||||
// Debug Exception and Monitor Control Register definitions
|
||||
#define VC_CORERESET 0x00000001 // Reset Vector Catch
|
||||
#define VC_MMERR 0x00000010 // Debug Trap on MMU Fault
|
||||
#define VC_NOCPERR 0x00000020 // Debug Trap on No Coprocessor Fault
|
||||
#define VC_CHKERR 0x00000040 // Debug Trap on Checking Error Fault
|
||||
#define VC_STATERR 0x00000080 // Debug Trap on State Error Fault
|
||||
#define VC_BUSERR 0x00000100 // Debug Trap on Bus Error Fault
|
||||
#define VC_INTERR 0x00000200 // Debug Trap on Interrupt Error Fault
|
||||
#define VC_HARDERR 0x00000400 // Debug Trap on Hard Fault
|
||||
#define MON_EN 0x00010000 // Monitor Enable
|
||||
#define MON_PEND 0x00020000 // Monitor Pend
|
||||
#define MON_STEP 0x00040000 // Monitor Step
|
||||
#define MON_REQ 0x00080000 // Monitor Request
|
||||
#define TRCENA 0x01000000 // Trace Enable (DWT, ITM, ETM, TPIU)
|
||||
|
||||
// NVIC: Interrupt Controller Type Register
|
||||
#define NVIC_ICT (NVIC_Addr + 0x0004) |
||||
#define INTLINESNUM 0x0000001F // Interrupt Line Numbers
|
||||
|
||||
// NVIC: CPUID Base Register
|
||||
#define NVIC_CPUID (NVIC_Addr + 0x0D00) |
||||
#define CPUID_PARTNO 0x0000FFF0 // Part Number Mask
|
||||
#define CPUID_REVISION 0x0000000F // Revision Mask
|
||||
#define CPUID_VARIANT 0x00F00000 // Variant Mask
|
||||
|
||||
// NVIC: Application Interrupt/Reset Control Register
|
||||
#define NVIC_AIRCR (NVIC_Addr + 0x0D0C) |
||||
#define VECTRESET 0x00000001 // Reset Cortex-M (except Debug)
|
||||
#define VECTCLRACTIVE 0x00000002 // Clear Active Vector Bit
|
||||
#define SYSRESETREQ 0x00000004 // Reset System (except Debug)
|
||||
#define VECTKEY 0x05FA0000 // Write Key
|
||||
|
||||
// NVIC: Debug Fault Status Register
|
||||
#define NVIC_DFSR (NVIC_Addr + 0x0D30) |
||||
#define HALTED 0x00000001 // Halt Flag
|
||||
#define BKPT 0x00000002 // BKPT Flag
|
||||
#define DWTTRAP 0x00000004 // DWT Match
|
||||
#define VCATCH 0x00000008 // Vector Catch Flag
|
||||
#define EXTERNAL 0x00000010 // External Debug Request
|
||||
|
||||
// Data Watchpoint and Trace unit
|
||||
#define DWT_PCSR 0xe000101c // DWT PC Sampling Register
|
||||
|
||||
#endif |
||||
@ -1,33 +0,0 @@ |
||||
#ifndef FLASH_BLOB_H |
||||
#define FLASH_BLOB_H |
||||
|
||||
#include <stdint.h> |
||||
|
||||
|
||||
typedef struct { |
||||
uint32_t breakpoint; |
||||
uint32_t static_base; |
||||
uint32_t stack_pointer; |
||||
} program_syscall_t; |
||||
|
||||
typedef struct { |
||||
const uint32_t init; |
||||
const uint32_t uninit; |
||||
const uint32_t erase_chip; |
||||
const uint32_t erase_sector; |
||||
const uint32_t program_page; |
||||
const program_syscall_t sys_call_s; |
||||
const uint32_t program_buffer; |
||||
const uint32_t algo_start; |
||||
const uint32_t algo_size; |
||||
const uint32_t *algo_blob; |
||||
const uint32_t program_buffer_size; |
||||
} program_target_t; |
||||
|
||||
typedef struct { |
||||
const uint32_t start; |
||||
const uint32_t size; |
||||
} sector_info_t; |
||||
|
||||
|
||||
#endif |
||||
Loading…
Reference in new issue