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412 lines
24 KiB
412 lines
24 KiB
/********************************** (C) COPYRIGHT ******************************* |
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* File Name : ch32x035_usbpd.h |
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* Author : WCH |
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* Version : V1.0.0 |
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* Date : 2023/04/06 |
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* Description : This file contains all the functions prototypes for the USBPD |
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* firmware library. |
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********************************************************************************* |
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. |
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* Attention: This software (modified or not) and binary are used for |
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* microcontroller manufactured by Nanjing Qinheng Microelectronics. |
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*******************************************************************************/ |
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#ifndef __CH32X035_USBPD_H |
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#define __CH32X035_USBPD_H |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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#include "ch32x035.h" |
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#ifndef VOID |
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#define VOID void |
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#endif |
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#ifndef CONST |
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#define CONST const |
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#endif |
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#ifndef BOOL |
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typedef unsigned char BOOL; |
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#endif |
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#ifndef BOOLEAN |
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typedef unsigned char BOOLEAN; |
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#endif |
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#ifndef CHAR |
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typedef char CHAR; |
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#endif |
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#ifndef INT8 |
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typedef char INT8; |
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#endif |
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#ifndef INT16 |
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typedef short INT16; |
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#endif |
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#ifndef INT32 |
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typedef long INT32; |
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#endif |
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#ifndef UINT8 |
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typedef unsigned char UINT8; |
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#endif |
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#ifndef UINT16 |
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typedef unsigned short UINT16; |
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#endif |
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#ifndef UINT32 |
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typedef unsigned long UINT32; |
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#endif |
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#ifndef UINT8V |
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typedef unsigned char volatile UINT8V; |
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#endif |
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#ifndef UINT16V |
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typedef unsigned short volatile UINT16V; |
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#endif |
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#ifndef UINT32V |
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typedef unsigned long volatile UINT32V; |
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#endif |
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#ifndef PVOID |
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typedef void *PVOID; |
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#endif |
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#ifndef PCHAR |
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typedef char *PCHAR; |
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#endif |
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#ifndef PCHAR |
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typedef const char *PCCHAR; |
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#endif |
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#ifndef PINT8 |
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typedef char *PINT8; |
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#endif |
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#ifndef PINT16 |
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typedef short *PINT16; |
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#endif |
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#ifndef PINT32 |
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typedef long *PINT32; |
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#endif |
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#ifndef PUINT8 |
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typedef unsigned char *PUINT8; |
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#endif |
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#ifndef PUINT16 |
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typedef unsigned short *PUINT16; |
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#endif |
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#ifndef PUINT32 |
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typedef unsigned long *PUINT32; |
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#endif |
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#ifndef PUINT8V |
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typedef volatile unsigned char *PUINT8V; |
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#endif |
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#ifndef PUINT16V |
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typedef volatile unsigned short *PUINT16V; |
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#endif |
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#ifndef PUINT32V |
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typedef volatile unsigned long *PUINT32V; |
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#endif |
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/******************************************************************************/ |
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/* Related macro definitions */ |
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/* Define the return value of the function */ |
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#ifndef SUCCESS |
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#define SUCCESS 0 |
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#endif |
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#ifndef FAIL |
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#define FAIL 0xFF |
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#endif |
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/* Register Bit Definition */ |
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/* USBPD->CONFIG */ |
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#define PD_FILT_ED (1<<0) /* PD pin input filter enable */ |
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#define PD_ALL_CLR (1<<1) /* Clear all interrupt flags */ |
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#define CC_SEL (1<<2) /* Select PD communication port */ |
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#define PD_DMA_EN (1<<3) /* Enable DMA for USBPD */ |
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#define PD_RST_EN (1<<4) /* PD mode reset command enable */ |
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#define WAKE_POLAR (1<<5) /* PD port wake-up level */ |
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#define IE_PD_IO (1<<10) /* PD IO interrupt enable */ |
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#define IE_RX_BIT (1<<11) /* Receive bit interrupt enable */ |
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#define IE_RX_BYTE (1<<12) /* Receive byte interrupt enable */ |
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#define IE_RX_ACT (1<<13) /* Receive completion interrupt enable */ |
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#define IE_RX_RESET (1<<14) /* Reset interrupt enable */ |
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#define IE_TX_END (1<<15) /* Transfer completion interrupt enable */ |
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/* USBPD->CONTROL */ |
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#define PD_TX_EN (1<<0) /* USBPD transceiver mode and transmit enable */ |
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#define BMC_START (1<<1) /* BMC send start signal */ |
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#define RX_STATE_0 (1<<2) /* PD received state bit 0 */ |
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#define RX_STATE_1 (1<<3) /* PD received state bit 1 */ |
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#define RX_STATE_2 (1<<4) /* PD received state bit 2 */ |
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#define DATA_FLAG (1<<5) /* Cache data valid flag bit */ |
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#define TX_BIT_BACK (1<<6) /* Indicates the current bit status of the BMC when sending the code */ |
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#define BMC_BYTE_HI (1<<7) /* Indicates the current half-byte status of the PD data being sent and received */ |
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/* USBPD->TX_SEL */ |
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#define TX_SEL1 (0<<0) |
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#define TX_SEL1_SYNC1 (0<<0) /* 0-SYNC1 */ |
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#define TX_SEL1_RST1 (1<<0) /* 1-RST1 */ |
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#define TX_SEL2_Mask (3<<2) |
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#define TX_SEL2_SYNC1 (0<<2) /* 00-SYNC1 */ |
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#define TX_SEL2_SYNC3 (1<<2) /* 01-SYNC3 */ |
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#define TX_SEL2_RST1 (2<<2) /* 1x-RST1 */ |
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#define TX_SEL3_Mask (3<<4) |
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#define TX_SEL3_SYNC1 (0<<4) /* 00-SYNC1 */ |
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#define TX_SEL3_SYNC3 (1<<4) /* 01-SYNC3 */ |
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#define TX_SEL3_RST1 (2<<4) /* 1x-RST1 */ |
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#define TX_SEL4_Mask (3<<6) |
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#define TX_SEL4_SYNC2 (0<<6) /* 00-SYNC2 */ |
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#define TX_SEL4_SYNC3 (1<<6) /* 01-SYNC3 */ |
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#define TX_SEL4_RST2 (2<<6) /* 1x-RST2 */ |
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/* USBPD->STATUS */ |
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#define BMC_AUX_Mask (3<<0) /* Clear BMC auxiliary information */ |
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#define BMC_AUX_INVALID (0<<0) /* 00-Invalid */ |
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#define BMC_AUX_SOP0 (1<<0) /* 01-SOP0 */ |
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#define BMC_AUX_SOP1_HRST (2<<0) /* 10-SOP1 hard reset */ |
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#define BMC_AUX_SOP2_CRST (3<<0) /* 11-SOP2 cable reset */ |
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#define BUF_ERR (1<<2) /* BUFFER or DMA error interrupt flag */ |
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#define IF_RX_BIT (1<<3) /* Receive bit or 5bit interrupt flag */ |
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#define IF_RX_BYTE (1<<4) /* Receive byte or SOP interrupt flag */ |
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#define IF_RX_ACT (1<<5) /* Receive completion interrupt flag */ |
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#define IF_RX_RESET (1<<6) /* Receive reset interrupt flag */ |
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#define IF_TX_END (1<<7) /* Transfer completion interrupt flag */ |
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/* USBPD->PORT_CC1 */ |
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/* USBPD->PORT_CC2 */ |
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#define PA_CC_AI (1<<0) /* CC port comparator analogue input */ |
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#define CC_PD (1<<1) /* CC port pull-down resistor enable */ |
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#define CC_PU_Mask (3<<2) /* Clear CC port pull-up current */ |
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#define CC_NO_PU (0<<2) /* 00-Prohibit pull-up current */ |
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#define CC_PU_330 (1<<2) /* 01-330uA */ |
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#define CC_PU_180 (2<<2) /* 10-180uA */ |
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#define CC_PU_80 (3<<2) /* 11-80uA */ |
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#define CC_LVE (1<<4) /* CC port output low voltage enable */ |
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#define CC_CMP_Mask (7<<5) /* Clear CC_CMP*/ |
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#define CC_NO_CMP (0<<5) /* 000-closed */ |
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#define CC_CMP_22 (2<<5) /* 010-0.22V */ |
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#define CC_CMP_45 (3<<5) /* 011-0.45V */ |
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#define CC_CMP_55 (4<<5) /* 100-0.55V */ |
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#define CC_CMP_66 (5<<5) /* 101-0.66V */ |
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#define CC_CMP_95 (6<<5) /* 110-0.95V */ |
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#define CC_CMP_123 (7<<5) /* 111-1.23V */ |
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#define USBPD_IN_HVT (1<<9) |
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/********************************************************* |
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* PD pin PC14/PC15 high threshold input mode: |
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* 1-High threshold input (2.2V typical), to reduce the I/O power consumption during PD communication |
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* 0-Normal GPIO threshold input |
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* *******************************************************/ |
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#define USBPD_PHY_V33 (1<<8) |
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/********************************************************** |
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* PD transceiver PHY pull-up limit configuration bits: |
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* 1-Direct use of VDD for GPIO applications or PD applications with VDD voltage of 3.3V |
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* 0-LDO buck enabled, limited to approx 3.3V, for PD applications with VDD more than 4V |
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* ********************************************************/ |
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/* Control Message Types */ |
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#define DEF_TYPE_RESERVED 0x00 |
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#define DEF_TYPE_GOODCRC 0x01 /* Send By: Source,Sink,Cable Plug */ |
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#define DEF_TYPE_GOTOMIN 0x02 /* Send By: Source */ |
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#define DEF_TYPE_ACCEPT 0x03 /* Send By: Source,Sink,Cable Plug */ |
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#define DEF_TYPE_REJECT 0x04 /* Send By: Source,Sink,Cable Plug */ |
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#define DEF_TYPE_PING 0x05 /* Send By: Source */ |
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#define DEF_TYPE_PS_RDY 0x06 /* Send By: Source,Sink */ |
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#define DEF_TYPE_GET_SRC_CAP 0x07 /* Send By: Sink,DRP */ |
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#define DEF_TYPE_GET_SNK_CAP 0x08 /* Send By: Source,DRP */ |
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#define DEF_TYPE_DR_SWAP 0x09 /* Send By: Source,Sink */ |
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#define DEF_TYPE_PR_SWAP 0x0A /* Send By: Source,Sink */ |
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#define DEF_TYPE_VCONN_SWAP 0x0B /* Send By: Source,Sink */ |
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#define DEF_TYPE_WAIT 0x0C /* Send By: Source,Sink */ |
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#define DEF_TYPE_SOFT_RESET 0x0D /* Send By: Source,Sink */ |
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#define DEF_TYPE_DATA_RESET 0x0E /* Send By: Source,Sink */ |
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#define DEF_TYPE_DATA_RESET_CMP 0x0F /* Send By: Source,Sink */ |
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#define DEF_TYPE_NOT_SUPPORT 0x10 /* Send By: Source,Sink,Cable Plug */ |
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#define DEF_TYPE_GET_SRC_CAP_EX 0x11 /* Send By: Sink,DRP */ |
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#define DEF_TYPE_GET_STATUS 0x12 /* Send By: Source,Sink */ |
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#define DEF_TYPE_GET_STATUS_R 0X02 /* ext=1 */ |
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#define DEF_TYPE_FR_SWAP 0x13 /* Send By: Sink */ |
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#define DEF_TYPE_GET_PPS_STATUS 0x14 /* Send By: Sink */ |
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#define DEF_TYPE_GET_CTY_CODES 0x15 /* Send By: Source,Sink */ |
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#define DEF_TYPE_GET_SNK_CAP_EX 0x16 /* Send By: Source,DRP */ |
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#define DEF_TYPE_GET_SRC_INFO 0x17 /* Send By: Sink,DRP */ |
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#define DEF_TYPE_GET_REVISION 0x18 /* Send By: Source,Sink */ |
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/* Data Message Types */ |
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#define DEF_TYPE_SRC_CAP 0x01 /* Send By: Source,Dual-Role Power */ |
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#define DEF_TYPE_REQUEST 0x02 /* Send By: Sink */ |
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#define DEF_TYPE_BIST 0x03 /* Send By: Tester,Source,Sink */ |
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#define DEF_TYPE_SNK_CAP 0x04 /* Send By: Sink,Dual-Role Power */ |
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#define DEF_TYPE_BAT_STATUS 0x05 /* Send By: Source,Sink */ |
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#define DEF_TYPE_ALERT 0x06 /* Send By: Source,Sink */ |
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#define DEF_TYPE_GET_CTY_INFO 0x07 /* Send By: Source,Sink */ |
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#define DEF_TYPE_ENTER_USB 0x08 /* Send By: DFP */ |
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#define DEF_TYPE_EPR_REQUEST 0x09 /* Send By: Sink */ |
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#define DEF_TYPE_EPR_MODE 0x0A /* Send By: Source,Sink */ |
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#define DEF_TYPE_SRC_INFO 0x0B /* Send By: Source */ |
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#define DEF_TYPE_REVISION 0x0C /* Send By: Source,Sink,Cable Plug */ |
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#define DEF_TYPE_VENDOR_DEFINED 0x0F /* Send By: Source,Sink,Cable Plug */ |
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/* Vendor Define Message Command */ |
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#define DEF_VDM_DISC_IDENT 0x01 |
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#define DEF_VDM_DISC_SVID 0x02 |
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#define DEF_VDM_DISC_MODE 0x03 |
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#define DEF_VDM_ENTER_MODE 0x04 |
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#define DEF_VDM_EXIT_MODE 0x05 |
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#define DEF_VDM_ATTENTION 0x06 |
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#define DEF_VDM_DP_S_UPDATE 0x10 |
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#define DEF_VDM_DP_CONFIG 0x11 |
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/* PD Revision */ |
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#define DEF_PD_REVISION_10 0x00 |
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#define DEF_PD_REVISION_20 0x01 |
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#define DEF_PD_REVISION_30 0x02 |
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/* PD PHY Channel */ |
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#define DEF_PD_CC1 0x00 |
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#define DEF_PD_CC2 0x01 |
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#define PIN_CC1 GPIO_Pin_14 |
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#define PIN_CC2 GPIO_Pin_15 |
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/* PD Tx Status */ |
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#define DEF_PD_TX_OK 0x00 |
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#define DEF_PD_TX_FAIL 0x01 |
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/* PDO INDEX */ |
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#define PDO_INDEX_1 1 |
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#define PDO_INDEX_2 2 |
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#define PDO_INDEX_3 3 |
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#define PDO_INDEX_4 4 |
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#define PDO_INDEX_5 5 |
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/******************************************************************************/ |
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#define UPD_TMR_TX_48M (80-1) /* timer value for USB PD BMC transmittal @Fsys=48MHz */ |
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#define UPD_TMR_RX_48M (120-1) /* timer value for USB PD BMC receiving @Fsys=48MHz */ |
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#define UPD_TMR_TX_24M (40-1) /* timer value for USB PD BMC transmittal @Fsys=24MHz */ |
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#define UPD_TMR_RX_24M (60-1) /* timer value for USB PD BMC receiving @Fsys=24MHz */ |
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#define UPD_TMR_TX_12M (20-1) /* timer value for USB PD BMC transmittal @Fsys=12MHz */ |
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#define UPD_TMR_RX_12M (30-1) /* timer value for USB PD BMC receiving @Fsys=12MHz */ |
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#define MASK_PD_STAT 0x03 /* Bit mask for current PD status */ |
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#define PD_RX_SOP0 0x01 /* SOP0 received */ |
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#define PD_RX_SOP1_HRST 0x02 /* SOP1 or Hard Reset received */ |
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#define PD_RX_SOP2_CRST 0x03 /* SOP2 or Cable Reset received */ |
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#define UPD_SOP0 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC1 | TX_SEL4_SYNC2 ) /* SOP1 */ |
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#define UPD_SOP1 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC3 | TX_SEL4_SYNC3 ) /* SOP2 */ |
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#define UPD_SOP2 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC3 | TX_SEL3_SYNC1 | TX_SEL4_SYNC3 ) /* SOP3 */ |
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#define UPD_HARD_RESET ( TX_SEL1_RST1 | TX_SEL2_RST1 | TX_SEL3_RST1 | TX_SEL4_RST2 ) /* Hard Reset*/ |
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#define UPD_CABLE_RESET ( TX_SEL1_RST1 | TX_SEL2_SYNC1 | TX_SEL3_RST1 | TX_SEL4_SYNC3 ) /* Cable Reset*/ |
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#define bCC_CMP_22 0X01 |
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#define bCC_CMP_45 0X02 |
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#define bCC_CMP_55 0X04 |
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#define bCC_CMP_66 0X08 |
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#define bCC_CMP_95 0X10 |
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#define bCC_CMP_123 0X20 |
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#define bCC_CMP_220 0X40 |
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/******************************************************************************/ |
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/* PD State Machine */ |
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typedef enum |
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{ |
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STA_IDLE = 0, /* 0: No task status */ |
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STA_DISCONNECT, /* 1: Disconnection */ |
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STA_SRC_CONNECT, /* 2: SRC connect */ |
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STA_RX_SRC_CAP_WAIT, /* 3: Waiting to receive SRC_CAP */ |
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STA_RX_SRC_CAP, /* 4: SRC_CAP received */ |
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STA_TX_REQ, /* 5: Send REQUEST */ |
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STA_RX_ACCEPT_WAIT, /* 6: Waiting to receive ACCEPT */ |
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STA_RX_ACCEPT, /* 7: ACCEPT received */ |
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STA_RX_REJECT, /* 8: REJECT received */ |
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STA_RX_PS_RDY_WAIT, /* 9: Waiting to receive PS_RDY */ |
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STA_RX_PS_RDY, /* 10: PS_RDY received */ |
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STA_SINK_CONNECT, /* 11: SNK access */ |
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STA_TX_SRC_CAP, /* 12: Send SRC_CAP */ |
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STA_RX_REQ_WAIT, /* 13: Waiting to receive REQUEST */ |
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STA_RX_REQ, /* 14: REQUEST received */ |
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STA_TX_ACCEPT, /* 15: Send ACCEPT */ |
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STA_TX_REJECT, /* 16: Send REJECT */ |
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STA_ADJ_VOL, /* 17: Adjustment of output voltage and current */ |
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STA_TX_PS_RDY, /* 18: Send PS_RDY */ |
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STA_TX_DR_SWAP, /* 19: Send DR_SWAP */ |
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STA_RX_DR_SWAP_ACCEPT, /* 20: Waiting to receive the answer ACCEPT from DR_SWAP */ |
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STA_TX_PR_SWAP, /* 21: Send PR_SWAP */ |
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STA_RX_PR_SWAP_ACCEPT, /* 22: Waiting to receive the answer ACCEPT from PR_SWAP */ |
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STA_RX_PR_SWAP_PS_RDY, /* 23: Waiting to receive the answer PS_RDY from PR_SWAP */ |
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STA_TX_PR_SWAP_PS_RDY, /* 24: Send answer PS_RDY for PR_SWAP */ |
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STA_PR_SWAP_RECON_WAIT, /* 25: Wait for PR_SWAP before reconnecting */ |
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STA_SRC_RECON_WAIT, /* 26: Waiting for SRC to reconnect */ |
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STA_SINK_RECON_WAIT, /* 27: Waiting for SNK to reconnect */ |
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STA_RX_APD_PS_RDY_WAIT, /* 28: Waiting for PS_RDY from the receiving adapter */ |
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STA_RX_APD_PS_RDY, /* 29: PS_RDY received from the adapter */ |
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STA_MODE_SWITCH, /* 30: Mode switching */ |
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STA_TX_SOFTRST, /* 31: Sending a software reset */ |
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STA_TX_HRST, /* 32: Send hardware reset */ |
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STA_PHY_RST, /* 33: PHY reset */ |
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STA_APD_IDLE_WAIT, /* 34: Waiting for the adapter to become idle */ |
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} CC_STATUS; |
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/******************************************************************************/ |
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/* PD Message Header Struct */ |
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typedef union |
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{ |
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struct _Message_Header |
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{ |
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UINT8 MsgType: 5; /* Message Type */ |
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UINT8 PDRole: 1; /* 0-UFP; 1-DFP */ |
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UINT8 SpecRev: 2; /* 00-Rev1.0; 01-Rev2.0; 10-Rev3.0; */ |
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UINT8 PRRole: 1; /* 0-Sink; 1-Source */ |
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UINT8 MsgID: 3; |
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UINT8 NumDO: 3; |
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UINT8 Ext: 1; |
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}Message_Header; |
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UINT16 Data; |
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}_Message_Header; |
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/******************************************************************************/ |
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/* Bit definition */ |
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typedef union |
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{ |
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struct _BITS_ |
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{ |
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UINT8 Msg_Recvd: 1; /* Notify the main program of the receipt of a PD packet */ |
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UINT8 Connected: 1; /* PD Physical Layer Connected Flag */ |
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UINT8 Stop_Det_Chk: 1; /* 0-Enable detection; 1-Disable disconnection detection */ |
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UINT8 PD_Role: 1; /* 0-UFP; 1-DFP */ |
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UINT8 PR_Role: 1; /* 0-Sink; 1-Source */ |
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UINT8 Auto_Ack_PRRole: 1; /* Role used by auto-responder 0:SINK; 1:SOURCE */ |
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UINT8 PD_Version: 1; /* PD version 0-PD2.0; 1-PD3.0 */ |
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UINT8 VDM_Version: 1; /* VDM Version 0-1.0 1-2.0 */ |
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UINT8 HPD_Connected: 1; /* HPD Physical Layer Connected Flag */ |
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UINT8 HPD_Det_Chk: 1; /* 0-turn off HPD connection detection; 1-turn on HPD connection detection */ |
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UINT8 CC_Sel_En: 1; /* 0-CC channel selection toggle enable; 1-CC channel selection toggle disable */ |
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UINT8 CC_Sel_State: 1; /* 0-CC channel selection switches to 0; 1-CC channel selection switches to 1 */ |
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UINT8 PD_Comm_Succ: 1; /* 0-PD communication unsuccessful; 1-PD communication successful; */ |
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UINT8 Recv: 3; |
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}Bit; |
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UINT16 Bit_Flag; |
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}_BIT_FLAG; |
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/* PD control-related structures */ |
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typedef struct _PD_CONTROL |
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{ |
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CC_STATUS PD_State; /* PD communication status machine */ |
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CC_STATUS PD_State_Last; /* PD communication status machine (last value) */ |
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UINT8 Msg_ID; /* ID of the message sent */ |
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UINT8 Det_Timer; /* PD connection status detection timing */ |
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UINT8 Det_Cnt; /* Number of PD connection status detections */ |
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UINT8 Det_Sel_Cnt; /* Number of SEL toggles for PD connection status detection */ |
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UINT8 HPD_Det_Timer; /* HPD connection detection timing */ |
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UINT8 HPD_Det_Cnt; /* HPD pin connection status detection count */ |
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UINT16 PD_Comm_Timer; /* PD shared timing variables */ |
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UINT8 ReqPDO_Idx; /* Index of the requested PDO, valid values 1-7 */ |
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UINT16 PD_BusIdle_Timer; /* Bus Idle Time Timer */ |
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UINT8 Mode_Try_Cnt; /* Number of retries for current mode, highest bit marks mode */ |
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UINT8 Err_Op_Cnt; /* Exception operation count */ |
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UINT8 Adapter_Idle_Cnt; /* Adapter communication idle timing */ |
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_BIT_FLAG Flag; /* Flag byte bit definition */ |
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}PD_CONTROL, *pPD_CONTROL; |
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#ifdef __cplusplus |
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} |
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#endif |
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#endif
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