diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..c28ff38 --- /dev/null +++ b/.gitignore @@ -0,0 +1,24 @@ +build/ +*.bak +*.ddk +*.edk +*.lst +*.lnp +*.mpf +*.mpj +*.obj +*.omf +*.plg +*.rpt +*.tmp +*.__i +*.crf +*.o +*.d +*.axf +*.tra +*.dep +JLinkLog.txt +*.iex +*.htm +*.map \ No newline at end of file diff --git a/Code/CH32X035RM.PDF b/Code/CH32X035RM.PDF new file mode 100644 index 0000000..99dbc39 Binary files /dev/null and b/Code/CH32X035RM.PDF differ diff --git a/Code/DAP_X033/.cproject b/Code/DAP_X033/.cproject new file mode 100644 index 0000000..3cb0c87 --- /dev/null +++ b/Code/DAP_X033/.cproject @@ -0,0 +1,152 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Code/DAP_X033/.project b/Code/DAP_X033/.project new file mode 100644 index 0000000..197fab6 --- /dev/null +++ b/Code/DAP_X033/.project @@ -0,0 +1,34 @@ + + + DAP_X033 + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 1595986042669 + + 22 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-*.wvproj + + + + diff --git a/Code/DAP_X033/.settings/language.settings.xml b/Code/DAP_X033/.settings/language.settings.xml new file mode 100644 index 0000000..723130d --- /dev/null +++ b/Code/DAP_X033/.settings/language.settings.xml @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/Code/DAP_X033/.settings/org.eclipse.cdt.codan.core.prefs b/Code/DAP_X033/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 0000000..067d6fd --- /dev/null +++ b/Code/DAP_X033/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,73 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.codan.checkers.errnoreturn=Warning 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+org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Symbol is not resolved\\")"} diff --git a/Code/DAP_X033/.settings/org.eclipse.core.resources.prefs b/Code/DAP_X033/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 0000000..66208b1 --- /dev/null +++ b/Code/DAP_X033/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +encoding//DAP/CherryUSB/port/ch32/usb_ch58x_dc_usbfs.c=UTF-8 diff --git a/Code/DAP_X033/.template b/Code/DAP_X033/.template new file mode 100644 index 0000000..9e9b728 --- /dev/null +++ b/Code/DAP_X033/.template @@ -0,0 +1,16 @@ +Mcu Type=CH32X033 +Address=0x08000000 +Target Path=obj/DAP_X033.hex +Erase All=true +Program=true +Verify=true +Reset=true + +Vendor=WCH +Link=WCH-Link +Toolchain=RISC-V +Series=CH32X035 +Description=ROM(byte): 62K, SRAM(byte): 20K, CHIP PINS: 48, GPIO PORTS: 46.\nWCH CH32X033 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools. + +PeripheralVersion=1.4 +MCU=CH32X033F8P6 diff --git a/Code/DAP_X033/.vscode/settings.json b/Code/DAP_X033/.vscode/settings.json new file mode 100644 index 0000000..e03748c --- /dev/null +++ b/Code/DAP_X033/.vscode/settings.json @@ -0,0 +1,11 @@ +{ + "files.associations": { + "ch32x035.h": "c", + "usb_desc.h": "c", + "led.h": "c", + "usart.h": "c", + "cdc_main.h": "c", + "buffer.h": "c", + "main.h": "c" + } +} \ No newline at end of file diff --git a/Code/DAP_X033/Core/core_riscv.c b/Code/DAP_X033/Core/core_riscv.c new file mode 100644 index 0000000..95394a5 --- /dev/null +++ b/Code/DAP_X033/Core/core_riscv.c @@ -0,0 +1,307 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : core_riscv.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/06/06 + * Description : RISC-V Core Peripheral Access Layer Source File +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /* asm keyword for ARM Compiler */ + #define __INLINE __inline /* inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /* asm keyword for IAR Compiler */ + #define __INLINE inline /* inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /* asm keyword for GNU Compiler */ + #define __INLINE inline /* inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /* asm keyword for TASKING Compiler */ + #define __INLINE inline /* inline keyword for TASKING Compiler */ + +#endif + + + +/********************************************************************* + * @fn __get_MSTATUS + * + * @brief Return the Machine Status Register + * + * @return mstatus value + */ +uint32_t __get_MSTATUS(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mstatus" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MSTATUS + * + * @brief Set the Machine Status Register + * + * @param value - set mstatus value + * + * @return none + */ +void __set_MSTATUS(uint32_t value) +{ + __ASM volatile ("csrw mstatus, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MISA + * + * @brief Return the Machine ISA Register + * + * @return misa value + */ +uint32_t __get_MISA(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "misa" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MISA + * + * @brief Set the Machine ISA Register + * + * @param value - set misa value + * + * @return none + */ +void __set_MISA(uint32_t value) +{ + __ASM volatile ("csrw misa, %0" : : "r" (value) ); +} + + +/********************************************************************* + * @fn __get_MTVEC + * + * @brief Return the Machine Trap-Vector Base-Address Register + * + * @return mtvec value + */ +uint32_t __get_MTVEC(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mtvec" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MTVEC + * + * @brief Set the Machine Trap-Vector Base-Address Register + * + * @param value - set mtvec value + * + * @return none + */ +void __set_MTVEC(uint32_t value) +{ + __ASM volatile ("csrw mtvec, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MSCRATCH + * + * @brief Return the Machine Seratch Register + * + * @return mscratch value + */ +uint32_t __get_MSCRATCH(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mscratch" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MSCRATCH + * + * @brief Set the Machine Seratch Register + * + * @param value - set mscratch value + * + * @return none + */ +void __set_MSCRATCH(uint32_t value) +{ + __ASM volatile ("csrw mscratch, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MEPC + * + * @brief Return the Machine Exception Program Register + * + * @return mepc value + */ +uint32_t __get_MEPC(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mepc" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Exception Program Register + * + * @return mepc value + */ +void __set_MEPC(uint32_t value) +{ + __ASM volatile ("csrw mepc, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MCAUSE + * + * @brief Return the Machine Cause Register + * + * @return mcause value + */ +uint32_t __get_MCAUSE(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mcause" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Cause Register + * + * @return mcause value + */ +void __set_MCAUSE(uint32_t value) +{ + __ASM volatile ("csrw mcause, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MTVAL + * + * @brief Return the Machine Trap Value Register + * + * @return mtval value + */ +uint32_t __get_MTVAL(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mtval" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MTVAL + * + * @brief Set the Machine Trap Value Register + * + * @return mtval value + */ +void __set_MTVAL(uint32_t value) +{ + __ASM volatile ("csrw mtval, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MVENDORID + * + * @brief Return Vendor ID Register + * + * @return mvendorid value + */ +uint32_t __get_MVENDORID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MARCHID + * + * @brief Return Machine Architecture ID Register + * + * @return marchid value + */ +uint32_t __get_MARCHID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "marchid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MIMPID + * + * @brief Return Machine Implementation ID Register + * + * @return mimpid value + */ +uint32_t __get_MIMPID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mimpid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MHARTID + * + * @brief Return Hart ID Register + * + * @return mhartid value + */ +uint32_t __get_MHARTID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mhartid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_SP + * + * @brief Return SP Register + * + * @return SP value + */ +uint32_t __get_SP(void) +{ + uint32_t result; + + __ASM volatile ( "mv %0," "sp" : "=r"(result) : ); + return (result); +} + diff --git a/Code/DAP_X033/Core/core_riscv.h b/Code/DAP_X033/Core/core_riscv.h new file mode 100644 index 0000000..472bca7 --- /dev/null +++ b/Code/DAP_X033/Core/core_riscv.h @@ -0,0 +1,578 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : core_riscv.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/06/06 + * Description : RISC-V Core Peripheral Access Layer Header File for CH32X035 +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CORE_RISCV_H__ +#define __CORE_RISCV_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* IO definitions */ +#ifdef __cplusplus + #define __I volatile /* defines 'read only' permissions */ +#else + #define __I volatile const /* defines 'read only' permissions */ +#endif +#define __O volatile /* defines 'write only' permissions */ +#define __IO volatile /* defines 'read / write' permissions */ + +/* Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef __I uint64_t vuc64; /* Read Only */ +typedef __I uint32_t vuc32; /* Read Only */ +typedef __I uint16_t vuc16; /* Read Only */ +typedef __I uint8_t vuc8; /* Read Only */ + +typedef const uint64_t uc64; /* Read Only */ +typedef const uint32_t uc32; /* Read Only */ +typedef const uint16_t uc16; /* Read Only */ +typedef const uint8_t uc8; /* Read Only */ + +typedef __I int64_t vsc64; /* Read Only */ +typedef __I int32_t vsc32; /* Read Only */ +typedef __I int16_t vsc16; /* Read Only */ +typedef __I int8_t vsc8; /* Read Only */ + +typedef const int64_t sc64; /* Read Only */ +typedef const int32_t sc32; /* Read Only */ +typedef const int16_t sc16; /* Read Only */ +typedef const int8_t sc8; /* Read Only */ + +typedef __IO uint64_t vu64; +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef uint64_t u64; +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef __IO int64_t vs64; +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef int64_t s64; +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +#define RV_STATIC_INLINE static inline + +/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ +typedef struct{ + __I uint32_t ISR[8]; + __I uint32_t IPR[8]; + __IO uint32_t ITHRESDR; + __IO uint32_t RESERVED; + __IO uint32_t CFGR; + __I uint32_t GISR; + __IO uint8_t VTFIDR[4]; + uint8_t RESERVED0[12]; + __IO uint32_t VTFADDR[4]; + uint8_t RESERVED1[0x90]; + __O uint32_t IENR[8]; + uint8_t RESERVED2[0x60]; + __O uint32_t IRER[8]; + uint8_t RESERVED3[0x60]; + __O uint32_t IPSR[8]; + uint8_t RESERVED4[0x60]; + __O uint32_t IPRR[8]; + uint8_t RESERVED5[0x60]; + __IO uint32_t IACTR[8]; + uint8_t RESERVED6[0xE0]; + __IO uint8_t IPRIOR[256]; + uint8_t RESERVED7[0x810]; + __IO uint32_t SCTLR; +}PFIC_Type; + +/* memory mapped structure for SysTick */ +typedef struct +{ + __IO u32 CTLR; + __IO u32 SR; + __IO u64 CNT; + __IO u64 CMP; +}SysTick_Type; + + +#define PFIC ((PFIC_Type *) 0xE000E000 ) +#define NVIC PFIC +#define NVIC_KEY1 ((uint32_t)0xFA050000) +#define NVIC_KEY2 ((uint32_t)0xBCAF0000) +#define NVIC_KEY3 ((uint32_t)0xBEEF0000) +#define SysTick ((SysTick_Type *) 0xE000F000) + + +/********************************************************************* + * @fn __enable_irq + * + * @brief Enable Global Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq() +{ + __asm volatile ("csrw 0x800, %0" : : "r" (0x6088) ); +} + +/********************************************************************* + * @fn __disable_irq + * + * @brief Disable Global Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq() +{ + __asm volatile ("csrw 0x800, %0" : : "r" (0x6000) ); +} + +/********************************************************************* + * @fn __NOP + * + * @brief nop + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __NOP() +{ + __asm volatile ("nop"); +} + +/********************************************************************* + * @fn NVIC_EnableIRQ + * + * @brief Enable Interrupt + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_DisableIRQ + * + * @brief Disable Interrupt + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_GetStatusIRQ + * + * @brief Get Interrupt Enable State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Pending Enable + * 0 - Interrupt Pending Disable + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_GetPendingIRQ + * + * @brief Get Interrupt Pending State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Pending Enable + * 0 - Interrupt Pending Disable + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_SetPendingIRQ + * + * @brief Set Interrupt Pending + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_ClearPendingIRQ + * + * @brief Clear Interrupt Pending + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_GetActive + * + * @brief Get Interrupt Active State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Active + * 0 - Interrupt No Active + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_SetPriority + * + * @brief Set Interrupt Priority + * + * @param IRQn - Interrupt Numbers + * priority: bit[7] - pre-emption priority + * bit[6:5] - subpriority + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority) +{ + NVIC->IPRIOR[(uint32_t)(IRQn)] = priority; +} + +/********************************************************************* + * @fn __WFI + * + * @brief Wait for Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void) +{ + NVIC->SCTLR &= ~(1<<3); // wfi + asm volatile ("wfi"); +} + +/********************************************************************* + * @fn _SEV + * + * @brief Set Event + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void) +{ + uint32_t t; + + t = NVIC->SCTLR; + NVIC->SCTLR |= (1<<3)|(1<<5); + NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5)); +} + +/********************************************************************* + * @fn _WFE + * + * @brief Wait for Events + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void) +{ + NVIC->SCTLR |= (1<<3); + asm volatile ("wfi"); +} + +/********************************************************************* + * @fn __WFE + * + * @brief Wait for Events + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void) +{ + _SEV(); + _WFE(); + _WFE(); +} + +/********************************************************************* + * @fn SetVTFIRQ + * + * @brief Set VTF Interrupt + * + * @param addr - VTF interrupt service function base address. + * IRQn - Interrupt Numbers + * num - VTF Interrupt Numbers + * NewState - DISABLE or ENABLE + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState){ + if(num > 3) return ; + + if (NewState != DISABLE) + { + NVIC->VTFIDR[num] = IRQn; + NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1); + } + else{ + NVIC->VTFIDR[num] = IRQn; + NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1)); + } +} + +/********************************************************************* + * @fn NVIC_SystemReset + * + * @brief Initiate a system reset request + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SystemReset(void) +{ + NVIC->CFGR = NVIC_KEY3|(1<<7); +} + +/********************************************************************* + * @fn __AMOADD_W + * + * @brief Atomic Add with 32bit value + * Atomically ADD 32bit value with value in memory using amoadd.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ADDed + * + * @return return memory value + add value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoadd.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOAND_W + * + * @brief Atomic And with 32bit value + * Atomically AND 32bit value with value in memory using amoand.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ANDed + * + * @return return memory value & and value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoand.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMAX_W + * + * @brief Atomic signed MAX with 32bit value + * Atomically signed max compare 32bit value with value in memory using amomax.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return the bigger value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amomax.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMAXU_W + * + * @brief Atomic unsigned MAX with 32bit value + * Atomically unsigned max compare 32bit value with value in memory using amomaxu.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return return the bigger value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value) +{ + uint32_t result; + + __asm volatile ("amomaxu.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMIN_W + * + * @brief Atomic signed MIN with 32bit value + * Atomically signed min compare 32bit value with value in memory using amomin.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return the smaller value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amomin.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMINU_W + * + * @brief Atomic unsigned MIN with 32bit value + * Atomically unsigned min compare 32bit value with value in memory using amominu.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return the smaller value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value) +{ + uint32_t result; + + __asm volatile ("amominu.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOOR_W + * + * @brief Atomic OR with 32bit value + * Atomically OR 32bit value with value in memory using amoor.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ORed + * + * @return return memory value | and value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoor.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOSWAP_W + * + * @brief Atomically swap new 32bit value into memory using amoswap.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * newval - New value to be stored into the address + * + * @return return the original value in memory + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval) +{ + uint32_t result; + + __asm volatile ("amoswap.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(newval) : "memory"); + return result; +} + +/********************************************************************* + * @fn __AMOXOR_W + * + * @brief Atomic XOR with 32bit value + * Atomically XOR 32bit value with value in memory using amoxor.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be XORed + * + * @return return memory value ^ and value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoxor.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/* Core_Exported_Functions */ +extern uint32_t __get_MSTATUS(void); +extern void __set_MSTATUS(uint32_t value); +extern uint32_t __get_MISA(void); +extern void __set_MISA(uint32_t value); +extern uint32_t __get_MTVEC(void); +extern void __set_MTVEC(uint32_t value); +extern uint32_t __get_MSCRATCH(void); +extern void __set_MSCRATCH(uint32_t value); +extern uint32_t __get_MEPC(void); +extern void __set_MEPC(uint32_t value); +extern uint32_t __get_MCAUSE(void); +extern void __set_MCAUSE(uint32_t value); +extern uint32_t __get_MTVAL(void); +extern void __set_MTVAL(uint32_t value); +extern uint32_t __get_MVENDORID(void); +extern uint32_t __get_MARCHID(void); +extern uint32_t __get_MIMPID(void); +extern uint32_t __get_MHARTID(void); +extern uint32_t __get_SP(void); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + diff --git a/Code/DAP_X033/DAP/CherryUSB/class/cdc/usb_cdc.h b/Code/DAP_X033/DAP/CherryUSB/class/cdc/usb_cdc.h new file mode 100644 index 0000000..b8a544f --- /dev/null +++ b/Code/DAP_X033/DAP/CherryUSB/class/cdc/usb_cdc.h @@ -0,0 +1,698 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_CDC_H +#define USB_CDC_H + +/*------------------------------------------------------------------------------ + * Definitions based on usbcdc11.pdf (www.usb.org) + *----------------------------------------------------------------------------*/ +/* Communication device class specification version 1.10 */ +#define CDC_V1_10 0x0110U +// Communication device class specification version 1.2 +#define CDC_V1_2_0 0x0120U + +/* Communication interface class code */ +/* (usbcdc11.pdf, 4.2, Table 15) */ +#define CDC_COMMUNICATION_INTERFACE_CLASS 0x02U + +/* Communication interface class subclass codes */ +/* (usbcdc11.pdf, 4.3, Table 16) */ +#define CDC_SUBCLASS_NONE 0x00 /* Reserved */ +#define CDC_SUBCLASS_DLC 0x01 /* Direct Line Control Model */ +#define CDC_SUBCLASS_ACM 0x02 /* Abstract Control Model */ +#define CDC_SUBCLASS_TCM 0x03 /* Telephone Control Model */ +#define CDC_SUBCLASS_MCM 0x04 /* Multi-Channel Control Model */ +#define CDC_SUBCLASS_CAPI 0x05 /* CAPI Control Model */ +#define CDC_SUBCLASS_ECM 0x06 /* Ethernet Networking Control Model */ +#define CDC_SUBCLASS_ATM 0x07 /* ATM Networking Control Model */ + /* 0x08-0x0d Reserved (future use) */ +#define CDC_SUBCLASS_MBIM 0x0e /* MBIM Control Model */ + /* 0x0f-0x7f Reserved (future use) */ + /* 0x80-0xfe Reserved (vendor specific) */ + +#define CDC_DIRECT_LINE_CONTROL_MODEL 0x01U +#define CDC_ABSTRACT_CONTROL_MODEL 0x02U +#define CDC_TELEPHONE_CONTROL_MODEL 0x03U +#define CDC_MULTI_CHANNEL_CONTROL_MODEL 0x04U +#define CDC_CAPI_CONTROL_MODEL 0x05U +#define CDC_ETHERNET_NETWORKING_CONTROL_MODEL 0x06U +#define CDC_ATM_NETWORKING_CONTROL_MODEL 0x07U +#define CDC_WIRELESS_HANDSET_CONTROL_MODEL 0x08U +#define CDC_DEVICE_MANAGEMENT 0x09U +#define CDC_MOBILE_DIRECT_LINE_MODEL 0x0AU +#define CDC_OBEX 0x0BU +#define CDC_ETHERNET_EMULATION_MODEL 0x0CU +#define CDC_NETWORK_CONTROL_MODEL 0x0DU + +/* Communication interface class control protocol codes */ +/* (usbcdc11.pdf, 4.4, Table 17) */ +#define CDC_COMMON_PROTOCOL_NONE 0x00U +#define CDC_COMMON_PROTOCOL_AT_COMMANDS 0x01U +#define CDC_COMMON_PROTOCOL_AT_COMMANDS_PCCA_101 0x02U +#define CDC_COMMON_PROTOCOL_AT_COMMANDS_PCCA_101_AND_ANNEXO 0x03U +#define CDC_COMMON_PROTOCOL_AT_COMMANDS_GSM_707 0x04U +#define CDC_COMMON_PROTOCOL_AT_COMMANDS_3GPP_27007 0x05U +#define CDC_COMMON_PROTOCOL_AT_COMMANDS_CDMA 0x06U +#define CDC_COMMON_PROTOCOL_ETHERNET_EMULATION_MODEL 0x07U +// NCM Communication Interface Protocol Codes +// (usbncm10.pdf, 4.2, Table 4-2) +#define CDC_NCM_PROTOCOL_NONE 0x00U +#define CDC_NCM_PROTOCOL_OEM 0xFEU + +/* Data interface class code */ +/* (usbcdc11.pdf, 4.5, Table 18) */ +#define CDC_DATA_INTERFACE_CLASS 0x0A + +/* Data Interface Sub-Class Codes ********************************************/ +#define CDC_DATA_SUBCLASS_NONE 0x00 + +/* Data interface class protocol codes */ +/* (usbcdc11.pdf, 4.7, Table 19) */ +#define CDC_DATA_PROTOCOL_ISDN_BRI 0x30 +#define CDC_DATA_PROTOCOL_HDLC 0x31 +#define CDC_DATA_PROTOCOL_TRANSPARENT 0x32 +#define CDC_DATA_PROTOCOL_Q921_MANAGEMENT 0x50 +#define CDC_DATA_PROTOCOL_Q921_DATA_LINK 0x51 +#define CDC_DATA_PROTOCOL_Q921_MULTIPLEXOR 0x52 +#define CDC_DATA_PROTOCOL_V42 0x90 +#define CDC_DATA_PROTOCOL_EURO_ISDN 0x91 +#define CDC_DATA_PROTOCOL_V24_RATE_ADAPTATION 0x92 +#define CDC_DATA_PROTOCOL_CAPI 0x93 +#define CDC_DATA_PROTOCOL_HOST_BASED_DRIVER 0xFD +#define CDC_DATA_PROTOCOL_DESCRIBED_IN_PUFD 0xFE + +/* Type values for bDescriptorType field of functional descriptors */ +/* (usbcdc11.pdf, 5.2.3, Table 24) */ +#define CDC_CS_INTERFACE 0x24 +#define CDC_CS_ENDPOINT 0x25 + +/* Type values for bDescriptorSubtype field of functional descriptors */ +/* (usbcdc11.pdf, 5.2.3, Table 25) */ +#define CDC_FUNC_DESC_HEADER 0x00 +#define CDC_FUNC_DESC_CALL_MANAGEMENT 0x01 +#define CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT 0x02 +#define CDC_FUNC_DESC_DIRECT_LINE_MANAGEMENT 0x03 +#define CDC_FUNC_DESC_TELEPHONE_RINGER 0x04 +#define CDC_FUNC_DESC_REPORTING_CAPABILITIES 0x05 +#define CDC_FUNC_DESC_UNION 0x06 +#define CDC_FUNC_DESC_COUNTRY_SELECTION 0x07 +#define CDC_FUNC_DESC_TELEPHONE_OPERATIONAL_MODES 0x08 +#define CDC_FUNC_DESC_USB_TERMINAL 0x09 +#define CDC_FUNC_DESC_NETWORK_CHANNEL 0x0A +#define CDC_FUNC_DESC_PROTOCOL_UNIT 0x0B +#define CDC_FUNC_DESC_EXTENSION_UNIT 0x0C +#define CDC_FUNC_DESC_MULTI_CHANNEL_MANAGEMENT 0x0D +#define CDC_FUNC_DESC_CAPI_CONTROL_MANAGEMENT 0x0E +#define CDC_FUNC_DESC_ETHERNET_NETWORKING 0x0F +#define CDC_FUNC_DESC_ATM_NETWORKING 0x10 +#define CDC_FUNC_DESC_WIRELESS_HANDSET_CONTROL_MODEL 0x11 +#define CDC_FUNC_DESC_MOBILE_DIRECT_LINE_MODEL 0x12 +#define CDC_FUNC_DESC_MOBILE_DIRECT_LINE_MODEL_DETAIL 0x13 +#define CDC_FUNC_DESC_DEVICE_MANAGEMENT_MODEL 0x14 +#define CDC_FUNC_DESC_OBEX 0x15 +#define CDC_FUNC_DESC_COMMAND_SET 0x16 +#define CDC_FUNC_DESC_COMMAND_SET_DETAIL 0x17 +#define CDC_FUNC_DESC_TELEPHONE_CONTROL_MODEL 0x18 +#define CDC_FUNC_DESC_OBEX_SERVICE_IDENTIFIER 0x19 +#define CDC_FUNC_DESC_NCM 0x1A + +/* CDC class-specific request codes */ +/* (usbcdc11.pdf, 6.2, Table 46) */ +/* see Table 45 for info about the specific requests. */ +#define CDC_REQUEST_SEND_ENCAPSULATED_COMMAND 0x00 +#define CDC_REQUEST_GET_ENCAPSULATED_RESPONSE 0x01 +#define CDC_REQUEST_SET_COMM_FEATURE 0x02 +#define CDC_REQUEST_GET_COMM_FEATURE 0x03 +#define CDC_REQUEST_CLEAR_COMM_FEATURE 0x04 +#define CDC_REQUEST_SET_AUX_LINE_STATE 0x10 +#define CDC_REQUEST_SET_HOOK_STATE 0x11 +#define CDC_REQUEST_PULSE_SETUP 0x12 +#define CDC_REQUEST_SEND_PULSE 0x13 +#define CDC_REQUEST_SET_PULSE_TIME 0x14 +#define CDC_REQUEST_RING_AUX_JACK 0x15 +#define CDC_REQUEST_SET_LINE_CODING 0x20 +#define CDC_REQUEST_GET_LINE_CODING 0x21 +#define CDC_REQUEST_SET_CONTROL_LINE_STATE 0x22 +#define CDC_REQUEST_SEND_BREAK 0x23 +#define CDC_REQUEST_SET_RINGER_PARMS 0x30 +#define CDC_REQUEST_GET_RINGER_PARMS 0x31 +#define CDC_REQUEST_SET_OPERATION_PARMS 0x32 +#define CDC_REQUEST_GET_OPERATION_PARMS 0x33 +#define CDC_REQUEST_SET_LINE_PARMS 0x34 +#define CDC_REQUEST_GET_LINE_PARMS 0x35 +#define CDC_REQUEST_DIAL_DIGITS 0x36 +#define CDC_REQUEST_SET_UNIT_PARAMETER 0x37 +#define CDC_REQUEST_GET_UNIT_PARAMETER 0x38 +#define CDC_REQUEST_CLEAR_UNIT_PARAMETER 0x39 +#define CDC_REQUEST_GET_PROFILE 0x3A +#define CDC_REQUEST_SET_ETHERNET_MULTICAST_FILTERS 0x40 +#define CDC_REQUEST_SET_ETHERNET_PMP_FILTER 0x41 +#define CDC_REQUEST_GET_ETHERNET_PMP_FILTER 0x42 +#define CDC_REQUEST_SET_ETHERNET_PACKET_FILTER 0x43 +#define CDC_REQUEST_GET_ETHERNET_STATISTIC 0x44 +#define CDC_REQUEST_SET_ATM_DATA_FORMAT 0x50 +#define CDC_REQUEST_GET_ATM_DEVICE_STATISTICS 0x51 +#define CDC_REQUEST_SET_ATM_DEFAULT_VC 0x52 +#define CDC_REQUEST_GET_ATM_VC_STATISTICS 0x53 +#define CDC_REQUEST_GET_NTB_PARAMETERS 0x80 +#define CDC_REQUEST_GET_NET_ADDRESS 0x81 +#define CDC_REQUEST_SET_NET_ADDRESS 0x82 +#define CDC_REQUEST_GET_NTB_FORMAT 0x83 +#define CDC_REQUEST_SET_NTB_FORMAT 0x84 +#define CDC_REQUEST_GET_NTB_INPUT_SIZE 0x85 +#define CDC_REQUEST_SET_NTB_INPUT_SIZE 0x86 +#define CDC_REQUEST_GET_MAX_DATAGRAM_SIZE 0x87 +#define CDC_REQUEST_SET_MAX_DATAGRAM_SIZE 0x88 +#define CDC_REQUEST_GET_CRC_MODE 0x89 +#define CDC_REQUEST_SET_CRC_MODE 0x90 + +/* Communication feature selector codes */ +/* (usbcdc11.pdf, 6.2.2..6.2.4, Table 47) */ +#define CDC_ABSTRACT_STATE 0x01 +#define CDC_COUNTRY_SETTING 0x02 + +/** Control Signal Bitmap Values for SetControlLineState */ +#define SET_CONTROL_LINE_STATE_RTS 0x02 +#define SET_CONTROL_LINE_STATE_DTR 0x01 + +/* Feature Status returned for ABSTRACT_STATE Selector */ +/* (usbcdc11.pdf, 6.2.3, Table 48) */ +#define CDC_IDLE_SETTING (1 << 0) +#define CDC_DATA_MULTPLEXED_STATE (1 << 1) + +/* Control signal bitmap values for the SetControlLineState request */ +/* (usbcdc11.pdf, 6.2.14, Table 51) */ +#define CDC_DTE_PRESENT (1 << 0) +#define CDC_ACTIVATE_CARRIER (1 << 1) + +/* CDC class-specific notification codes */ +/* (usbcdc11.pdf, 6.3, Table 68) */ +/* see Table 67 for Info about class-specific notifications */ +#define CDC_NOTIFICATION_NETWORK_CONNECTION 0x00 +#define CDC_RESPONSE_AVAILABLE 0x01 +#define CDC_AUX_JACK_HOOK_STATE 0x08 +#define CDC_RING_DETECT 0x09 +#define CDC_NOTIFICATION_SERIAL_STATE 0x20 +#define CDC_CALL_STATE_CHANGE 0x28 +#define CDC_LINE_STATE_CHANGE 0x29 +#define CDC_CONNECTION_SPEED_CHANGE 0x2A + +/* UART state bitmap values (Serial state notification). */ +/* (usbcdc11.pdf, 6.3.5, Table 69) */ +#define CDC_SERIAL_STATE_OVERRUN (1 << 6) /* receive data overrun error has occurred */ +#define CDC_SERIAL_STATE_OVERRUN_Pos (6) +#define CDC_SERIAL_STATE_OVERRUN_Msk (1 << CDC_SERIAL_STATE_OVERRUN_Pos) +#define CDC_SERIAL_STATE_PARITY (1 << 5) /* parity error has occurred */ +#define CDC_SERIAL_STATE_PARITY_Pos (5) +#define CDC_SERIAL_STATE_PARITY_Msk (1 << CDC_SERIAL_STATE_PARITY_Pos) +#define CDC_SERIAL_STATE_FRAMING (1 << 4) /* framing error has occurred */ +#define CDC_SERIAL_STATE_FRAMING_Pos (4) +#define CDC_SERIAL_STATE_FRAMING_Msk (1 << CDC_SERIAL_STATE_FRAMING_Pos) +#define CDC_SERIAL_STATE_RING (1 << 3) /* state of ring signal detection */ +#define CDC_SERIAL_STATE_RING_Pos (3) +#define CDC_SERIAL_STATE_RING_Msk (1 << CDC_SERIAL_STATE_RING_Pos) +#define CDC_SERIAL_STATE_BREAK (1 << 2) /* state of break detection */ +#define CDC_SERIAL_STATE_BREAK_Pos (2) +#define CDC_SERIAL_STATE_BREAK_Msk (1 << CDC_SERIAL_STATE_BREAK_Pos) +#define CDC_SERIAL_STATE_TX_CARRIER (1 << 1) /* state of transmission carrier */ +#define CDC_SERIAL_STATE_TX_CARRIER_Pos (1) +#define CDC_SERIAL_STATE_TX_CARRIER_Msk (1 << CDC_SERIAL_STATE_TX_CARRIER_Pos) +#define CDC_SERIAL_STATE_RX_CARRIER (1 << 0) /* state of receiver carrier */ +#define CDC_SERIAL_STATE_RX_CARRIER_Pos (0) +#define CDC_SERIAL_STATE_RX_CARRIER_Msk (1 << CDC_SERIAL_STATE_RX_CARRIER_Pos) + +#define CDC_ECM_XMIT_OK (1 << 0) +#define CDC_ECM_RVC_OK (1 << 1) +#define CDC_ECM_XMIT_ERROR (1 << 2) +#define CDC_ECM_RCV_ERROR (1 << 3) +#define CDC_ECM_RCV_NO_BUFFER (1 << 4) +#define CDC_ECM_DIRECTED_BYTES_XMIT (1 << 5) +#define CDC_ECM_DIRECTED_FRAMES_XMIT (1 << 6) +#define CDC_ECM_MULTICAST_BYTES_XMIT (1 << 7) +#define CDC_ECM_MULTICAST_FRAMES_XMIT (1 << 8) +#define CDC_ECM_BROADCAST_BYTES_XMIT (1 << 9) +#define CDC_ECM_BROADCAST_FRAMES_XMIT (1 << 10) +#define CDC_ECM_DIRECTED_BYTES_RCV (1 << 11) +#define CDC_ECM_DIRECTED_FRAMES_RCV (1 << 12) +#define CDC_ECM_MULTICAST_BYTES_RCV (1 << 13) +#define CDC_ECM_MULTICAST_FRAMES_RCV (1 << 14) +#define CDC_ECM_BROADCAST_BYTES_RCV (1 << 15) +#define CDC_ECM_BROADCAST_FRAMES_RCV (1 << 16) +#define CDC_ECM_RCV_CRC_ERROR (1 << 17) +#define CDC_ECM_TRANSMIT_QUEUE_LENGTH (1 << 18) +#define CDC_ECM_RCV_ERROR_ALIGNMENT (1 << 19) +#define CDC_ECM_XMIT_ONE_COLLISION (1 << 20) +#define CDC_ECM_XMIT_MORE_COLLISIONS (1 << 21) +#define CDC_ECM_XMIT_DEFERRED (1 << 22) +#define CDC_ECM_XMIT_MAX_COLLISIONS (1 << 23) +#define CDC_ECM_RCV_OVERRUN (1 << 24) +#define CDC_ECM_XMIT_UNDERRUN (1 << 25) +#define CDC_ECM_XMIT_HEARTBEAT_FAILURE (1 << 26) +#define CDC_ECM_XMIT_TIMES_CRS_LOST (1 << 27) +#define CDC_ECM_XMIT_LATE_COLLISIONS (1 << 28) + +#define CDC_ECM_MAC_STR_DESC (uint8_t *)"010202030000" +#define CDC_ECM_MAC_ADDR0 0x00U /* 01 */ +#define CDC_ECM_MAC_ADDR1 0x02U /* 02 */ +#define CDC_ECM_MAC_ADDR2 0x02U /* 03 */ +#define CDC_ECM_MAC_ADDR3 0x03U /* 00 */ +#define CDC_ECM_MAC_ADDR4 0x00U /* 00 */ +#define CDC_ECM_MAC_ADDR5 0x00U /* 00 */ + +#define CDC_ECM_NET_DISCONNECTED 0x00U +#define CDC_ECM_NET_CONNECTED 0x01U + +#define CDC_ECM_ETH_STATS_RESERVED 0xE0U +#define CDC_ECM_BMREQUEST_TYPE_ECM 0xA1U + +#define CDC_ECM_CONNECT_SPEED_UPSTREAM 0x004C4B40U /* 5Mbps */ +#define CDC_ECM_CONNECT_SPEED_DOWNSTREAM 0x004C4B40U /* 5Mbps */ + +#define CDC_ECM_NOTIFY_CODE_NETWORK_CONNECTION 0x00 +#define CDC_ECM_NOTIFY_CODE_RESPONSE_AVAILABLE 0x01 +#define CDC_ECM_NOTIFY_CODE_CONNECTION_SPEED_CHANGE 0x2A + +#define CDC_NCM_NTH16_SIGNATURE 0x484D434E +#define CDC_NCM_NDP16_SIGNATURE_NCM0 0x304D434E +#define CDC_NCM_NDP16_SIGNATURE_NCM1 0x314D434E + +/*------------------------------------------------------------------------------ + * Structures based on usbcdc11.pdf (www.usb.org) + *----------------------------------------------------------------------------*/ + +/* Header functional descriptor */ +/* (usbcdc11.pdf, 5.2.3.1) */ +/* This header must precede any list of class-specific descriptors. */ +struct cdc_header_descriptor { + uint8_t bFunctionLength; /* size of this descriptor in bytes */ + uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */ + uint8_t bDescriptorSubtype; /* Header functional descriptor subtype */ + uint16_t bcdCDC; /* USB CDC specification release version */ +} __PACKED; + +/* Call management functional descriptor */ +/* (usbcdc11.pdf, 5.2.3.2) */ +/* Describes the processing of calls for the communication class interface. */ +struct cdc_call_management_descriptor { + uint8_t bFunctionLength; /* size of this descriptor in bytes */ + uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */ + uint8_t bDescriptorSubtype; /* call management functional descriptor subtype */ + uint8_t bmCapabilities; /* capabilities that this configuration supports */ + uint8_t bDataInterface; /* interface number of the data class interface used for call management (optional) */ +} __PACKED; + +/* Abstract control management functional descriptor */ +/* (usbcdc11.pdf, 5.2.3.3) */ +/* Describes the command supported by the communication interface class with the Abstract Control Model subclass code. */ +struct cdc_abstract_control_management_descriptor { + uint8_t bFunctionLength; /* size of this descriptor in bytes */ + uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */ + uint8_t bDescriptorSubtype; /* abstract control management functional descriptor subtype */ + uint8_t bmCapabilities; /* capabilities supported by this configuration */ +} __PACKED; + +/* Union functional descriptors */ +/* (usbcdc11.pdf, 5.2.3.8) */ +/* Describes the relationship between a group of interfaces that can be considered to form a functional unit. */ +struct cdc_union_descriptor { + uint8_t bFunctionLength; /* size of this descriptor in bytes */ + uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */ + uint8_t bDescriptorSubtype; /* union functional descriptor subtype */ + uint8_t bMasterInterface; /* interface number designated as master */ +} __PACKED; + +/* Union functional descriptors with one slave interface */ +/* (usbcdc11.pdf, 5.2.3.8) */ +struct cdc_union_1slave_descriptor { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bControlInterface; + uint8_t bSubordinateInterface0; +} __PACKED; + +/* Line coding structure for GET_LINE_CODING / SET_LINE_CODING class requests*/ +/* Format of the data returned when a GetLineCoding request is received */ +/* (usbcdc11.pdf, 6.2.13) */ +struct cdc_line_coding { + uint32_t dwDTERate; /* Data terminal rate in bits per second */ + uint8_t bCharFormat; /* Number of stop bits */ + uint8_t bParityType; /* Parity bit type */ + uint8_t bDataBits; /* Number of data bits */ +} __PACKED; + +/** Data structure for the notification about SerialState */ +struct cdc_acm_notification { + uint8_t bmRequestType; + uint8_t bNotificationType; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; + uint16_t data; +} __PACKED; + +/** Ethernet Networking Functional Descriptor */ +struct cdc_eth_descriptor { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t iMACAddress; + uint32_t bmEthernetStatistics; + uint16_t wMaxSegmentSize; + uint16_t wNumberMCFilters; + uint8_t bNumberPowerFilters; +} __PACKED; + +struct cdc_eth_notification { + uint8_t bmRequestType; + uint8_t bNotificationType; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; + uint8_t data[8]; +} __PACKED; + +struct cdc_ncm_ntb_parameters { + uint16_t wLength; + uint16_t bmNtbFormatsSupported; + uint32_t dwNtbInMaxSize; + uint16_t wNdbInDivisor; + uint16_t wNdbInPayloadRemainder; + uint16_t wNdbInAlignment; + uint16_t wReserved; + uint32_t dwNtbOutMaxSize; + uint16_t wNdbOutDivisor; + uint16_t wNdbOutPayloadRemainder; + uint16_t wNdbOutAlignment; + uint16_t wNtbOutMaxDatagrams; +}; + +struct cdc_ncm_nth16 { + uint32_t dwSignature; + uint16_t wHeaderLength; + uint16_t wSequence; + uint16_t wBlockLength; + uint16_t wNdpIndex; +}; + +struct cdc_ncm_ndp16_datagram { + uint16_t wDatagramIndex; + uint16_t wDatagramLength; +}; + +struct cdc_ncm_ndp16 { + uint32_t dwSignature; + uint16_t wLength; + uint16_t wNextNdpIndex; + struct cdc_ncm_ndp16_datagram datagram[]; +}; + +/*Length of template descriptor: 66 bytes*/ +#define CDC_ACM_DESCRIPTOR_LEN (8 + 9 + 5 + 5 + 4 + 5 + 7 + 9 + 7 + 7) +// clang-format off +#define CDC_ACM_DESCRIPTOR_INIT(bFirstInterface, int_ep, out_ep, in_ep, wMaxPacketSize, str_idx) \ + /* Interface Associate */ \ + 0x08, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, /* bDescriptorType */ \ + bFirstInterface, /* bFirstInterface */ \ + 0x02, /* bInterfaceCount */ \ + USB_DEVICE_CLASS_CDC, /* bFunctionClass */ \ + CDC_ABSTRACT_CONTROL_MODEL, /* bFunctionSubClass */ \ + CDC_COMMON_PROTOCOL_AT_COMMANDS, /* bFunctionProtocol */ \ + 0x00, /* iFunction */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bFirstInterface, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x01, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_CDC, /* bInterfaceClass */ \ + CDC_ABSTRACT_CONTROL_MODEL, /* bInterfaceSubClass */ \ + CDC_COMMON_PROTOCOL_AT_COMMANDS, /* bInterfaceProtocol */ \ + str_idx, /* iInterface */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_HEADER, /* bDescriptorSubtype */ \ + WBVAL(CDC_V1_10), /* bcdCDC */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_CALL_MANAGEMENT, /* bDescriptorSubtype */ \ + 0x00, /* bmCapabilities */ \ + (uint8_t)(bFirstInterface + 1), /* bDataInterface */ \ + 0x04, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT, /* bDescriptorSubtype */ \ + 0x02, /* bmCapabilities */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_UNION, /* bDescriptorSubtype */ \ + bFirstInterface, /* bMasterInterface */ \ + (uint8_t)(bFirstInterface + 1), /* bSlaveInterface0 */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + int_ep, /* bEndpointAddress */ \ + 0x03, /* bmAttributes */ \ + 0x08, 0x00, /* wMaxPacketSize */ \ + 0x0a, /* bInterval */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + (uint8_t)(bFirstInterface + 1), /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x02, /* bNumEndpoints */ \ + CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass */ \ + 0x00, /* bInterfaceSubClass */ \ + 0x00, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + out_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00, /* bInterval */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + in_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00 /* bInterval */ +// clang-format on + +/*Length of template descriptor: 66 bytes*/ +#define CDC_RNDIS_DESCRIPTOR_LEN (8 + 9 + 5 + 5 + 4 + 5 + 7 + 9 + 7 + 7) +// clang-format off +#define CDC_RNDIS_DESCRIPTOR_INIT(bFirstInterface, int_ep, out_ep, in_ep, wMaxPacketSize, str_idx) \ + /* Interface Associate */ \ + 0x08, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, /* bDescriptorType */ \ + bFirstInterface, /* bFirstInterface */ \ + 0x02, /* bInterfaceCount */ \ + USB_DEVICE_CLASS_WIRELESS, /* bFunctionClass */ \ + CDC_DIRECT_LINE_CONTROL_MODEL, /* bFunctionSubClass */ \ + CDC_COMMON_PROTOCOL_AT_COMMANDS_PCCA_101_AND_ANNEXO, /* bFunctionProtocol */ \ + 0x00, /* iFunction */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bFirstInterface, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x01, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_WIRELESS, /* bInterfaceClass */ \ + CDC_DIRECT_LINE_CONTROL_MODEL, /* bInterfaceSubClass */ \ + CDC_COMMON_PROTOCOL_AT_COMMANDS_PCCA_101_AND_ANNEXO, /* bInterfaceProtocol */ \ + str_idx, /* iInterface */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_HEADER, /* bDescriptorSubtype */ \ + WBVAL(CDC_V1_10), /* bcdCDC */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_CALL_MANAGEMENT, /* bDescriptorSubtype */ \ + 0x00, /* bmCapabilities */ \ + (uint8_t)(bFirstInterface + 1), /* bDataInterface */ \ + 0x04, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT, /* bDescriptorSubtype */ \ + 0x00, /* bmCapabilities */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_UNION, /* bDescriptorSubtype */ \ + bFirstInterface, /* bMasterInterface */ \ + (uint8_t)(bFirstInterface + 1), /* bSlaveInterface0 */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + int_ep, /* bEndpointAddress */ \ + 0x03, /* bmAttributes */ \ + 0x08, 0x00, /* wMaxPacketSize */ \ + 0x10, /* bInterval */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + (uint8_t)(bFirstInterface + 1), /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x02, /* bNumEndpoints */ \ + CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass */ \ + 0x00, /* bInterfaceSubClass */ \ + 0x00, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + out_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00, /* bInterval */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + in_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00 /* bInterval */ +// clang-format on + +#define DBVAL_BE(x) ((x >> 24) & 0xFF), ((x >> 16) & 0xFF), ((x >> 8) & 0xFF), (x & 0xFF) + +/*Length of template descriptor: 71 bytes*/ +#define CDC_ECM_DESCRIPTOR_LEN (8 + 9 + 5 + 5 + 13 + 7 + 9 + 7 + 7) +// clang-format off +#define CDC_ECM_DESCRIPTOR_INIT(bFirstInterface, int_ep, out_ep, in_ep, wMaxPacketSize, \ +eth_statistics, wMaxSegmentSize, wNumberMCFilters, bNumberPowerFilters, str_idx) \ + /* Interface Associate */ \ + 0x08, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, /* bDescriptorType */ \ + bFirstInterface, /* bFirstInterface */ \ + 0x02, /* bInterfaceCount */ \ + USB_DEVICE_CLASS_CDC, /* bFunctionClass */ \ + CDC_ETHERNET_NETWORKING_CONTROL_MODEL, /* bFunctionSubClass */ \ + CDC_COMMON_PROTOCOL_NONE, /* bFunctionProtocol */ \ + 0x00, /* iFunction */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bFirstInterface, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x01, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_CDC, /* bInterfaceClass */ \ + CDC_ETHERNET_NETWORKING_CONTROL_MODEL, /* bInterfaceSubClass */ \ + CDC_COMMON_PROTOCOL_NONE, /* bInterfaceProtocol */ \ + str_idx, /* iInterface */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_HEADER, /* bDescriptorSubtype */ \ + WBVAL(CDC_V1_10), /* bcdCDC */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_UNION, /* bDescriptorSubtype */ \ + bFirstInterface, /* bMasterInterface */ \ + (uint8_t)(bFirstInterface + 1), /* bSlaveInterface0 */ \ + /* CDC_ECM Functional Descriptor */ \ + 0x0D, /* bFunctionLength */\ + CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */\ + CDC_FUNC_DESC_ETHERNET_NETWORKING, /* Ethernet Networking functional descriptor subtype */\ + str_idx, /* Device's MAC string index */\ + DBVAL_BE(eth_statistics), /* Ethernet statistics (bitmap) */\ + WBVAL(wMaxPacketSize),/* wMaxSegmentSize: Ethernet Maximum Segment size, typically 1514 bytes */\ + WBVAL(wNumberMCFilters), /* wNumberMCFilters: the number of multicast filters */\ + bNumberPowerFilters, /* bNumberPowerFilters: the number of wakeup power filters */\ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + int_ep, /* bEndpointAddress */ \ + 0x03, /* bmAttributes */ \ + 0x10, 0x00, /* wMaxPacketSize */ \ + 0x10, /* bInterval */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + (uint8_t)(bFirstInterface + 1), /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x02, /* bNumEndpoints */ \ + CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass */ \ + 0x00, /* bInterfaceSubClass */ \ + 0x00, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + out_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00, /* bInterval */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + in_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00 /* bInterval */ +// clang-format on + +/*Length of template descriptor: 77 bytes*/ +#define CDC_NCM_DESCRIPTOR_LEN (8 + 9 + 5 + 5 + 13 + 6 + 7 + 9 + 7 + 7) +// clang-format off +#define CDC_NCM_DESCRIPTOR_INIT(bFirstInterface, int_ep, out_ep, in_ep, wMaxPacketSize, \ +eth_statistics, wMaxSegmentSize, wNumberMCFilters, bNumberPowerFilters, str_idx) \ + /* Interface Associate */ \ + 0x08, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, /* bDescriptorType */ \ + bFirstInterface, /* bFirstInterface */ \ + 0x02, /* bInterfaceCount */ \ + USB_DEVICE_CLASS_CDC, /* bFunctionClass */ \ + CDC_NETWORK_CONTROL_MODEL, /* bFunctionSubClass */ \ + CDC_COMMON_PROTOCOL_NONE, /* bFunctionProtocol */ \ + 0x00, /* iFunction */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bFirstInterface, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x01, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_CDC, /* bInterfaceClass */ \ + CDC_NETWORK_CONTROL_MODEL, /* bInterfaceSubClass */ \ + CDC_COMMON_PROTOCOL_NONE, /* bInterfaceProtocol */ \ + str_idx, /* iInterface */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_HEADER, /* bDescriptorSubtype */ \ + WBVAL(CDC_V1_10), /* bcdCDC */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_UNION, /* bDescriptorSubtype */ \ + bFirstInterface, /* bMasterInterface */ \ + (uint8_t)(bFirstInterface + 1), /* bSlaveInterface0 */ \ + /* CDC ETH Functional Descriptor */ \ + 0x0D, /* bFunctionLength */\ + CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */\ + CDC_FUNC_DESC_ETHERNET_NETWORKING, /* Ethernet Networking functional descriptor subtype */\ + str_idx, /* Device's MAC string index */\ + DBVAL_BE(eth_statistics), /* Ethernet statistics (bitmap) */\ + WBVAL(wMaxPacketSize),/* wMaxSegmentSize: Ethernet Maximum Segment size, typically 1514 bytes */\ + WBVAL(wNumberMCFilters), /* wNumberMCFilters: the number of multicast filters */\ + bNumberPowerFilters, /* bNumberPowerFilters: the number of wakeup power filters */\ + 0x06, \ + CDC_CS_INTERFACE, \ + CDC_FUNC_DESC_NCM, \ + 0x00, 0x01, \ + 0x23, \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + int_ep, /* bEndpointAddress */ \ + 0x03, /* bmAttributes */ \ + 0x10, 0x00, /* wMaxPacketSize */ \ + 0x10, /* bInterval */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + (uint8_t)(bFirstInterface + 1), /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x02, /* bNumEndpoints */ \ + CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass */ \ + 0x00, /* bInterfaceSubClass */ \ + 0x00, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + out_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00, /* bInterval */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + in_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00 /* bInterval */ +// clang-format on + +#endif /* USB_CDC_H */ diff --git a/Code/DAP_X033/DAP/CherryUSB/class/cdc/usbd_cdc.c b/Code/DAP_X033/DAP/CherryUSB/class/cdc/usbd_cdc.c new file mode 100644 index 0000000..50d13d7 --- /dev/null +++ b/Code/DAP_X033/DAP/CherryUSB/class/cdc/usbd_cdc.c @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_cdc.h" + +const char *stop_name[] = { "1", "1.5", "2" }; +const char *parity_name[] = { "N", "O", "E", "M", "S" }; + +static int cdc_acm_class_interface_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + USB_LOG_DBG("CDC Class request: " + "bRequest 0x%02x\r\n", + setup->bRequest); + + struct cdc_line_coding line_coding; + bool dtr, rts; + uint8_t intf_num = LO_BYTE(setup->wIndex); + + switch (setup->bRequest) { + case CDC_REQUEST_SET_LINE_CODING: + + /*******************************************************************************/ + /* Line Coding Structure */ + /*-----------------------------------------------------------------------------*/ + /* Offset | Field | Size | Value | Description */ + /* 0 | dwDTERate | 4 | Number |Data terminal rate, in bits per second*/ + /* 4 | bCharFormat | 1 | Number | Stop bits */ + /* 0 - 1 Stop bit */ + /* 1 - 1.5 Stop bits */ + /* 2 - 2 Stop bits */ + /* 5 | bParityType | 1 | Number | Parity */ + /* 0 - None */ + /* 1 - Odd */ + /* 2 - Even */ + /* 3 - Mark */ + /* 4 - Space */ + /* 6 | bDataBits | 1 | Number Data bits (5, 6, 7, 8 or 16). */ + /*******************************************************************************/ + memcpy(&line_coding, *data, setup->wLength); + USB_LOG_DBG("Set intf:%d linecoding <%d %d %s %s>\r\n", + intf_num, + line_coding.dwDTERate, + line_coding.bDataBits, + parity_name[line_coding.bParityType], + stop_name[line_coding.bCharFormat]); + + usbd_cdc_acm_set_line_coding(busid, intf_num, &line_coding); + break; + + case CDC_REQUEST_SET_CONTROL_LINE_STATE: + dtr = (setup->wValue & 0x0001); + rts = (setup->wValue & 0x0002); + USB_LOG_DBG("Set intf:%d DTR 0x%x,RTS 0x%x\r\n", + intf_num, + dtr, + rts); + usbd_cdc_acm_set_dtr(busid, intf_num, dtr); + usbd_cdc_acm_set_rts(busid, intf_num, rts); + break; + + case CDC_REQUEST_GET_LINE_CODING: + usbd_cdc_acm_get_line_coding(busid, intf_num, &line_coding); + memcpy(*data, &line_coding, 7); + *len = 7; + USB_LOG_DBG("Get intf:%d linecoding %d %d %d %d\r\n", + intf_num, + line_coding.dwDTERate, + line_coding.bCharFormat, + line_coding.bParityType, + line_coding.bDataBits); + break; + case CDC_REQUEST_SEND_BREAK: + usbd_cdc_acm_send_break(busid, intf_num); + break; + default: + USB_LOG_WRN("Unhandled CDC Class bRequest 0x%02x\r\n", setup->bRequest); + return -1; + } + + return 0; +} + +struct usbd_interface *usbd_cdc_acm_init_intf(uint8_t busid, struct usbd_interface *intf) +{ + intf->class_interface_handler = cdc_acm_class_interface_request_handler; + intf->class_endpoint_handler = NULL; + intf->vendor_handler = NULL; + intf->notify_handler = NULL; + + return intf; +} + +__WEAK void usbd_cdc_acm_set_line_coding(uint8_t busid, uint8_t intf, struct cdc_line_coding *line_coding) +{ +} + +__WEAK void usbd_cdc_acm_get_line_coding(uint8_t busid, uint8_t intf, struct cdc_line_coding *line_coding) +{ + line_coding->dwDTERate = 2000000; + line_coding->bDataBits = 8; + line_coding->bParityType = 0; + line_coding->bCharFormat = 0; +} + +__WEAK void usbd_cdc_acm_set_dtr(uint8_t busid, uint8_t intf, bool dtr) +{ +} + +__WEAK void usbd_cdc_acm_set_rts(uint8_t busid, uint8_t intf, bool rts) +{ +} + +__WEAK void usbd_cdc_acm_send_break(uint8_t busid, uint8_t intf) +{ +} diff --git a/Code/DAP_X033/DAP/CherryUSB/class/cdc/usbd_cdc.h b/Code/DAP_X033/DAP/CherryUSB/class/cdc/usbd_cdc.h new file mode 100644 index 0000000..ebf3d02 --- /dev/null +++ b/Code/DAP_X033/DAP/CherryUSB/class/cdc/usbd_cdc.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_CDC_H +#define USBD_CDC_H + +#include "usb_cdc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Init cdc acm interface driver */ +struct usbd_interface *usbd_cdc_acm_init_intf(uint8_t busid, struct usbd_interface *intf); + +/* Setup request command callback api */ +void usbd_cdc_acm_set_line_coding(uint8_t busid, uint8_t intf, struct cdc_line_coding *line_coding); +void usbd_cdc_acm_get_line_coding(uint8_t busid, uint8_t intf, struct cdc_line_coding *line_coding); +void usbd_cdc_acm_set_dtr(uint8_t busid, uint8_t intf, bool dtr); +void usbd_cdc_acm_set_rts(uint8_t busid, uint8_t intf, bool rts); +void usbd_cdc_acm_send_break(uint8_t busid, uint8_t intf); + +#ifdef __cplusplus +} +#endif + +#endif /* USBD_CDC_H */ diff --git a/Code/DAP_X033/DAP/CherryUSB/class/hid/usb_hid.h b/Code/DAP_X033/DAP/CherryUSB/class/hid/usb_hid.h new file mode 100644 index 0000000..5a88a34 --- /dev/null +++ b/Code/DAP_X033/DAP/CherryUSB/class/hid/usb_hid.h @@ -0,0 +1,585 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_HID_H +#define USB_HID_H + +/* Subclass codes (HID 4.2) */ +#define HID_SUBCLASS_NONE 0 /* No subclass */ +#define HID_SUBCLASS_BOOTIF 1 /* Boot Interface Subclass */ + +/* HID Protocol Codes (HID 4.3) */ +#define HID_PROTOCOL_NONE 0x00 +#define HID_PROTOCOL_BOOT 0x00 +#define HID_PROTOCOL_KEYBOARD 0x01 +#define HID_PROTOCOL_REPORT 0x01 +#define HID_PROTOCOL_MOUSE 0x02 + +/* HID Class Descriptor Types (HID 7.1) */ +#define HID_DESCRIPTOR_TYPE_HID 0x21 +#define HID_DESCRIPTOR_TYPE_HID_REPORT 0x22 +#define HID_DESCRIPTOR_TYPE_HID_PHYSICAL 0x23 + +/* HID Class Specific Requests (HID 7.2) */ +#define HID_REQUEST_GET_REPORT 0x01 +#define HID_REQUEST_GET_IDLE 0x02 +#define HID_REQUEST_GET_PROTOCOL 0x03 +#define HID_REQUEST_SET_REPORT 0x09 +#define HID_REQUEST_SET_IDLE 0x0A +#define HID_REQUEST_SET_PROTOCOL 0x0B + +/* Report Type (MS byte of wValue for GET_REPORT) (HID 7.2.1) */ +#define HID_REPORT_INPUT 0x01 +#define HID_REPORT_OUTPUT 0x02 +#define HID_REPORT_FEATURE 0x03 + +/* HID Descriptor ***********************************************************/ + +#define HID_COUNTRY_NONE 0x00 /* Not Supported */ +#define HID_COUNTRY_ARABIC 0x01 /* Arabic */ +#define HID_COUNTRY_BELGIAN 0x02 /* Belgian */ +#define HID_COUNTRY_CANADA 0x03 /* Canadian-Bilingual */ +#define HID_COUNTRY_CANADRFR 0x04 /* Canadian-French */ +#define HID_COUNTRY_CZECH 0x05 /* Czech Republic */ +#define HID_COUNTRY_DANISH 0x06 /* Danish */ +#define HID_COUNTRY_FINNISH 0x07 /* Finnish */ +#define HID_COUNTRY_FRENCH 0x08 /* French */ +#define HID_COUNTRY_GERMAN 0x09 /* German */ +#define HID_COUNTRY_GREEK 0x10 /* Greek */ +#define HID_COUNTRY_HEBREW 0x11 /* Hebrew */ +#define HID_COUNTRY_HUNGARY 0x12 /* Hungary */ +#define HID_COUNTRY_ISO 0x13 /* International (ISO) */ +#define HID_COUNTRY_ITALIAN 0x14 /* Italian */ +#define HID_COUNTRY_JAPAN 0x15 /* Japan (Katakana) */ +#define HID_COUNTRY_KOREAN 0x16 /* Korean */ +#define HID_COUNTRY_LATINAM 0x17 /* Latin American */ +#define HID_COUNTRY_DUTCH 0x18 /* Netherlands/Dutch */ +#define HID_COUNTRY_NORWEGIAN 0x19 /* Norwegian */ +#define HID_COUNTRY_PERSIAN 0x20 /* Persian (Farsi) */ +#define HID_COUNTRY_POLAND 0x21 /* Poland */ +#define HID_COUNTRY_PORTUGUESE 0x22 /* Portuguese */ +#define HID_COUNTRY_RUSSIA 0x23 /* Russia */ +#define HID_COUNTRY_SLOVAKIA 0x24 /* Slovakia */ +#define HID_COUNTRY_SPANISH 0x25 /* Spanish */ +#define HID_COUNTRY_SWEDISH 0x26 /* Swedish */ +#define HID_COUNTRY_SWISSFR 0x27 /* Swiss/French */ +#define HID_COUNTRY_SWISSGR 0x28 /* Swiss/German */ +#define HID_COUNTRY_SWITZERLAND 0x29 /* Switzerland */ +#define HID_COUNTRY_TAIWAN 0x30 /* Taiwan */ +#define HID_COUNTRY_TURKISHQ 0x31 /* Turkish-Q */ +#define HID_COUNTRY_UK 0x32 /* UK */ +#define HID_COUNTRY_US 0x33 /* US */ +#define HID_COUNTRY_YUGOSLAVIA 0x34 /* Yugoslavia */ +#define HID_COUNTRY_TURKISHF 0x35 /* Turkish-F */ + +/* HID report items */ +#define HID_REPORT_ITEM_SIZE_MASK 0x03 +#define HID_REPORT_ITEM_SIZE_0 0x00 /* No data follows */ +#define HID_REPORT_ITEM_SIZE_1 0x01 /* 1 byte of data follows */ +#define HID_REPORT_ITEM_SIZE_2 0x02 /* 2 bytes of data follow */ +#define HID_REPORT_ITEM_SIZE_4 0x03 /* 4 bytes of data follow */ +#define HID_REPORT_ITEM_TYPE_MASK 0x0c +#define HID_REPORT_ITEM_TYPE_MAIN 0x00 +#define HID_REPORT_ITEM_TYPE_GLOBAL 0x04 +#define HID_REPORT_ITEM_TYPE_LOCAL 0x08 +#define HID_REPORT_ITEM_TAG_MASK 0xf0 + +/* Main Items (HID 6.2.2.4) */ +#define HID_MAIN_ITEM_CONSTANT (1 << 0) /* Constant(1) vs Data(0) */ +#define HID_MAIN_ITEM_VARIABLE (1 << 1) /* Variable(1) vs Array(0) */ +#define HID_MAIN_ITEM_RELATIVE (1 << 2) /* Relative(1) vs Absolute(0) */ +#define HID_MAIN_ITEM_WRAP (1 << 3) /* Wrap(1) vs No Wrap(0) */ +#define HID_MAIN_ITEM_NONLINEAR (1 << 4) /* Non Linear(1) vs Linear(0) */ +#define HID_MAIN_ITEM_NOPREFERRED (1 << 5) /* No Preferred (1) vs Preferred State(0) */ +#define HID_MAIN_ITEM_NULLSTATE (1 << 6) /* Null state(1) vs No Null position(0) */ +#define HID_MAIN_ITEM_VOLATILE (1 << 7) /* Volatile(1) vs Non volatile(0) */ +#define HID_MAIN_ITEM_BUFFEREDBYTES (1 << 8) /* Buffered Bytes(1) vs Bit Field(0) */ + +#define HID_MAIN_ITEM_SIZE(pfx) ((pfx)&HID_REPORT_ITEM_SIZE_MASK) +#define HID_MAIN_ITEM_INPUT_PREFIX 0x80 +#define HID_MAIN_ITEM_INPUT_CONSTANT HID_MAIN_ITEM_CONSTANT +#define HID_MAIN_ITEM_INPUT_VARIABLE HID_MAIN_ITEM_VARIABLE +#define HID_MAIN_ITEM_INPUT_RELATIVE HID_MAIN_ITEM_RELATIVE +#define HID_MAIN_ITEM_INPUT_WRAP HID_MAIN_ITEM_WRAP +#define HID_MAIN_ITEM_INPUT_NONLINEAR HID_MAIN_ITEM_NONLINEAR +#define HID_MAIN_ITEM_INPUT_NOPREFERRED HID_MAIN_ITEM_NOPREFERRED +#define HID_MAIN_ITEM_INPUT_NULLSTATE HID_MAIN_ITEM_NULLSTATE +#define HID_MAIN_ITEM_INPUT_BUFFEREDBYTES HID_MAIN_ITEM_BUFFEREDBYTES + +#define HID_MAIN_ITEM_OUTPUT_PREFIX 0x90 +#define HID_MAIN_ITEM_OUTPUT_CONSTANT HID_MAIN_ITEM_CONSTANT +#define HID_MAIN_ITEM_OUTPUT_VARIABLE HID_MAIN_ITEM_VARIABLE +#define HID_MAIN_ITEM_OUTPUT_RELATIVE HID_MAIN_ITEM_RELATIVE +#define HID_MAIN_ITEM_OUTPUT_WRAP HID_MAIN_ITEM_WRAP +#define HID_MAIN_ITEM_OUTPUT_NONLINEAR HID_MAIN_ITEM_NONLINEAR +#define HID_MAIN_ITEM_OUTPUT_NOPREFERRED HID_MAIN_ITEM_NOPREFERRED +#define HID_MAIN_ITEM_OUTPUT_NULLSTATE HID_MAIN_ITEM_NULLSTATE +#define HID_MAIN_ITEM_OUTPUT_VOLATILE HID_MAIN_ITEM_VOLATILE +#define HID_MAIN_ITEM_OUTPUT_BUFFEREDBYTES HID_MAIN_ITEM_BUFFEREDBYTES + +#define HID_MAIN_ITEM_FEATURE_PREFIX 0xb0 +#define HID_MAIN_ITEM_FEATURE_CONSTANT HID_MAIN_ITEM_CONSTANT +#define HID_MAIN_ITEM_FEATURE_VARIABLE HID_MAIN_ITEM_VARIABLE +#define HID_MAIN_ITEM_FEATURE_RELATIVE HID_MAIN_ITEM_RELATIVE +#define HID_MAIN_ITEM_FEATURE_WRAP HID_MAIN_ITEM_WRAP +#define HID_MAIN_ITEM_FEATURE_NONLINEAR HID_MAIN_ITEM_NONLINEAR +#define HID_MAIN_ITEM_FEATURE_NOPREFERRED HID_MAIN_ITEM_NOPREFERRED +#define HID_MAIN_ITEM_FEATURE_NULLSTATE HID_MAIN_ITEM_NULLSTATE +#define HID_MAIN_ITEM_FEATURE_VOLATILE HID_MAIN_ITEM_VOLATILE +#define HID_MAIN_ITEM_FEATURE_BUFFEREDBYTES HID_MAIN_ITEM_BUFFEREDBYTES + +#define HID_MAIN_ITEM_COLLECTION_PREFIX 0xa0 +#define HID_MAIN_ITEM_COLLECTION_PHYSICAL 0x00 /* Physical (group of axes) */ +#define HID_MAIN_ITEM_COLLECTION_APPL 0x01 /* Application (mouse, keyboard) */ +#define HID_MAIN_ITEM_COLLECTION_LOGICAL 0x02 /* Logical (interrelated data) */ +#define HID_MAIN_ITEM_COLLECTION_REPORT 0x03 /* Report */ +#define HID_MAIN_ITEM_COLLECTION_ARRAY 0x04 /* Named Array */ +#define HID_MAIN_ITEM_COLLECTION_SWITCH 0x05 /* Usage Switch */ +#define HID_MAIN_ITEM_COLLECTION_MODIFIER 0x06 /* Usage Modifier */ +#define HID_MAIN_ITEM_ENDCOLLECTION_PREFIX 0xc0 + +/* Global Items (HID 6.2.2.7) */ +#define HID_GLOBAL_ITEM_SIZE(pfx) ((pfx)&HID_REPORT_ITEM_SIZE_MASK) +#define HID_GLOBAL_ITEM_USAGEPAGE_PREFIX 0x04 /* Usage Page */ +#define HID_GLOBAL_ITEM_LOGICALMIN_PREFIX 0x14 /* Logical Minimum */ +#define HID_GLOBAL_ITEM_LOGICALMAX_PREFIX 0x24 /* Logical Maximum */ +#define HID_GLOBAL_ITEM_PHYSICALMIN_PREFIX 0x34 /* Physical Minimum */ +#define HID_GLOBAL_ITEM_PHYSMICALAX_PREFIX 0x44 /* Physical Maximum */ +#define HID_GLOBAL_ITEM_UNITEXP_PREFIX 0x54 /* Unit Exponent */ +#define HID_GLOBAL_ITEM_UNIT_PREFIX 0x64 /* Unit */ +#define HID_GLOBAL_ITEM_REPORTSIZE_PREFIX 0x74 /* Report Size */ +#define HID_GLOBAL_ITEM_REPORTID_PREFIX 0x84 /* Report ID */ +#define HID_GLOBAL_ITEM_REPORTCOUNT_PREFIX 0x94 /* Report Count */ +#define HID_GLOBAL_ITEM_PUSH_PREFIX 0xa4 /* Push */ +#define HID_GLOBAL_ITEM_POP_PREFIX 0xb4 /* Pop */ + +/* Local Items (HID 6.2.2.8) */ +#define HID_LOCAL_ITEM_SIZE(pfx) ((pfx)&HID_REPORT_ITEM_SIZE_MASK) +#define HID_LOCAL_ITEM_USAGE_PREFIX 0x08 /* Usage */ +#define HID_LOCAL_ITEM_USAGEMIN_PREFIX 0x18 /* Usage Minimum */ +#define HID_LOCAL_ITEM_USAGEMAX_PREFIX 0x28 /* Usage Maximum */ +#define HID_LOCAL_ITEM_DESIGNATORIDX_PREFIX 0x38 /* Designator Index */ +#define HID_LOCAL_ITEM_DESIGNATORMIN_PREFIX 0x48 /* Designator Minimum */ +#define HID_LOCAL_ITEM_DESIGNATORMAX_PREFIX 0x58 /* Designator Maximum */ +#define HID_LOCAL_ITEM_STRINGIDX_PREFIX 0x78 /* String Index */ +#define HID_LOCAL_ITEM_STRINGMIN_PREFIX 0x88 /* String Minimum */ +#define HID_LOCAL_ITEM_STRINGMAX_PREFIX 0x98 /* xx */ +#define HID_LOCAL_ITEM_DELIMITER_PREFIX 0xa8 /* Delimiter */ + +/* Modifier Keys (HID 8.3) */ +#define HID_MODIFER_LCTRL (1 << 0) /* Left Ctrl */ +#define HID_MODIFER_LSHIFT (1 << 1) /* Left Shift */ +#define HID_MODIFER_LALT (1 << 2) /* Left Alt */ +#define HID_MODIFER_LGUI (1 << 3) /* Left GUI */ +#define HID_MODIFER_RCTRL (1 << 4) /* Right Ctrl */ +#define HID_MODIFER_RSHIFT (1 << 5) /* Right Shift */ +#define HID_MODIFER_RALT (1 << 6) /* Right Alt */ +#define HID_MODIFER_RGUI (1 << 7) /* Right GUI */ + +/* Keyboard output report (1 byte) (HID B.1) */ +#define HID_KBD_OUTPUT_REPORT_NUMLOCK (1 << 0) +#define HID_KBD_OUTPUT_REPORT_CAPSLOCK (1 << 1) +#define HID_KBD_OUTPUT_REPORT_SCROLLLOCK (1 << 2) +#define HID_KBD_OUTPUT_REPORT_COMPOSE (1 << 3) +#define HID_KBD_OUTPUT_REPORT_KANA (1 << 4) + +/* Mouse input report (HID B.2) */ +#define HID_MOUSE_INPUT_REPORT_BUTTON1 (1 << 0) +#define HID_MOUSE_INPUT_REPORT_BUTTON2 (1 << 1) +#define HID_MOUSE_INPUT_REPORT_BUTTON3 (1 << 2) +#define HID_MOUSE_INPUT_REPORT_BUTTON_MASK (7) + +#define HID_MOUSE_INPUT_BUTTON_LEFT (1 << 0) +#define HID_MOUSE_INPUT_BUTTON_RIGHT (1 << 1) +#define HID_MOUSE_INPUT_BUTTON_MIDDLE (1 << 2) +#define HID_MOUSE_INPUT_BUTTON_BACKWARD (1 << 3) +#define HID_MOUSE_INPUT_BUTTON_FORWARD (1 << 4) + +/* Joystick input report (4 bytes) (HID D.1) */ +#define HID_JS_INPUT_REPORT_HATSWITCH_SHIFT (0) +#define HID_JS_INPUT_REPORT_HATSWITCH_MASK (15 << HID_JSIN_HATSWITCH_SHIFT) +#define HID_JS_INPUT_REPORT_BUTTON1 (1 << 4) +#define HID_JS_INPUT_REPORT_BUTTON2 (1 << 5) +#define HID_JS_INPUT_REPORT_BUTTON3 (1 << 6) +#define HID_JS_INPUT_REPORT_BUTTON4 (1 << 7) + +/* Usage pages (HuT 3) */ +#define HID_USAGE_PAGE_UNDEFINED 0x00 /* Undefined */ +#define HID_USAGE_PAGE_GENERIC_DCTRL 0x01 /* Generic Desktop Controls */ +#define HID_USAGE_PAGE_SIMCTRL 0x02 /* Simulation Controls */ +#define HID_USAGE_PAGE_VRCTRL 0x03 /* VR Controls */ +#define HID_USAGE_PAGE_SPORTCTRL 0x04 /* Sport Controls */ +#define HID_USAGE_PAGE_GAMECTRL 0x05 /* Game Controls */ +#define HID_USAGE_PAGE_GENERIC_DEVCTRL 0x06 /* Generic Device Controls */ +#define HID_USAGE_PAGE_KBD 0x07 /* Keyboard/Keypad */ +#define HID_USAGE_PAGE_LEDS 0x08 /* LEDs */ +#define HID_USAGE_PAGE_BUTTON 0x09 /* Button */ +#define HID_USAGE_PAGE_ORDINAL 0x0a /* Ordinal */ +#define HID_USAGE_PAGE_TELEPHONY 0x0b /* Telephony */ +#define HID_USAGE_PAGE_CONSUMER 0x0c /* Consumer */ +#define HID_USAGE_PAGE_DIGITIZER 0x0d /* Digitizer */ + /* 0x0e Reserved */ +#define HID_USAGE_PAGE_PIDPAGE 0x0f /* PID Page Physical Interface Device */ +#define HID_USAGE_PAGE_UNICODE 0x10 /* Unicode */ + /* 0x11-13 Reserved */ +#define HID_USAGE_PAGE_ALPHA_DISPLAY 0x14 /* Alphanumeric Display */ + /* 0x15-3f Reserved */ +#define HID_USAGE_PAGE_MEDICAL 0x40 /* Medical Instruments */ + /* 0x41-7f Reserved */ + /* 0x80-83 Monitor Devices */ + /* 0x84-87 Power Devices */ + /* 0x88-8b Reserved */ +#define HID_USAGE_PAGE_BARCODE_SCANNER 0x8c /* Bar Code Scanner page */ +#define HID_USAGE_PAGE_SCALE 0x8d /* Scale page */ +#define HID_USAGE_PAGE_MSR 0x8e /* Magnetic Stripe Reading (MSR) Devices */ +#define HID_USAGE_PAGE_POS 0x8f /* Point of Sale devices */ +#define HID_USAGE_PAGE_CAMERA_CTRL 0x90 /* Camera Control Page */ + +/* Generic Desktop Page Usage IDs (HuT 4) */ +#define HID_DESKTOP_USAGE_UNDEFINED 0x00 /* Undefined */ +#define HID_DESKTOP_USAGE_POINTER 0x01 /* Pointer */ +#define HID_DESKTOP_USAGE_MOUSE 0x02 /* Mouse */ + /* 0x03 Reserved */ +#define HID_DESKTOP_USAGE_JOYSTICK 0x04 /* Joystick */ +#define HID_DESKTOP_USAGE_GAMEPAD 0x05 /* Game Pad */ +#define HID_DESKTOP_USAGE_KEYBOARD 0x06 /* Keyboard */ +#define HID_DESKTOP_USAGE_KEYPAD 0x07 /* Keypad */ +#define HID_DESKTOP_USAGE_MULTIAXIS 0x08 /* Multi-axis Controller */ +#define HID_DESKTOP_USAGE_TABLET 0x09 /* Tablet PC System Controls */ + /* 0x0a-2f Reserved */ +#define HID_DESKTOP_USAGE_X 0x30 /* X */ +#define HID_DESKTOP_USAGE_Y 0x31 /* Y */ +#define HID_DESKTOP_USAGE_Z 0x32 /* Z */ +#define HID_DESKTOP_USAGE_RX 0x33 /* Rx */ +#define HID_DESKTOP_USAGE_RY 0x34 /* Ry */ +#define HID_DESKTOP_USAGE_RZ 0x35 /* Rz */ +#define HID_DESKTOP_USAGE_SLIDER 0x36 /* Slider */ +#define HID_DESKTOP_USAGE_DIAL 0x37 /* Dial */ +#define HID_DESKTOP_USAGE_WHEEL 0x38 /* Wheel */ +#define HID_DESKTOP_USAGE_HATSWITCH 0x39 /* Hat switch */ +#define HID_DESKTOP_USAGE_COUNTED 0x3a /* Counted Buffer */ +#define HID_DESKTOP_USAGE_BYTECOUNT 0x3b /* Byte Count */ +#define HID_DESKTOP_USAGE_MOTION 0x3c /* Motion Wakeup */ +#define HID_DESKTOP_USAGE_START 0x3d /* Start */ +#define HID_DESKTOP_USAGE_SELECT 0x3e /* Select */ + /* 0x3f Reserved */ +#define HID_DESKTOP_USAGE_VX 0x40 /* Vx */ +#define HID_DESKTOP_USAGE_VY 0x41 /* Vy */ +#define HID_DESKTOP_USAGE_VZ 0x42 /* Vz */ +#define HID_DESKTOP_USAGE_VBRX 0x43 /* Vbrx */ +#define HID_DESKTOP_USAGE_VBRY 0x44 /* Vbry */ +#define HID_DESKTOP_USAGE_VBRZ 0x45 /* Vbrz */ +#define HID_DESKTOP_USAGE_VNO 0x46 /* Vno */ +#define HID_DESKTOP_USAGE_FEATURE 0x47 /* Feature Notification */ +#define HID_DESKTOP_USAGE_RESOLUTION 0x48 /* Resolution Multiplier */ + /* 0x49-7f Reserved */ +#define HID_DESKTOP_USAGE_CONTROL 0x80 /* System Control */ +#define HID_DESKTOP_USAGE_POWERDOWN 0x81 /* System Power Down */ +#define HID_DESKTOP_USAGE_SLEEP 0x82 /* System Sleep */ +#define HID_DESKTOP_USAGE_WAKEUP 0x83 /* System Wake Up */ +#define HID_DESKTOP_USAGE_CONTEXT_MENU 0x84 /* System Context Menu */ +#define HID_DESKTOP_USAGE_MAIN_MENU 0x85 /* System Main Menu */ +#define HID_DESKTOP_USAGE_APP_MENU 0x86 /* System App Menu */ +#define HID_DESKTOP_USAGE_MENU_HELP 0x87 /* System Menu Help */ +#define HID_DESKTOP_USAGE_MENU_EXIT 0x88 /* System Menu Exit */ +#define HID_DESKTOP_USAGE_MENU_SELECT 0x89 /* System Menu Select */ +#define HID_DESKTOP_USAGE_MENU_RIGHT 0x8a /* System Menu Right */ +#define HID_DESKTOP_USAGE_MENU_LEFT 0x8b /* System Menu Left */ +#define HID_DESKTOP_USAGE_MENU_UP 0x8c /* System Menu Up */ +#define HID_DESKTOP_USAGE_MENU_DOWN 0x8d /* System Menu Down */ +#define HID_DESKTOP_USAGE_COLD_RESTART 0x8e /* System Cold Restart */ +#define HID_DESKTOP_USAGE_WARM_RESTART 0x8f /* System Warm Restart */ +#define HID_DESKTOP_USAGE_DPAD_UP 0x90 /* D-pad Up */ +#define HID_DESKTOP_USAGE_DPAD_DOWN 0x91 /* D-pad Down */ +#define HID_DESKTOP_USAGE_DPAD_RIGHT 0x92 /* D-pad Right */ +#define HID_DESKTOP_USAGE_DPAD_LEFT 0x93 /* D-pad Left */ + /* 0x94-9f Reserved */ +#define HID_DESKTOP_USAGE_DOCK 0xa0 /* System Dock */ +#define HID_DESKTOP_USAGE_UNDOCK 0xa1 /* System Undock */ +#define HID_DESKTOP_USAGE_SETUP 0xa2 /* System Setup */ +#define HID_DESKTOP_USAGE_BREAK 0xa3 /* System Break */ +#define HID_DESKTOP_USAGE_DEBUG_BREAK 0xa4 /* System Debugger Break */ +#define HID_DESKTOP_USAGE_APP_BREAK 0xa5 /* Application Break */ +#define HID_DESKTOP_USAGE_APP_DEBUG_BREAK 0xa6 /* Application Debugger Break */ +#define HID_DESKTOP_USAGE_MUTE 0xa7 /* System Speaker Mute */ +#define HID_DESKTOP_USAGE_HIBERNATE 0xa8 /* System Hibernate */ + /* 0xa9-af Reserved */ +#define HID_DESKTOP_USAGE_DISPLAY_INVERT 0xb0 /* System Display Invert */ +#define HID_DESKTOP_USAGE_DISPALY_INTERNAL 0xb1 /* System Display Internal */ +#define HID_DESKTOP_USAGE_DISPLAY_EXTERNAL 0xb2 /* System Display External */ +#define HID_DESKTOP_USAGE_DISPLAY_BOTH 0xb3 /* System Display Both */ +#define HID_DESKTOP_USAGE_DISPLAY_DUAL 0xb4 /* System Display Dual */ +#define HID_DESKTOP_USAGE_DISPLAY_TOGGLE 0xb5 /* System Display Toggle Int/Ext */ +#define HID_DESKTOP_USAGE_DISPLAY_SWAP 0xb6 /* System Display Swap */ +#define HID_DESKTOP_USAGE_ 0xb7 /* System Display LCD Autoscale */ + /* 0xb8-ffff Reserved */ + +/* Keyboard usage IDs (HuT 10) */ +#define HID_KBD_USAGE_NONE 0x00 /* Reserved (no event indicated) */ +#define HID_KBD_USAGE_ERRORROLLOVER 0x01 /* Keyboard ErrorRollOver */ +#define HID_KBD_USAGE_POSTFAIL 0x02 /* Keyboard POSTFail */ +#define HID_KBD_USAGE_ERRUNDEF 0x03 /* Keyboard ErrorUndefined */ +#define HID_KBD_USAGE_A 0x04 /* Keyboard a or A (B-Z follow) */ +#define HID_KBD_USAGE_1 0x1e /* Keyboard 1 (2-9 follow) */ +#define HID_KBD_USAGE_EXCLAM 0x1e /* Keyboard 1 and ! */ +#define HID_KBD_USAGE_AT 0x1f /* Keyboard 2 and @ */ +#define HID_KBD_USAGE_POUND 0x20 /* Keyboard 3 and # */ +#define HID_KBD_USAGE_DOLLAR 0x21 /* Keyboard 4 and $ */ +#define HID_KBD_USAGE_PERCENT 0x22 /* Keyboard 5 and % */ +#define HID_KBD_USAGE_CARAT 0x23 /* Keyboard 6 and ^ */ +#define HID_KBD_USAGE_AMPERSAND 0x24 /* Keyboard 7 and & */ +#define HID_KBD_USAGE_ASTERISK 0x25 /* Keyboard 8 and * */ +#define HID_KBD_USAGE_LPAREN 0x26 /* Keyboard 9 and ( */ +#define HID_KBD_USAGE_0 0x27 /* Keyboard 0 and ) */ +#define HID_KBD_USAGE_RPAREN 0x27 /* Keyboard 0 and ) */ +#define HID_KBD_USAGE_ENTER 0x28 /* Keyboard Return (ENTER) */ +#define HID_KBD_USAGE_ESCAPE 0x29 /* Keyboard ESCAPE */ +#define HID_KBD_USAGE_DELETE 0x2a /* Keyboard DELETE (Backspace) */ +#define HID_KBD_USAGE_TAB 0x2b /* Keyboard Tab */ +#define HID_KBD_USAGE_SPACE 0x2c /* Keyboard Spacebar */ +#define HID_KBD_USAGE_HYPHEN 0x2d /* Keyboard - and (underscore) */ +#define HID_KBD_USAGE_UNDERSCORE 0x2d /* Keyboard - and (underscore) */ +#define HID_KBD_USAGE_EQUAL 0x2e /* Keyboard = and + */ +#define HID_KBD_USAGE_PLUS 0x2e /* Keyboard = and + */ +#define HID_KBD_USAGE_LBRACKET 0x2f /* Keyboard [ and { */ +#define HID_KBD_USAGE_LBRACE 0x2f /* Keyboard [ and { */ +#define HID_KBD_USAGE_RBRACKET 0x30 /* Keyboard ] and } */ +#define HID_KBD_USAGE_RBRACE 0x30 /* Keyboard ] and } */ +#define HID_KBD_USAGE_BSLASH 0x31 /* Keyboard \ and | */ +#define HID_KBD_USAGE_VERTBAR 0x31 /* Keyboard \ and | */ +#define HID_KBD_USAGE_NONUSPOUND 0x32 /* Keyboard Non-US # and ~ */ +#define HID_KBD_USAGE_TILDE 0x32 /* Keyboard Non-US # and ~ */ +#define HID_KBD_USAGE_SEMICOLON 0x33 /* Keyboard ; and : */ +#define HID_KBD_USAGE_COLON 0x33 /* Keyboard ; and : */ +#define HID_KBD_USAGE_SQUOTE 0x34 /* Keyboard ' and " */ +#define HID_KBD_USAGE_DQUOUTE 0x34 /* Keyboard ' and " */ +#define HID_KBD_USAGE_GACCENT 0x35 /* Keyboard Grave Accent and Tilde */ +#define HID_KBD_USAGE_GTILDE 0x35 /* Keyboard Grave Accent and Tilde */ +#define HID_KBD_USAGE_COMMON 0x36 /* Keyboard , and < */ +#define HID_KBD_USAGE_LT 0x36 /* Keyboard , and < */ +#define HID_KBD_USAGE_PERIOD 0x37 /* Keyboard . and > */ +#define HID_KBD_USAGE_GT 0x37 /* Keyboard . and > */ +#define HID_KBD_USAGE_DIV 0x38 /* Keyboard / and ? */ +#define HID_KBD_USAGE_QUESTION 0x38 /* Keyboard / and ? */ +#define HID_KBD_USAGE_CAPSLOCK 0x39 /* Keyboard Caps Lock */ +#define HID_KBD_USAGE_F1 0x3a /* Keyboard F1 */ +#define HID_KBD_USAGE_F2 0x3b /* Keyboard F2 */ +#define HID_KBD_USAGE_F3 0x3c /* Keyboard F3 */ +#define HID_KBD_USAGE_F4 0x3d /* Keyboard F4 */ +#define HID_KBD_USAGE_F5 0x3e /* Keyboard F5 */ +#define HID_KBD_USAGE_F6 0x3f /* Keyboard F6 */ +#define HID_KBD_USAGE_F7 0x40 /* Keyboard F7 */ +#define HID_KBD_USAGE_F8 0x41 /* Keyboard F8 */ +#define HID_KBD_USAGE_F9 0x42 /* Keyboard F9 */ +#define HID_KBD_USAGE_F10 0x43 /* Keyboard F10 */ +#define HID_KBD_USAGE_F11 0x44 /* Keyboard F11 */ +#define HID_KBD_USAGE_F12 0x45 /* Keyboard F12 */ +#define HID_KBD_USAGE_PRINTSCN 0x46 /* Keyboard PrintScreen */ +#define HID_KBD_USAGE_SCROLLLOCK 0x47 /* Keyboard Scroll Lock */ +#define HID_KBD_USAGE_PAUSE 0x48 /* Keyboard Pause */ +#define HID_KBD_USAGE_INSERT 0x49 /* Keyboard Insert */ +#define HID_KBD_USAGE_HOME 0x4a /* Keyboard Home */ +#define HID_KBD_USAGE_PAGEUP 0x4b /* Keyboard PageUp */ +#define HID_KBD_USAGE_DELFWD 0x4c /* Keyboard Delete Forward */ +#define HID_KBD_USAGE_END 0x4d /* Keyboard End */ +#define HID_KBD_USAGE_PAGEDOWN 0x4e /* Keyboard PageDown */ +#define HID_KBD_USAGE_RIGHT 0x4f /* eyboard RightArrow */ +#define HID_KBD_USAGE_LEFT 0x50 /* Keyboard LeftArrow */ +#define HID_KBD_USAGE_DOWN 0x51 /* Keyboard DownArrow */ +#define HID_KBD_USAGE_UP 0x52 /* Keyboard UpArrow */ +#define HID_KBD_USAGE_KPDNUMLOCK 0x53 /* Keypad Num Lock and Clear */ +#define HID_KBD_USAGE_KPDNUMLOCKCLEAR 0x53 /* Keypad Num Lock and Clear */ +#define HID_KBD_USAGE_KPDDIV 0x54 /* Keypad / */ +#define HID_KBD_USAGE_KPDMUL 0x55 /* Keypad * */ +#define HID_KBD_USAGE_KPDHMINUS 0x56 /* Keypad - */ +#define HID_KBD_USAGE_KPDPLUS 0x57 /* Keypad + */ +#define HID_KBD_USAGE_KPDEMTER 0x58 /* Keypad ENTER */ +#define HID_KBD_USAGE_KPD1 0x59 /* Keypad 1 (2-9 follow) */ +#define HID_KBD_USAGE_KPDEND 0x59 /* Keypad 1 and End */ +#define HID_KBD_USAGE_KPDDOWN 0x5a /* Keypad 2 and Down Arrow */ +#define HID_KBD_USAGE_KPDPAGEDN 0x5b /* Keypad 3 and PageDn */ +#define HID_KBD_USAGE_KPDLEFT 0x5c /* Keypad 4 and Left Arrow */ +#define HID_KBD_USAGE_KPDRIGHT 0x5e /* Keypad 6 and Right Arrow */ +#define HID_KBD_USAGE_KPDHOME 0x5f /* Keypad 7 and Home */ +#define HID_KBD_USAGE_KPDUP 0x60 /* Keypad 8 and Up Arrow */ +#define HID_KBD_USAGE_KPDPAGEUP 0x61 /* Keypad 9 and PageUp */ +#define HID_KBD_USAGE_KPD0 0x62 /* Keypad 0 and Insert */ +#define HID_KBD_USAGE_KPDINSERT 0x62 /* Keypad 0 and Insert */ +#define HID_KBD_USAGE_KPDDECIMALPT 0x63 /* Keypad . and Delete */ +#define HID_KBD_USAGE_KPDDELETE 0x63 /* Keypad . and Delete */ +#define HID_KBD_USAGE_NONSLASH 0x64 /* Keyboard Non-US \ and | */ +#define HID_KBD_USAGE_NONUSVERT 0x64 /* Keyboard Non-US \ and | */ +#define HID_KBD_USAGE_APPLICATION 0x65 /* Keyboard Application */ +#define HID_KBD_USAGE_POWER 0x66 /* Keyboard Power */ +#define HID_KBD_USAGE_KPDEQUAL 0x67 /* Keypad = */ +#define HID_KBD_USAGE_F13 0x68 /* Keyboard F13 */ +#define HID_KBD_USAGE_F14 0x69 /* Keyboard F14 */ +#define HID_KBD_USAGE_F15 0x6a /* Keyboard F15 */ +#define HID_KBD_USAGE_F16 0x6b /* Keyboard F16 */ +#define HID_KBD_USAGE_F17 0x6c /* Keyboard F17 */ +#define HID_KBD_USAGE_F18 0x6d /* Keyboard F18 */ +#define HID_KBD_USAGE_F19 0x6e /* Keyboard F19 */ +#define HID_KBD_USAGE_F20 0x6f /* Keyboard F20 */ +#define HID_KBD_USAGE_F21 0x70 /* Keyboard F21 */ +#define HID_KBD_USAGE_F22 0x71 /* Keyboard F22 */ +#define HID_KBD_USAGE_F23 0x72 /* Keyboard F23 */ +#define HID_KBD_USAGE_F24 0x73 /* Keyboard F24 */ +#define HID_KBD_USAGE_EXECUTE 0x74 /* Keyboard Execute */ +#define HID_KBD_USAGE_HELP 0x75 /* Keyboard Help */ +#define HID_KBD_USAGE_MENU 0x76 /* Keyboard Menu */ +#define HID_KBD_USAGE_SELECT 0x77 /* Keyboard Select */ +#define HID_KBD_USAGE_STOP 0x78 /* Keyboard Stop */ +#define HID_KBD_USAGE_AGAIN 0x79 /* Keyboard Again */ +#define HID_KBD_USAGE_UNDO 0x7a /* Keyboard Undo */ +#define HID_KBD_USAGE_CUT 0x7b /* Keyboard Cut */ +#define HID_KBD_USAGE_COPY 0x7c /* Keyboard Copy */ +#define HID_KBD_USAGE_PASTE 0x7d /* Keyboard Paste */ +#define HID_KBD_USAGE_FIND 0x7e /* Keyboard Find */ +#define HID_KBD_USAGE_MUTE 0x7f /* Keyboard Mute */ +#define HID_KBD_USAGE_VOLUP 0x80 /* Keyboard Volume Up */ +#define HID_KBD_USAGE_VOLDOWN 0x81 /* Keyboard Volume Down */ +#define HID_KBD_USAGE_LCAPSLOCK 0x82 /* Keyboard Locking Caps Lock */ +#define HID_KBD_USAGE_LNUMLOCK 0x83 /* Keyboard Locking Num Lock */ +#define HID_KBD_USAGE_LSCROLLLOCK 0x84 /* Keyboard Locking Scroll Lock */ +#define HID_KBD_USAGE_KPDCOMMA 0x85 /* Keypad Comma */ +#define HID_KBD_USAGE_KPDEQUALSIGN 0x86 /* Keypad Equal Sign */ +#define HID_KBD_USAGE_INTERNATIONAL1 0x87 /* Keyboard International 1 */ +#define HID_KBD_USAGE_INTERNATIONAL2 0x88 /* Keyboard International 2 */ +#define HID_KBD_USAGE_INTERNATIONAL3 0x89 /* Keyboard International 3 */ +#define HID_KBD_USAGE_INTERNATIONAL4 0x8a /* Keyboard International 4 */ +#define HID_KBD_USAGE_INTERNATIONAL5 0x8b /* Keyboard International 5 */ +#define HID_KBD_USAGE_INTERNATIONAL6 0x8c /* Keyboard International 6 */ +#define HID_KBD_USAGE_INTERNATIONAL7 0x8d /* Keyboard International 7 */ +#define HID_KBD_USAGE_INTERNATIONAL8 0x8e /* Keyboard International 8 */ +#define HID_KBD_USAGE_INTERNATIONAL9 0x8f /* Keyboard International 9 */ +#define HID_KBD_USAGE_LANG1 0x90 /* Keyboard LANG1 */ +#define HID_KBD_USAGE_LANG2 0x91 /* Keyboard LANG2 */ +#define HID_KBD_USAGE_LANG3 0x92 /* Keyboard LANG3 */ +#define HID_KBD_USAGE_LANG4 0x93 /* Keyboard LANG4 */ +#define HID_KBD_USAGE_LANG5 0x94 /* Keyboard LANG5 */ +#define HID_KBD_USAGE_LANG6 0x95 /* Keyboard LANG6 */ +#define HID_KBD_USAGE_LANG7 0x96 /* Keyboard LANG7 */ +#define HID_KBD_USAGE_LANG8 0x97 /* Keyboard LANG8 */ +#define HID_KBD_USAGE_LANG9 0x98 /* Keyboard LANG9 */ +#define HID_KBD_USAGE_ALTERASE 0x99 /* Keyboard Alternate Erase */ +#define HID_KBD_USAGE_SYSREQ 0x9a /* Keyboard SysReq/Attention */ +#define HID_KBD_USAGE_CANCEL 0x9b /* Keyboard Cancel */ +#define HID_KBD_USAGE_CLEAR 0x9c /* Keyboard Clear */ +#define HID_KBD_USAGE_PRIOR 0x9d /* Keyboard Prior */ +#define HID_KBD_USAGE_RETURN 0x9e /* Keyboard Return */ +#define HID_KBD_USAGE_SEPARATOR 0x9f /* Keyboard Separator */ +#define HID_KBD_USAGE_OUT 0xa0 /* Keyboard Out */ +#define HID_KBD_USAGE_OPER 0xa1 /* Keyboard Oper */ +#define HID_KBD_USAGE_CLEARAGAIN 0xa2 /* Keyboard Clear/Again */ +#define HID_KBD_USAGE_CLRSEL 0xa3 /* Keyboard CrSel/Props */ +#define HID_KBD_USAGE_EXSEL 0xa4 /* Keyboard ExSel */ +#define HID_KBD_USAGE_KPD00 0xb0 /* Keypad 00 */ +#define HID_KBD_USAGE_KPD000 0xb1 /* Keypad 000 */ +#define HID_KBD_USAGE_THOUSEPARATOR 0xb2 /* Thousands Separator */ +#define HID_KBD_USAGE_DECSEPARATOR 0xb3 /* Decimal Separator */ +#define HID_KBD_USAGE_CURRUNIT 0xb4 /* Currency Unit */ +#define HID_KBD_USAGE_CURRSUBUNIT 0xb5 /* Currency Sub-unit */ +#define HID_KBD_USAGE_KPDLPAREN 0xb6 /* Keypad ( */ +#define HID_KBD_USAGE_KPDRPAREN 0xb7 /* Keypad ) */ +#define HID_KBD_USAGE_KPDLBRACE 0xb8 /* Keypad { */ +#define HID_KBD_USAGE_KPDRBRACE 0xb9 /* Keypad } */ +#define HID_KBD_USAGE_KPDTAB 0xba /* Keypad Tab */ +#define HID_KBD_USAGE_KPDBACKSPACE 0xbb /* Keypad Backspace */ +#define HID_KBD_USAGE_KPDA 0xbc /* Keypad A (B-F follow) */ +#define HID_KBD_USAGE_KPDXOR 0xc2 /* Keypad XOR */ +#define HID_KBD_USAGE_KPDEXP 0xc3 /* Keypad ^ */ +#define HID_KBD_USAGE_KPDPERCENT 0xc4 /* Keypad % */ +#define HID_KBD_USAGE_KPDLT 0xc5 /* Keypad < */ +#define HID_KBD_USAGE_KPDGT 0xc6 /* Keypad > */ +#define HID_KBD_USAGE_KPDAMPERSAND 0xc7 /* Keypad & */ +#define HID_KBD_USAGE_KPDAND 0xc8 /* Keypad && */ +#define HID_KBD_USAGE_KPDVERT 0xc9 /* Keypad | */ +#define HID_KBD_USAGE_KPDOR 0xca /* Keypad || */ +#define HID_KBD_USAGE_KPDCOLON 0xcb /* Keypad : */ +#define HID_KBD_USAGE_KPDPOUND 0xcc /* Keypad # */ +#define HID_KBD_USAGE_KPDSPACE 0xcd /* Keypad Space */ +#define HID_KBD_USAGE_KPDAT 0xce /* Keypad @ */ +#define HID_KBD_USAGE_KPDEXCLAM 0xcf /* Keypad ! */ +#define HID_KBD_USAGE_KPDMEMSTORE 0xd0 /* Keypad Memory Store */ +#define HID_KBD_USAGE_KPDMEMRECALL 0xd1 /* Keypad Memory Recall */ +#define HID_KBD_USAGE_KPDMEMCLEAR 0xd2 /* Keypad Memory Clear */ +#define HID_KBD_USAGE_KPDMEMADD 0xd3 /* Keypad Memory Add */ +#define HID_KBD_USAGE_KPDMEMSUB 0xd4 /* Keypad Memory Subtract */ +#define HID_KBD_USAGE_KPDMEMMULT 0xd5 /* Keypad Memory Multiply */ +#define HID_KBD_USAGE_KPDMEMDIV 0xd6 /* Keypad Memory Divide */ +#define HID_KBD_USAGE_KPDPLUSMINUS 0xd7 /* Keypad +/- */ +#define HID_KBD_USAGE_KPDCLEAR 0xd8 /* Keypad Clear */ +#define HID_KBD_USAGE_KPDCLEARENTRY 0xd9 /* Keypad Clear Entry */ +#define HID_KBD_USAGE_KPDBINARY 0xda /* Keypad Binary */ +#define HID_KBD_USAGE_KPDOCTAL 0xdb /* Keypad Octal */ +#define HID_KBD_USAGE_KPDDECIMAL 0xdc /* Keypad Decimal */ +#define HID_KBD_USAGE_KPDHEXADECIMAL 0xdd /* Keypad Hexadecimal */ +#define HID_KBD_USAGE_LCTRL 0xe0 /* Keyboard LeftControl */ +#define HID_KBD_USAGE_LSHIFT 0xe1 /* Keyboard LeftShift */ +#define HID_KBD_USAGE_LALT 0xe2 /* Keyboard LeftAlt */ +#define HID_KBD_USAGE_LGUI 0xe3 /* Keyboard Left GUI */ +#define HID_KBD_USAGE_RCTRL 0xe4 /* Keyboard RightControl */ +#define HID_KBD_USAGE_RSHIFT 0xe5 /* Keyboard RightShift */ +#define HID_KBD_USAGE_RALT 0xe6 /* Keyboard RightAlt */ +#define HID_KBD_USAGE_RGUI 0xe7 /* Keyboard Right GUI */ + +#define HID_KBD_USAGE_MAX 0xe7 + +/* HID Report Definitions */ +struct usb_hid_class_subdescriptor { + uint8_t bDescriptorType;/* Class descriptor type (See 7.1) */ + uint16_t wDescriptorLength;/* Size of the report descriptor */ +} __PACKED; + +struct usb_hid_descriptor { + uint8_t bLength; /* Size of the HID descriptor */ + uint8_t bDescriptorType;/* HID descriptor type */ + uint16_t bcdHID;/* HID class specification release */ + uint8_t bCountryCode;/* Country code */ + uint8_t bNumDescriptors;/* Number of descriptors (>=1) */ + + /* + * Specification says at least one Class Descriptor needs to + * be present (Report Descriptor). + */ + struct usb_hid_class_subdescriptor subdesc[1]; +} __PACKED; + +/* Standard Reports *********************************************************/ + +/* Keyboard input report (8 bytes) (HID B.1) */ +struct usb_hid_kbd_report +{ + uint8_t modifier; /* Modifier keys. See HID_MODIFER_* definitions */ + uint8_t reserved; + uint8_t key[6]; /* Keycode 1-6 */ +}; + +/* Keyboard output report (1 byte) (HID B.1), + * see USBHID_KBDOUT_* definitions + */ + +/* Mouse input report (HID B.2) */ +struct usb_hid_mouse_report +{ + uint8_t buttons; /* See HID_MOUSE_INPUT_BUTTON_* definitions */ + uint8_t xdisp; /* X displacement */ + uint8_t ydisp; /* y displacement */ + /* Device specific additional bytes may follow */ +#ifdef CONFIG_INPUT_MOUSE_WHEEL + uint8_t wdisp; /* Wheel displacement */ +#endif +}; + +/* Joystick input report (1 bytes) (HID D.1) */ +struct usb_hid_js_report +{ + uint8_t xpos; /* X position */ + uint8_t ypos; /* X position */ + uint8_t buttons; /* See USBHID_JSIN_* definitions */ + uint8_t throttle; /* Throttle */ +}; + +#endif /* USB_HID_H */ diff --git a/Code/DAP_X033/DAP/CherryUSB/class/hid/usbd_hid.c b/Code/DAP_X033/DAP/CherryUSB/class/hid/usbd_hid.c new file mode 100644 index 0000000..d98b82e --- /dev/null +++ b/Code/DAP_X033/DAP/CherryUSB/class/hid/usbd_hid.c @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_hid.h" + +static int hid_class_interface_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + USB_LOG_DBG("HID Class request: " + "bRequest 0x%02x\r\n", + setup->bRequest); + + uint8_t intf_num = LO_BYTE(setup->wIndex); + + switch (setup->bRequest) { + case HID_REQUEST_GET_REPORT: + /* report id ,report type */ + usbd_hid_get_report(busid, intf_num, LO_BYTE(setup->wValue), HI_BYTE(setup->wValue), data, len); + break; + case HID_REQUEST_GET_IDLE: + (*data)[0] = usbd_hid_get_idle(busid, intf_num, LO_BYTE(setup->wValue)); + *len = 1; + break; + case HID_REQUEST_GET_PROTOCOL: + (*data)[0] = usbd_hid_get_protocol(busid, intf_num); + *len = 1; + break; + case HID_REQUEST_SET_REPORT: + /* report id ,report type, report, report len */ + usbd_hid_set_report(busid, intf_num, LO_BYTE(setup->wValue), HI_BYTE(setup->wValue), *data, *len); + break; + case HID_REQUEST_SET_IDLE: + /* report id, duration */ + usbd_hid_set_idle(busid, intf_num, LO_BYTE(setup->wValue), HI_BYTE(setup->wValue)); + break; + case HID_REQUEST_SET_PROTOCOL: + /* protocol */ + usbd_hid_set_protocol(busid, intf_num, LO_BYTE(setup->wValue)); + break; + + default: + USB_LOG_WRN("Unhandled HID Class bRequest 0x%02x\r\n", setup->bRequest); + return -1; + } + + return 0; +} + +struct usbd_interface *usbd_hid_init_intf(uint8_t busid, struct usbd_interface *intf, const uint8_t *desc, uint32_t desc_len) +{ + intf->class_interface_handler = hid_class_interface_request_handler; + intf->class_endpoint_handler = NULL; + intf->vendor_handler = NULL; + intf->notify_handler = NULL; + + intf->hid_report_descriptor = desc; + intf->hid_report_descriptor_len = desc_len; + return intf; +} + +__WEAK void usbd_hid_get_report(uint8_t busid, uint8_t intf, uint8_t report_id, uint8_t report_type, uint8_t **data, uint32_t *len) +{ + (*data[0]) = 0; + *len = 1; +} + +__WEAK uint8_t usbd_hid_get_idle(uint8_t busid, uint8_t intf, uint8_t report_id) +{ + return 0; +} + +__WEAK uint8_t usbd_hid_get_protocol(uint8_t busid, uint8_t intf) +{ + return 0; +} + +__WEAK void usbd_hid_set_report(uint8_t busid, uint8_t intf, uint8_t report_id, uint8_t report_type, uint8_t *report, uint32_t report_len) +{ +} + +__WEAK void usbd_hid_set_idle(uint8_t busid, uint8_t intf, uint8_t report_id, uint8_t duration) +{ +} + +__WEAK void usbd_hid_set_protocol(uint8_t busid, uint8_t intf, uint8_t protocol) +{ +} \ No newline at end of file diff --git a/Code/DAP_X033/DAP/CherryUSB/class/hid/usbd_hid.h b/Code/DAP_X033/DAP/CherryUSB/class/hid/usbd_hid.h new file mode 100644 index 0000000..d5c3484 --- /dev/null +++ b/Code/DAP_X033/DAP/CherryUSB/class/hid/usbd_hid.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_HID_H +#define USBD_HID_H + +#include "usb_hid.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Init hid interface driver */ +struct usbd_interface *usbd_hid_init_intf(uint8_t busid, struct usbd_interface *intf, const uint8_t *desc, uint32_t desc_len); + +/* Register desc api */ +void usbd_hid_descriptor_register(uint8_t busid, uint8_t intf_num, const uint8_t *desc); +void usbd_hid_report_descriptor_register(uint8_t busid, uint8_t intf_num, const uint8_t *desc, uint32_t desc_len); + +/* Setup request command callback api */ +void usbd_hid_get_report(uint8_t busid, uint8_t intf, uint8_t report_id, uint8_t report_type, uint8_t **data, uint32_t *len); +uint8_t usbd_hid_get_idle(uint8_t busid, uint8_t intf, uint8_t report_id); +uint8_t usbd_hid_get_protocol(uint8_t busid, uint8_t intf); +void usbd_hid_set_report(uint8_t busid, uint8_t intf, uint8_t report_id, uint8_t report_type, uint8_t *report, uint32_t report_len); +void usbd_hid_set_idle(uint8_t busid, uint8_t intf, uint8_t report_id, uint8_t duration); +void usbd_hid_set_protocol(uint8_t busid, uint8_t intf, uint8_t protocol); + +#ifdef __cplusplus +} +#endif + +#endif /* USBD_HID_H */ diff --git a/Code/DAP_X033/DAP/CherryUSB/common/usb_dc.h b/Code/DAP_X033/DAP/CherryUSB/common/usb_dc.h new file mode 100644 index 0000000..ca6c10e --- /dev/null +++ b/Code/DAP_X033/DAP/CherryUSB/common/usb_dc.h @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_DC_H +#define USB_DC_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief init device controller registers. + * @return On success will return 0, and others indicate fail. + */ +int usb_dc_init(uint8_t busid); + +/** + * @brief deinit device controller registers. + * @return On success will return 0, and others indicate fail. + */ +int usb_dc_deinit(uint8_t busid); + +/** + * @brief Set USB device address + * + * @param[in] addr Device address + * + * @return On success will return 0, and others indicate fail. + */ +int usbd_set_address(uint8_t busid, const uint8_t addr); + +/** + * @brief Get USB device speed + * + * @param[in] port port index + * + * @return port speed, USB_SPEED_LOW or USB_SPEED_FULL or USB_SPEED_HIGH + */ +uint8_t usbd_get_port_speed(uint8_t busid, const uint8_t port); + +/** + * @brief configure and enable endpoint. + * + * @param [in] ep_cfg Endpoint config. + * + * @return On success will return 0, and others indicate fail. + */ +int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep); + +/** + * @brief Disable the selected endpoint + * + * @param[in] ep Endpoint address + * + * @return On success will return 0, and others indicate fail. + */ +int usbd_ep_close(uint8_t busid, const uint8_t ep); + +/** + * @brief Set stall condition for the selected endpoint + * + * @param[in] ep Endpoint address + * + * + * @return On success will return 0, and others indicate fail. + */ +int usbd_ep_set_stall(uint8_t busid, const uint8_t ep); + +/** + * @brief Clear stall condition for the selected endpoint + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return On success will return 0, and others indicate fail. + */ +int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep); + +/** + * @brief Check if the selected endpoint is stalled + * + * @param[in] ep Endpoint address + * + * @param[out] stalled Endpoint stall status + * + * @return On success will return 0, and others indicate fail. + */ +int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled); + +/** + * @brief Setup in ep transfer setting and start transfer. + * + * This function is asynchronous. + * This function is similar to uart with tx dma. + * + * This function is called to write data to the specified endpoint. The + * supplied usbd_endpoint_callback function will be called when data is transmitted + * out. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data Pointer to data to write + * @param[in] data_len Length of the data requested to write. This may + * be zero for a zero length status packet. + * @return 0 on success, negative errno code on fail. + */ +int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len); + +/** + * @brief Setup out ep transfer setting and start transfer. + * + * This function is asynchronous. + * This function is similar to uart with rx dma. + * + * This function is called to read data to the specified endpoint. The + * supplied usbd_endpoint_callback function will be called when data is received + * in. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data Pointer to data to read + * @param[in] data_len Max length of the data requested to read. + * + * @return 0 on success, negative errno code on fail. + */ +int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len); + +/* usb dcd irq callback */ + +/** + * @brief Usb connect irq callback. + */ +void usbd_event_connect_handler(uint8_t busid); + +/** + * @brief Usb disconnect irq callback. + */ +void usbd_event_disconnect_handler(uint8_t busid); + +/** + * @brief Usb resume irq callback. + */ +void usbd_event_resume_handler(uint8_t busid); + +/** + * @brief Usb suspend irq callback. + */ +void usbd_event_suspend_handler(uint8_t busid); + +/** + * @brief Usb reset irq callback. + */ +void usbd_event_reset_handler(uint8_t busid); + +/** + * @brief Usb setup packet recv irq callback. + * @param[in] psetup setup packet. + */ +void usbd_event_ep0_setup_complete_handler(uint8_t busid, uint8_t *psetup); + +/** + * @brief In ep transfer complete irq callback. + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] nbytes How many nbytes have transferred. + */ +void usbd_event_ep_in_complete_handler(uint8_t busid, uint8_t ep, uint32_t nbytes); + +/** + * @brief Out ep transfer complete irq callback. + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] nbytes How many nbytes have transferred. + */ +void usbd_event_ep_out_complete_handler(uint8_t busid, uint8_t ep, uint32_t nbytes); + +#ifdef CONFIG_USBDEV_TEST_MODE +/** + * @brief Usb execute test mode + * @param[in] busid device busid + * @param[in] test_mode usb test mode + */ +void usbd_execute_test_mode(uint8_t busid, uint8_t test_mode); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* USB_DC_H */ diff --git a/Code/DAP_X033/DAP/CherryUSB/common/usb_def.h b/Code/DAP_X033/DAP/CherryUSB/common/usb_def.h new file mode 100644 index 0000000..8fc76d1 --- /dev/null +++ b/Code/DAP_X033/DAP/CherryUSB/common/usb_def.h @@ -0,0 +1,699 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_DEF_H +#define USB_DEF_H + +/* Useful define */ +#define USB_1_1 0x0110 +#define USB_2_0 0x0200 +/* Set USB version to 2.1 so that the host will request the BOS descriptor */ +#define USB_2_1 0x0210 +#define USB_3_0 0x0300 +#define USB_3_1 0x0310 +#define USB_3_2 0x0320 + +/* Device speeds */ +#define USB_SPEED_UNKNOWN 0 /* Transfer rate not yet set */ +#define USB_SPEED_LOW 1 /* USB 1.1 */ +#define USB_SPEED_FULL 2 /* USB 1.1 */ +#define USB_SPEED_HIGH 3 /* USB 2.0 */ +#define USB_SPEED_WIRELESS 4 /* Wireless USB 2.5 */ +#define USB_SPEED_SUPER 5 /* USB 3.0 */ +#define USB_SPEED_SUPER_PLUS 6 /* USB 3.1 */ + +/* Maximum number of devices per controller */ +#define USB_MAX_DEVICES (127) + +/* Default USB control EP, always 0 and 0x80 */ +#define USB_CONTROL_OUT_EP0 0 +#define USB_CONTROL_IN_EP0 0x80 + +/**< maximum packet size (MPS) for EP 0 */ +#define USB_CTRL_EP_MPS 64 + +/* USB PID Types */ +#define USB_PID_OUT (0x01) /* Tokens */ +#define USB_PID_IN (0x09) +#define USB_PID_SOF (0x05) +#define USB_PID_SETUP (0x0d) + +#define USB_PID_DATA0 (0x03) /* Data */ +#define USB_PID_DATA1 (0x0b) +#define USB_PID_DATA2 (0x07) +#define USB_PID_MDATA (0x0f) + +#define USB_PID_ACK (0x02) /* Handshake */ +#define USB_PID_NAK (0x0a) +#define USB_PID_STALL (0x0e) +#define USB_PID_NYET (0x06) + +#define USB_PID_PRE (0x0c) /* Special */ +#define USB_PID_ERR (0x0c) +#define USB_PID_SPLIT (0x08) +#define USB_PID_PING (0x04) +#define USB_PID_RESERVED (0x00) + +#define USB_REQUEST_DIR_SHIFT 7U /* Bits 7: Request dir */ +#define USB_REQUEST_DIR_OUT (0U << USB_REQUEST_DIR_SHIFT) /* Bit 7=0: Host-to-device */ +#define USB_REQUEST_DIR_IN (1U << USB_REQUEST_DIR_SHIFT) /* Bit 7=1: Device-to-host */ +#define USB_REQUEST_DIR_MASK (1U << USB_REQUEST_DIR_SHIFT) /* Bit 7=1: Direction bit */ + +#define USB_REQUEST_TYPE_SHIFT 5U /* Bits 5:6: Request type */ +#define USB_REQUEST_STANDARD (0U << USB_REQUEST_TYPE_SHIFT) +#define USB_REQUEST_CLASS (1U << USB_REQUEST_TYPE_SHIFT) +#define USB_REQUEST_VENDOR (2U << USB_REQUEST_TYPE_SHIFT) +#define USB_REQUEST_RESERVED (3U << USB_REQUEST_TYPE_SHIFT) +#define USB_REQUEST_TYPE_MASK (3U << USB_REQUEST_TYPE_SHIFT) + +#define USB_REQUEST_RECIPIENT_SHIFT 0U /* Bits 0:4: Recipient */ +#define USB_REQUEST_RECIPIENT_DEVICE (0U << USB_REQUEST_RECIPIENT_SHIFT) +#define USB_REQUEST_RECIPIENT_INTERFACE (1U << USB_REQUEST_RECIPIENT_SHIFT) +#define USB_REQUEST_RECIPIENT_ENDPOINT (2U << USB_REQUEST_RECIPIENT_SHIFT) +#define USB_REQUEST_RECIPIENT_OTHER (3U << USB_REQUEST_RECIPIENT_SHIFT) +#define USB_REQUEST_RECIPIENT_MASK (3U << USB_REQUEST_RECIPIENT_SHIFT) + +/* USB Standard Request Codes */ +#define USB_REQUEST_GET_STATUS 0x00 +#define USB_REQUEST_CLEAR_FEATURE 0x01 +#define USB_REQUEST_SET_FEATURE 0x03 +#define USB_REQUEST_SET_ADDRESS 0x05 +#define USB_REQUEST_GET_DESCRIPTOR 0x06 +#define USB_REQUEST_SET_DESCRIPTOR 0x07 +#define USB_REQUEST_GET_CONFIGURATION 0x08 +#define USB_REQUEST_SET_CONFIGURATION 0x09 +#define USB_REQUEST_GET_INTERFACE 0x0A +#define USB_REQUEST_SET_INTERFACE 0x0B +#define USB_REQUEST_SYNCH_FRAME 0x0C +#define USB_REQUEST_SET_ENCRYPTION 0x0D +#define USB_REQUEST_GET_ENCRYPTION 0x0E +#define USB_REQUEST_RPIPE_ABORT 0x0E +#define USB_REQUEST_SET_HANDSHAKE 0x0F +#define USB_REQUEST_RPIPE_RESET 0x0F +#define USB_REQUEST_GET_HANDSHAKE 0x10 +#define USB_REQUEST_SET_CONNECTION 0x11 +#define USB_REQUEST_SET_SECURITY_DATA 0x12 +#define USB_REQUEST_GET_SECURITY_DATA 0x13 +#define USB_REQUEST_SET_WUSB_DATA 0x14 +#define USB_REQUEST_LOOPBACK_DATA_WRITE 0x15 +#define USB_REQUEST_LOOPBACK_DATA_READ 0x16 +#define USB_REQUEST_SET_INTERFACE_DS 0x17 + +/* USB Standard Feature selectors */ +#define USB_FEATURE_ENDPOINT_HALT 0 +#define USB_FEATURE_SELF_POWERED 0 +#define USB_FEATURE_REMOTE_WAKEUP 1 +#define USB_FEATURE_TEST_MODE 2 +#define USB_FEATURE_BATTERY 2 +#define USB_FEATURE_BHNPENABLE 3 +#define USB_FEATURE_WUSBDEVICE 3 +#define USB_FEATURE_AHNPSUPPORT 4 +#define USB_FEATURE_AALTHNPSUPPORT 5 +#define USB_FEATURE_DEBUGMODE 6 + +/* USB GET_STATUS Bit Values */ +#define USB_GETSTATUS_ENDPOINT_HALT 0x01 +#define USB_GETSTATUS_SELF_POWERED 0x01 +#define USB_GETSTATUS_REMOTE_WAKEUP 0x02 + +/* USB Descriptor Types */ +#define USB_DESCRIPTOR_TYPE_DEVICE 0x01U +#define USB_DESCRIPTOR_TYPE_CONFIGURATION 0x02U +#define USB_DESCRIPTOR_TYPE_STRING 0x03U +#define USB_DESCRIPTOR_TYPE_INTERFACE 0x04U +#define USB_DESCRIPTOR_TYPE_ENDPOINT 0x05U +#define USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER 0x06U +#define USB_DESCRIPTOR_TYPE_OTHER_SPEED 0x07U +#define USB_DESCRIPTOR_TYPE_INTERFACE_POWER 0x08U +#define USB_DESCRIPTOR_TYPE_OTG 0x09U +#define USB_DESCRIPTOR_TYPE_DEBUG 0x0AU +#define USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION 0x0BU +#define USB_DESCRIPTOR_TYPE_BINARY_OBJECT_STORE 0x0FU +#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY 0x10U +#define USB_DESCRIPTOR_TYPE_WIRELESS_ENDPOINTCOMP 0x11U + +/* Class Specific Descriptor */ +#define USB_CS_DESCRIPTOR_TYPE_DEVICE 0x21U +#define USB_CS_DESCRIPTOR_TYPE_CONFIGURATION 0x22U +#define USB_CS_DESCRIPTOR_TYPE_STRING 0x23U +#define USB_CS_DESCRIPTOR_TYPE_INTERFACE 0x24U +#define USB_CS_DESCRIPTOR_TYPE_ENDPOINT 0x25U + +#define USB_DESCRIPTOR_TYPE_SUPERSPEED_ENDPOINT_COMPANION 0x30U +#define USB_DESCRIPTOR_TYPE_SUPERSPEED_ISO_ENDPOINT_COMPANION 0x31U + +/* USB Device Classes */ +#define USB_DEVICE_CLASS_RESERVED 0x00 +#define USB_DEVICE_CLASS_AUDIO 0x01 +#define USB_DEVICE_CLASS_CDC 0x02 +#define USB_DEVICE_CLASS_HID 0x03 +#define USB_DEVICE_CLASS_MONITOR 0x04 +#define USB_DEVICE_CLASS_PHYSICAL 0x05 +#define USB_DEVICE_CLASS_IMAGE 0x06 +#define USB_DEVICE_CLASS_PRINTER 0x07 +#define USB_DEVICE_CLASS_MASS_STORAGE 0x08 +#define USB_DEVICE_CLASS_HUB 0x09 +#define USB_DEVICE_CLASS_CDC_DATA 0x0a +#define USB_DEVICE_CLASS_SMART_CARD 0x0b +#define USB_DEVICE_CLASS_SECURITY 0x0d +#define USB_DEVICE_CLASS_VIDEO 0x0e +#define USB_DEVICE_CLASS_HEALTHCARE 0x0f +#define USB_DEVICE_CLASS_DIAG_DEVICE 0xdc +#define USB_DEVICE_CLASS_WIRELESS 0xe0 +#define USB_DEVICE_CLASS_MISC 0xef +#define USB_DEVICE_CLASS_APP_SPECIFIC 0xfe +#define USB_DEVICE_CLASS_VEND_SPECIFIC 0xff + +/* usb string index define */ +#define USB_STRING_LANGID_INDEX 0x00 +#define USB_STRING_MFC_INDEX 0x01 +#define USB_STRING_PRODUCT_INDEX 0x02 +#define USB_STRING_SERIAL_INDEX 0x03 +#define USB_STRING_CONFIG_INDEX 0x04 +#define USB_STRING_INTERFACE_INDEX 0x05 +#define USB_STRING_OS_INDEX 0x06 +#define USB_STRING_MAX USB_STRING_OS_INDEX +/* + * Devices supporting Microsoft OS Descriptors store special string + * descriptor at fixed index (0xEE). It is read when a new device is + * attached to a computer for the first time. + */ +#define USB_OSDESC_STRING_DESC_INDEX 0xEE + +/* bmAttributes in Configuration Descriptor */ +#define USB_CONFIG_REMOTE_WAKEUP 0x20 +#define USB_CONFIG_POWERED_MASK 0x40 +#define USB_CONFIG_BUS_POWERED 0x80 +#define USB_CONFIG_SELF_POWERED 0xC0 + +/* bMaxPower in Configuration Descriptor */ +#define USB_CONFIG_POWER_MA(mA) ((mA) / 2) + +/* bEndpointAddress in Endpoint Descriptor */ +#define USB_ENDPOINT_DIRECTION_MASK 0x80 +#define USB_ENDPOINT_OUT(addr) ((addr) | 0x00) +#define USB_ENDPOINT_IN(addr) ((addr) | 0x80) + +/** + * USB endpoint direction and number. + */ +#define USB_EP_DIR_MASK 0x80U +#define USB_EP_DIR_IN 0x80U +#define USB_EP_DIR_OUT 0x00U + +/** Get endpoint index (number) from endpoint address */ +#define USB_EP_GET_IDX(ep) ((ep) & ~USB_EP_DIR_MASK) +/** Get direction from endpoint address */ +#define USB_EP_GET_DIR(ep) ((ep)&USB_EP_DIR_MASK) +/** Get endpoint address from endpoint index and direction */ +#define USB_EP_GET_ADDR(idx, dir) ((idx) | ((dir)&USB_EP_DIR_MASK)) +/** True if the endpoint is an IN endpoint */ +#define USB_EP_DIR_IS_IN(ep) (USB_EP_GET_DIR(ep) == USB_EP_DIR_IN) +/** True if the endpoint is an OUT endpoint */ +#define USB_EP_DIR_IS_OUT(ep) (USB_EP_GET_DIR(ep) == USB_EP_DIR_OUT) + +/* bmAttributes in Endpoint Descriptor */ +#define USB_ENDPOINT_TYPE_SHIFT 0 +#define USB_ENDPOINT_TYPE_CONTROL (0 << USB_ENDPOINT_TYPE_SHIFT) +#define USB_ENDPOINT_TYPE_ISOCHRONOUS (1 << USB_ENDPOINT_TYPE_SHIFT) +#define USB_ENDPOINT_TYPE_BULK (2 << USB_ENDPOINT_TYPE_SHIFT) +#define USB_ENDPOINT_TYPE_INTERRUPT (3 << USB_ENDPOINT_TYPE_SHIFT) +#define USB_ENDPOINT_TYPE_MASK (3 << USB_ENDPOINT_TYPE_SHIFT) +#define USB_GET_ENDPOINT_TYPE(x) ((x & USB_ENDPOINT_TYPE_MASK) >> USB_ENDPOINT_TYPE_SHIFT) + +#define USB_ENDPOINT_SYNC_SHIFT 2 +#define USB_ENDPOINT_SYNC_NO_SYNCHRONIZATION (0 << USB_ENDPOINT_SYNC_SHIFT) +#define USB_ENDPOINT_SYNC_ASYNCHRONOUS (1 << USB_ENDPOINT_SYNC_SHIFT) +#define USB_ENDPOINT_SYNC_ADAPTIVE (2 << USB_ENDPOINT_SYNC_SHIFT) +#define USB_ENDPOINT_SYNC_SYNCHRONOUS (3 << USB_ENDPOINT_SYNC_SHIFT) +#define USB_ENDPOINT_SYNC_MASK (3 << USB_ENDPOINT_SYNC_SHIFT) + +#define USB_ENDPOINT_USAGE_SHIFT 4 +#define USB_ENDPOINT_USAGE_DATA (0 << USB_ENDPOINT_USAGE_SHIFT) +#define USB_ENDPOINT_USAGE_FEEDBACK (1 << USB_ENDPOINT_USAGE_SHIFT) +#define USB_ENDPOINT_USAGE_IMPLICIT_FEEDBACK (2 << USB_ENDPOINT_USAGE_SHIFT) +#define USB_ENDPOINT_USAGE_MASK (3 << USB_ENDPOINT_USAGE_SHIFT) + +#define USB_ENDPOINT_MAX_ADJUSTABLE (1 << 7) + +/* wMaxPacketSize in Endpoint Descriptor */ +#define USB_MAXPACKETSIZE_SHIFT 0 +#define USB_MAXPACKETSIZE_MASK (0x7ff << USB_MAXPACKETSIZE_SHIFT) +#define USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT 11 +#define USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_NONE (0 << USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT) +#define USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_ONE (1 << USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT) +#define USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_TWO (2 << USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT) +#define USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_MASK (3 << USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT) +#define USB_GET_MAXPACKETSIZE(x) ((x & USB_MAXPACKETSIZE_MASK) >> USB_MAXPACKETSIZE_SHIFT) +#define USB_GET_MULT(x) ((x & USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_MASK) >> USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT) + +/* bDevCapabilityType in Device Capability Descriptor */ +#define USB_DEVICE_CAPABILITY_WIRELESS_USB 1 +#define USB_DEVICE_CAPABILITY_USB_2_0_EXTENSION 2 +#define USB_DEVICE_CAPABILITY_SUPERSPEED_USB 3 +#define USB_DEVICE_CAPABILITY_CONTAINER_ID 4 +#define USB_DEVICE_CAPABILITY_PLATFORM 5 +#define USB_DEVICE_CAPABILITY_POWER_DELIVERY_CAPABILITY 6 +#define USB_DEVICE_CAPABILITY_BATTERY_INFO_CAPABILITY 7 +#define USB_DEVICE_CAPABILITY_PD_CONSUMER_PORT_CAPABILITY 8 +#define USB_DEVICE_CAPABILITY_PD_PROVIDER_PORT_CAPABILITY 9 +#define USB_DEVICE_CAPABILITY_SUPERSPEED_PLUS 10 +#define USB_DEVICE_CAPABILITY_PRECISION_TIME_MEASUREMENT 11 +#define USB_DEVICE_CAPABILITY_WIRELESS_USB_EXT 12 + +#define USB_BOS_CAPABILITY_EXTENSION 0x02 +#define USB_BOS_CAPABILITY_PLATFORM 0x05 + +/* OTG SET FEATURE Constants */ +#define USB_OTG_FEATURE_B_HNP_ENABLE 3 /* Enable B device to perform HNP */ +#define USB_OTG_FEATURE_A_HNP_SUPPORT 4 /* A device supports HNP */ +#define USB_OTG_FEATURE_A_ALT_HNP_SUPPORT 5 /* Another port on the A device supports HNP */ + +/* WinUSB Microsoft OS 2.0 descriptor request codes */ +#define WINUSB_REQUEST_GET_DESCRIPTOR_SET 0x07 +#define WINUSB_REQUEST_SET_ALT_ENUM 0x08 + +/* WinUSB Microsoft OS 2.0 descriptor sizes */ +#define WINUSB_DESCRIPTOR_SET_HEADER_SIZE 10 +#define WINUSB_FUNCTION_SUBSET_HEADER_SIZE 8 +#define WINUSB_FEATURE_COMPATIBLE_ID_SIZE 20 + +/* WinUSB Microsoft OS 2.0 Descriptor Types */ +#define WINUSB_SET_HEADER_DESCRIPTOR_TYPE 0x00 +#define WINUSB_SUBSET_HEADER_CONFIGURATION_TYPE 0x01 +#define WINUSB_SUBSET_HEADER_FUNCTION_TYPE 0x02 +#define WINUSB_FEATURE_COMPATIBLE_ID_TYPE 0x03 +#define WINUSB_FEATURE_REG_PROPERTY_TYPE 0x04 +#define WINUSB_FEATURE_MIN_RESUME_TIME_TYPE 0x05 +#define WINUSB_FEATURE_MODEL_ID_TYPE 0x06 +#define WINUSB_FEATURE_CCGP_DEVICE_TYPE 0x07 + +#define WINUSB_PROP_DATA_TYPE_REG_SZ 0x01 +#define WINUSB_PROP_DATA_TYPE_REG_MULTI_SZ 0x07 + +/* WebUSB Descriptor Types */ +#define WEBUSB_DESCRIPTOR_SET_HEADER_TYPE 0x00 +#define WEBUSB_CONFIGURATION_SUBSET_HEADER_TYPE 0x01 +#define WEBUSB_FUNCTION_SUBSET_HEADER_TYPE 0x02 +#define WEBUSB_URL_TYPE 0x03 + +/* WebUSB Request Codes */ +#define WEBUSB_REQUEST_GET_URL 0x02 + +/* bScheme in URL descriptor */ +#define WEBUSB_URL_SCHEME_HTTP 0x00 +#define WEBUSB_URL_SCHEME_HTTPS 0x01 + +/* WebUSB Descriptor sizes */ +#define WEBUSB_DESCRIPTOR_SET_HEADER_SIZE 5 +#define WEBUSB_CONFIGURATION_SUBSET_HEADER_SIZE 4 +#define WEBUSB_FUNCTION_SUBSET_HEADER_SIZE 3 + +/* Setup packet definition used to read raw data from USB line */ +struct usb_setup_packet { + /** Request type. Bits 0:4 determine recipient, see + * \ref usb_request_recipient. Bits 5:6 determine type, see + * \ref usb_request_type. Bit 7 determines data transfer direction, see + * \ref usb_endpoint_direction. + */ + uint8_t bmRequestType; + + /** Request. If the type bits of bmRequestType are equal to + * \ref usb_request_type::LIBUSB_REQUEST_TYPE_STANDARD + * "USB_REQUEST_TYPE_STANDARD" then this field refers to + * \ref usb_standard_request. For other cases, use of this field is + * application-specific. */ + uint8_t bRequest; + + /** Value. Varies according to request */ + uint16_t wValue; + + /** Index. Varies according to request, typically used to pass an index + * or offset */ + uint16_t wIndex; + + /** Number of bytes to transfer */ + uint16_t wLength; +} __PACKED; + +#define USB_SIZEOF_SETUP_PACKET 8 + +/** Standard Device Descriptor */ +struct usb_device_descriptor { + uint8_t bLength; /* Descriptor size in bytes = 18 */ + uint8_t bDescriptorType; /* DEVICE descriptor type = 1 */ + uint16_t bcdUSB; /* USB spec in BCD, e.g. 0x0200 */ + uint8_t bDeviceClass; /* Class code, if 0 see interface */ + uint8_t bDeviceSubClass; /* Sub-Class code, 0 if class = 0 */ + uint8_t bDeviceProtocol; /* Protocol, if 0 see interface */ + uint8_t bMaxPacketSize0; /* Endpoint 0 max. size */ + uint16_t idVendor; /* Vendor ID per USB-IF */ + uint16_t idProduct; /* Product ID per manufacturer */ + uint16_t bcdDevice; /* Device release # in BCD */ + uint8_t iManufacturer; /* Index to manufacturer string */ + uint8_t iProduct; /* Index to product string */ + uint8_t iSerialNumber; /* Index to serial number string */ + uint8_t bNumConfigurations; /* Number of possible configurations */ +} __PACKED; + +#define USB_SIZEOF_DEVICE_DESC 18 + +/** Standard Configuration Descriptor */ +struct usb_configuration_descriptor { + uint8_t bLength; /* Descriptor size in bytes = 9 */ + uint8_t bDescriptorType; /* CONFIGURATION type = 2 or 7 */ + uint16_t wTotalLength; /* Length of concatenated descriptors */ + uint8_t bNumInterfaces; /* Number of interfaces, this config. */ + uint8_t bConfigurationValue; /* Value to set this config. */ + uint8_t iConfiguration; /* Index to configuration string */ + uint8_t bmAttributes; /* Config. characteristics */ + uint8_t bMaxPower; /* Max.power from bus, 2mA units */ +} __PACKED; + +#define USB_SIZEOF_CONFIG_DESC 9 + +/** Standard Interface Descriptor */ +struct usb_interface_descriptor { + uint8_t bLength; /* Descriptor size in bytes = 9 */ + uint8_t bDescriptorType; /* INTERFACE descriptor type = 4 */ + uint8_t bInterfaceNumber; /* Interface no.*/ + uint8_t bAlternateSetting; /* Value to select this IF */ + uint8_t bNumEndpoints; /* Number of endpoints excluding 0 */ + uint8_t bInterfaceClass; /* Class code, 0xFF = vendor */ + uint8_t bInterfaceSubClass; /* Sub-Class code, 0 if class = 0 */ + uint8_t bInterfaceProtocol; /* Protocol, 0xFF = vendor */ + uint8_t iInterface; /* Index to interface string */ +} __PACKED; + +#define USB_SIZEOF_INTERFACE_DESC 9 + +/** Standard Endpoint Descriptor */ +struct usb_endpoint_descriptor { + uint8_t bLength; /* Descriptor size in bytes = 7 */ + uint8_t bDescriptorType; /* ENDPOINT descriptor type = 5 */ + uint8_t bEndpointAddress; /* Endpoint # 0 - 15 | IN/OUT */ + uint8_t bmAttributes; /* Transfer type */ + uint16_t wMaxPacketSize; /* Bits 10:0 = max. packet size */ + uint8_t bInterval; /* Polling interval in (micro) frames */ +} __PACKED; + +#define USB_SIZEOF_ENDPOINT_DESC 7 + +/** Unicode (UTF16LE) String Descriptor */ +struct usb_string_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bString; +} __PACKED; + +#define USB_SIZEOF_STRING_LANGID_DESC 4 + +/* USB Interface Association Descriptor */ +struct usb_interface_association_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bFirstInterface; + uint8_t bInterfaceCount; + uint8_t bFunctionClass; + uint8_t bFunctionSubClass; + uint8_t bFunctionProtocol; + uint8_t iFunction; +} __PACKED; + +#define USB_SIZEOF_IAD_DESC 8 + +/** USB device_qualifier descriptor */ +struct usb_device_qualifier_descriptor { + uint8_t bLength; /* Descriptor size in bytes = 10 */ + uint8_t bDescriptorType; /* DEVICE QUALIFIER type = 6 */ + uint16_t bcdUSB; /* USB spec in BCD, e.g. 0x0200 */ + uint8_t bDeviceClass; /* Class code, if 0 see interface */ + uint8_t bDeviceSubClass; /* Sub-Class code, 0 if class = 0 */ + uint8_t bDeviceProtocol; /* Protocol, if 0 see interface */ + uint8_t bMaxPacketSize; /* Endpoint 0 max. size */ + uint8_t bNumConfigurations; /* Number of possible configurations */ + uint8_t bReserved; /* Reserved = 0 */ +} __PACKED; + +#define USB_SIZEOF_DEVICE_QUALIFIER_DESC 10 + +/* Microsoft OS function descriptor. + * This can be used to request a specific driver (such as WINUSB) to be + * loaded on Windows. Unlike other descriptors, it is requested by a special + * request USB_REQ_GETMSFTOSDESCRIPTOR. + * More details: + * https://msdn.microsoft.com/en-us/windows/hardware/gg463179 + * And excellent explanation: + * https://github.com/pbatard/libwdi/wiki/WCID-Devices + * + * The device will have exactly one "Extended Compat ID Feature Descriptor", + * which may contain multiple "Function Descriptors" associated with + * different interfaces. + */ + +/* MS OS 1.0 string descriptor */ +struct usb_msosv1_string_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bString[14]; + uint8_t bMS_VendorCode; /* Vendor Code, used for a control request */ + uint8_t bPad; /* Padding byte for VendorCode look as UTF16 */ +} __PACKED; + +/* MS OS 1.0 Header descriptor */ +struct usb_msosv1_compat_id_header_descriptor { + uint32_t dwLength; + uint16_t bcdVersion; + uint16_t wIndex; + uint8_t bCount; + uint8_t reserved[7]; +} __PACKED; + +/* MS OS 1.0 Function descriptor */ +struct usb_msosv1_comp_id_function_descriptor { + uint8_t bFirstInterfaceNumber; + uint8_t reserved1; + uint8_t compatibleID[8]; + uint8_t subCompatibleID[8]; + uint8_t reserved2[6]; +} __PACKED; + +#define usb_msosv1_comp_id_create(x) \ + struct usb_msosv1_comp_id { \ + struct usb_msosv1_compat_id_header_descriptor compat_id_header; \ + struct usb_msosv1_comp_id_function_descriptor compat_id_function[x]; \ + }; + +struct usb_msosv1_descriptor { + const uint8_t *string; + uint8_t vendor_code; + const uint8_t *compat_id; + const uint8_t **comp_id_property; +}; + +/* MS OS 2.0 Header descriptor */ +struct usb_msosv2_header_descriptor { + uint32_t dwLength; + uint16_t bcdVersion; + uint16_t wIndex; + uint8_t bCount; +} __PACKED; + +/*Microsoft OS 2.0 set header descriptor*/ +struct usb_msosv2_set_header_descriptor { + uint16_t wLength; + uint16_t wDescriptorType; + uint32_t dwWindowsVersion; + uint16_t wDescriptorSetTotalLength; +} __PACKED; + +/* Microsoft OS 2.0 compatibleID descriptor*/ +struct usb_msosv2_comp_id_descriptor { + uint16_t wLength; + uint16_t wDescriptorType; + uint8_t compatibleID[8]; + uint8_t subCompatibleID[8]; +} __PACKED; + +/* MS OS 2.0 property descriptor */ +struct usb_msosv2_property_descriptor { + uint16_t wLength; + uint16_t wDescriptorType; + uint32_t dwPropertyDataType; + uint16_t wPropertyNameLength; + const char *bPropertyName; + uint32_t dwPropertyDataLength; + const char *bPropertyData; +}; + +/* Microsoft OS 2.0 subset function descriptor */ +struct usb_msosv2_subset_function_descriptor { + uint16_t wLength; + uint16_t wDescriptorType; + uint8_t bFirstInterface; + uint8_t bReserved; + uint16_t wSubsetLength; +} __PACKED; + +struct usb_msosv2_descriptor { + uint8_t *compat_id; + uint16_t compat_id_len; + uint8_t vendor_code; +}; + +/* BOS header Descriptor */ +struct usb_bos_header_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wTotalLength; + uint8_t bNumDeviceCaps; +} __PACKED; + +/* BOS Capability platform Descriptor */ +struct usb_bos_capability_platform_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDevCapabilityType; + uint8_t bReserved; + uint8_t PlatformCapabilityUUID[16]; +} __PACKED; + +/* BOS Capability MS OS Descriptors version 2 */ +struct usb_bos_capability_msosv2_descriptor { + uint32_t dwWindowsVersion; + uint16_t wMSOSDescriptorSetTotalLength; + uint8_t bVendorCode; + uint8_t bAltEnumCode; +} __PACKED; + +/* BOS Capability webusb */ +struct usb_bos_capability_webusb_descriptor { + uint16_t bcdVersion; + uint8_t bVendorCode; + uint8_t iLandingPage; +} __PACKED; + +/* BOS Capability extension Descriptor*/ +struct usb_bos_capability_extension_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDevCapabilityType; + uint32_t bmAttributes; +} __PACKED; + +/* Microsoft OS 2.0 Platform Capability Descriptor +* See https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/ +* microsoft-defined-usb-descriptors +* Adapted from the source: +* https://github.com/sowbug/weblight/blob/master/firmware/webusb.c +* (BSD-2) Thanks http://janaxelson.com/files/ms_os_20_descriptors.c +*/ +struct usb_bos_capability_platform_msosv2_descriptor { + struct usb_bos_capability_platform_descriptor platform_msos; + struct usb_bos_capability_msosv2_descriptor data_msosv2; +} __PACKED; + +/* WebUSB Platform Capability Descriptor: +* https://wicg.github.io/webusb/#webusb-platform-capability-descriptor +*/ +struct usb_bos_capability_platform_webusb_descriptor { + struct usb_bos_capability_platform_descriptor platform_webusb; + struct usb_bos_capability_webusb_descriptor data_webusb; +} __PACKED; + +struct usb_webusb_url_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bScheme; + char URL[]; +} __PACKED; + +struct usb_webusb_url_ex_descriptor { + uint8_t vendor_code; + uint8_t *string; + uint32_t string_len; +} __PACKED; + +struct usb_bos_descriptor { + uint8_t *string; + uint32_t string_len; +}; + +/* USB Device Capability Descriptor */ +struct usb_device_capability_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDevCapabilityType; +} __PACKED; + +/** USB descriptor header */ +struct usb_desc_header { + uint8_t bLength; /**< descriptor length */ + uint8_t bDescriptorType; /**< descriptor type */ +}; +// clang-format off +#define USB_DEVICE_DESCRIPTOR_INIT(bcdUSB, bDeviceClass, bDeviceSubClass, bDeviceProtocol, idVendor, idProduct, bcdDevice, bNumConfigurations) \ + 0x12, /* bLength */ \ + USB_DESCRIPTOR_TYPE_DEVICE, /* bDescriptorType */ \ + WBVAL(bcdUSB), /* bcdUSB */ \ + bDeviceClass, /* bDeviceClass */ \ + bDeviceSubClass, /* bDeviceSubClass */ \ + bDeviceProtocol, /* bDeviceProtocol */ \ + 0x40, /* bMaxPacketSize */ \ + WBVAL(idVendor), /* idVendor */ \ + WBVAL(idProduct), /* idProduct */ \ + WBVAL(bcdDevice), /* bcdDevice */ \ + USB_STRING_MFC_INDEX, /* iManufacturer */ \ + USB_STRING_PRODUCT_INDEX, /* iProduct */ \ + USB_STRING_SERIAL_INDEX, /* iSerial */ \ + bNumConfigurations /* bNumConfigurations */ + +#define USB_CONFIG_DESCRIPTOR_INIT(wTotalLength, bNumInterfaces, bConfigurationValue, bmAttributes, bMaxPower) \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_CONFIGURATION, /* bDescriptorType */ \ + WBVAL(wTotalLength), /* wTotalLength */ \ + bNumInterfaces, /* bNumInterfaces */ \ + bConfigurationValue, /* bConfigurationValue */ \ + 0x00, /* iConfiguration */ \ + bmAttributes, /* bmAttributes */ \ + USB_CONFIG_POWER_MA(bMaxPower) /* bMaxPower */ + +#define USB_INTERFACE_DESCRIPTOR_INIT(bInterfaceNumber, bAlternateSetting, bNumEndpoints, \ + bInterfaceClass, bInterfaceSubClass, bInterfaceProtocol, iInterface) \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bInterfaceNumber, /* bInterfaceNumber */ \ + bAlternateSetting, /* bAlternateSetting */ \ + bNumEndpoints, /* bNumEndpoints */ \ + bInterfaceClass, /* bInterfaceClass */ \ + bInterfaceSubClass, /* bInterfaceSubClass */ \ + bInterfaceProtocol, /* bInterfaceProtocol */ \ + iInterface /* iInterface */ + +#define USB_ENDPOINT_DESCRIPTOR_INIT(bEndpointAddress, bmAttributes, wMaxPacketSize, bInterval) \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + bEndpointAddress, /* bEndpointAddress */ \ + bmAttributes, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + bInterval /* bInterval */ + +#define USB_IAD_INIT(bFirstInterface, bInterfaceCount, bFunctionClass, bFunctionSubClass, bFunctionProtocol) \ + 0x08, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, /* bDescriptorType */ \ + bFirstInterface, /* bFirstInterface */ \ + bInterfaceCount, /* bInterfaceCount */ \ + bFunctionClass, /* bFunctionClass */ \ + bFunctionSubClass, /* bFunctionSubClass */ \ + bFunctionProtocol, /* bFunctionProtocol */ \ + 0x00 /* iFunction */ + +#define USB_LANGID_INIT(id) \ + 0x04, /* bLength */ \ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ \ + WBVAL(id) /* wLangID0 */ +// clang-format on + +#endif /* USB_DEF_H */ diff --git a/Code/DAP_X033/DAP/CherryUSB/common/usb_errno.h b/Code/DAP_X033/DAP/CherryUSB/common/usb_errno.h new file mode 100644 index 0000000..57f37c1 --- /dev/null +++ b/Code/DAP_X033/DAP/CherryUSB/common/usb_errno.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2023, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_ERRNO_H +#define USB_ERRNO_H + +#define USB_ERR_NOMEM 1 +#define USB_ERR_INVAL 2 +#define USB_ERR_NODEV 3 +#define USB_ERR_NOTCONN 4 +#define USB_ERR_NOTSUPP 5 +#define USB_ERR_BUSY 6 +#define USB_ERR_RANGE 7 +#define USB_ERR_STALL 8 +#define USB_ERR_BABBLE 9 +#define USB_ERR_NAK 10 +#define USB_ERR_DT 11 +#define USB_ERR_IO 12 +#define USB_ERR_SHUTDOWN 13 +#define USB_ERR_TIMEOUT 14 + +#endif /* USB_ERRNO_H */ diff --git a/Code/DAP_X033/DAP/CherryUSB/common/usb_hc.h b/Code/DAP_X033/DAP/CherryUSB/common/usb_hc.h new file mode 100644 index 0000000..adfddbe --- /dev/null +++ b/Code/DAP_X033/DAP/CherryUSB/common/usb_hc.h @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_HC_H +#define USB_HC_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef void (*usbh_complete_callback_t)(void *arg, int nbytes); + +struct usbh_bus; + +/** + * @brief USB Iso Configuration. + * + * Structure containing the USB Iso configuration. + */ +struct usbh_iso_frame_packet { + uint8_t *transfer_buffer; + uint32_t transfer_buffer_length; + uint32_t actual_length; + int errorcode; +}; + +/** + * @brief USB Urb Configuration. + * + * Structure containing the USB Urb configuration. + */ +struct usbh_urb { + void *hcpriv; + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *ep; + uint8_t data_toggle; + uint8_t interval; + struct usb_setup_packet *setup; + uint8_t *transfer_buffer; + uint32_t transfer_buffer_length; + int transfer_flags; + uint32_t actual_length; + uint32_t timeout; + int errorcode; + uint32_t num_of_iso_packets; + uint32_t start_frame; + usbh_complete_callback_t complete; + void *arg; +#if defined(__ICCARM__) || defined(__ICCRISCV__) || defined(__ICCRX__) + struct usbh_iso_frame_packet *iso_packet; +#else + struct usbh_iso_frame_packet iso_packet[0]; +#endif +}; + +/** + * @brief usb host controller hardware init. + * + * @return On success will return 0, and others indicate fail. + */ +int usb_hc_init(struct usbh_bus *bus); + +/** + * @brief usb host controller hardware deinit. + * + * @return On success will return 0, and others indicate fail. + */ +int usb_hc_deinit(struct usbh_bus *bus); + +/** + * @brief Get frame number. + * + * @return frame number. + */ +uint16_t usbh_get_frame_number(struct usbh_bus *bus); +/** + * @brief control roothub. + * + * @param setup setup request buffer. + * @param buf buf for reading response or write data. + * @return On success will return 0, and others indicate fail. + */ +int usbh_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, uint8_t *buf); + +/** + * @brief Submit a usb transfer request to an endpoint. + * + * If timeout is not zero, this function will be in poll transfer mode, + * otherwise will be in async transfer mode. + * + * @param urb Usb request block. + * @return On success will return 0, and others indicate fail. + */ +int usbh_submit_urb(struct usbh_urb *urb); + +/** + * @brief Cancel a transfer request. + * + * This function will call When calls usbh_submit_urb and return -USB_ERR_TIMEOUT or -USB_ERR_SHUTDOWN. + * + * @param urb Usb request block. + * @return On success will return 0, and others indicate fail. + */ +int usbh_kill_urb(struct usbh_urb *urb); + +#ifdef __cplusplus +} +#endif + +#endif /* USB_HC_H */ diff --git a/Code/DAP_X033/DAP/CherryUSB/common/usb_list.h b/Code/DAP_X033/DAP/CherryUSB/common/usb_list.h new file mode 100644 index 0000000..3078a1f --- /dev/null +++ b/Code/DAP_X033/DAP/CherryUSB/common/usb_list.h @@ -0,0 +1,459 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_LIST_H +#define USB_LIST_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * usb_container_of - return the member address of ptr, if the type of ptr is the + * struct type. + */ +#define usb_container_of(ptr, type, member) \ + ((type *)((char *)(ptr) - (unsigned long)(&((type *)0)->member))) + +/** + * Single List structure + */ +struct usb_slist_node { + struct usb_slist_node *next; /**< point to next node. */ +}; +typedef struct usb_slist_node usb_slist_t; /**< Type for single list. */ + +/** + * @brief initialize a single list + * + * @param l the single list to be initialized + */ +static inline void usb_slist_init(usb_slist_t *l) +{ + l->next = NULL; +} + +static inline void usb_slist_add_head(usb_slist_t *l, usb_slist_t *n) +{ + n->next = l->next; + l->next = n; +} + +static inline void usb_slist_add_tail(usb_slist_t *l, usb_slist_t *n) +{ + usb_slist_t *tmp = l; + + while (tmp->next) { + tmp = tmp->next; + } + + /* append the node to the tail */ + tmp->next = n; + n->next = NULL; +} + +static inline void usb_slist_insert(usb_slist_t *l, usb_slist_t *next, usb_slist_t *n) +{ + if (!next) { + usb_slist_add_tail(next, l); + return; + } + + while (l->next) { + if (l->next == next) { + l->next = n; + n->next = next; + } + + l = l->next; + } +} + +static inline usb_slist_t *usb_slist_remove(usb_slist_t *l, usb_slist_t *n) +{ + usb_slist_t *tmp = l; + /* remove slist head */ + while (tmp->next && tmp->next != n) { + tmp = tmp->next; + } + + /* remove node */ + if (tmp->next != (usb_slist_t *)0) { + tmp->next = tmp->next->next; + } + + return l; +} + +static inline unsigned int usb_slist_len(const usb_slist_t *l) +{ + unsigned int len = 0; + const usb_slist_t *list = l->next; + + while (list != NULL) { + list = list->next; + len++; + } + + return len; +} + +static inline unsigned int usb_slist_contains(usb_slist_t *l, usb_slist_t *n) +{ + while (l->next) { + if (l->next == n) { + return 0; + } + + l = l->next; + } + + return 1; +} + +static inline usb_slist_t *usb_slist_head(usb_slist_t *l) +{ + return l->next; +} + +static inline usb_slist_t *usb_slist_tail(usb_slist_t *l) +{ + while (l->next) { + l = l->next; + } + + return l; +} + +static inline usb_slist_t *usb_slist_next(usb_slist_t *n) +{ + return n->next; +} + +static inline int usb_slist_isempty(usb_slist_t *l) +{ + return l->next == NULL; +} + +/** + * @brief initialize a slist object + */ +#define USB_SLIST_OBJECT_INIT(object) \ + { \ + NULL \ + } + +/** + * @brief initialize a slist object + */ +#define USB_SLIST_DEFINE(slist) \ + usb_slist_t slist = { NULL } + +/** + * @brief get the struct for this single list node + * @param node the entry point + * @param type the type of structure + * @param member the name of list in structure + */ +#define usb_slist_entry(node, type, member) \ + usb_container_of(node, type, member) + +/** + * usb_slist_first_entry - get the first element from a slist + * @ptr: the slist head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the slist_struct within the struct. + * + * Note, that slist is expected to be not empty. + */ +#define usb_slist_first_entry(ptr, type, member) \ + usb_slist_entry((ptr)->next, type, member) + +/** + * usb_slist_tail_entry - get the tail element from a slist + * @ptr: the slist head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the slist_struct within the struct. + * + * Note, that slist is expected to be not empty. + */ +#define usb_slist_tail_entry(ptr, type, member) \ + usb_slist_entry(usb_slist_tail(ptr), type, member) + +/** + * usb_slist_first_entry_or_null - get the first element from a slist + * @ptr: the slist head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the slist_struct within the struct. + * + * Note, that slist is expected to be not empty. + */ +#define usb_slist_first_entry_or_null(ptr, type, member) \ + (usb_slist_isempty(ptr) ? NULL : usb_slist_first_entry(ptr, type, member)) + +/** + * usb_slist_for_each - iterate over a single list + * @pos: the usb_slist_t * to use as a loop cursor. + * @head: the head for your single list. + */ +#define usb_slist_for_each(pos, head) \ + for (pos = (head)->next; pos != NULL; pos = pos->next) + +#define usb_slist_for_each_safe(pos, next, head) \ + for (pos = (head)->next, next = pos->next; pos; \ + pos = next, next = pos->next) + +/** + * usb_slist_for_each_entry - iterate over single list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your single list. + * @member: the name of the list_struct within the struct. + */ +#define usb_slist_for_each_entry(pos, head, member) \ + for (pos = usb_slist_entry((head)->next, typeof(*pos), member); \ + &pos->member != (NULL); \ + pos = usb_slist_entry(pos->member.next, typeof(*pos), member)) + +#define usb_slist_for_each_entry_safe(pos, n, head, member) \ + for (pos = usb_slist_entry((head)->next, typeof(*pos), member), \ + n = usb_slist_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (NULL); \ + pos = n, n = usb_slist_entry(pos->member.next, typeof(*pos), member)) + +/** + * Double List structure + */ +struct usb_dlist_node { + struct usb_dlist_node *next; /**< point to next node. */ + struct usb_dlist_node *prev; /**< point to prev node. */ +}; +typedef struct usb_dlist_node usb_dlist_t; /**< Type for lists. */ + +/** + * @brief initialize a list + * + * @param l list to be initialized + */ +static inline void usb_dlist_init(usb_dlist_t *l) +{ + l->next = l->prev = l; +} + +/** + * @brief insert a node after a list + * + * @param l list to insert it + * @param n new node to be inserted + */ +static inline void usb_dlist_insert_after(usb_dlist_t *l, usb_dlist_t *n) +{ + l->next->prev = n; + n->next = l->next; + + l->next = n; + n->prev = l; +} + +/** + * @brief insert a node before a list + * + * @param n new node to be inserted + * @param l list to insert it + */ +static inline void usb_dlist_insert_before(usb_dlist_t *l, usb_dlist_t *n) +{ + l->prev->next = n; + n->prev = l->prev; + + l->prev = n; + n->next = l; +} + +/** + * @brief remove node from list. + * @param n the node to remove from the list. + */ +static inline void usb_dlist_remove(usb_dlist_t *n) +{ + n->next->prev = n->prev; + n->prev->next = n->next; + + n->next = n->prev = n; +} + +/** + * @brief move node from list. + * @param n the node to remove from the list. + */ +static inline void usb_dlist_move_head(usb_dlist_t *l, usb_dlist_t *n) +{ + usb_dlist_remove(n); + usb_dlist_insert_after(l, n); +} + +/** + * @brief move node from list. + * @param n the node to remove from the list. + */ +static inline void usb_dlist_move_tail(usb_dlist_t *l, usb_dlist_t *n) +{ + usb_dlist_remove(n); + usb_dlist_insert_before(l, n); +} + +/** + * @brief tests whether a list is empty + * @param l the list to test. + */ +static inline int usb_dlist_isempty(const usb_dlist_t *l) +{ + return l->next == l; +} + +/** + * @brief get the list length + * @param l the list to get. + */ +static inline unsigned int usb_dlist_len(const usb_dlist_t *l) +{ + unsigned int len = 0; + const usb_dlist_t *p = l; + + while (p->next != l) { + p = p->next; + len++; + } + + return len; +} + +/** + * @brief initialize a dlist object + */ +#define USB_DLIST_OBJECT_INIT(object) \ + { \ + &(object), &(object) \ + } +/** + * @brief initialize a dlist object + */ +#define USB_DLIST_DEFINE(list) \ + usb_dlist_t list = { &(list), &(list) } + +/** + * @brief get the struct for this entry + * @param node the entry point + * @param type the type of structure + * @param member the name of list in structure + */ +#define usb_dlist_entry(node, type, member) \ + usb_container_of(node, type, member) + +/** + * dlist_first_entry - get the first element from a list + * @ptr: the list head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + * + * Note, that list is expected to be not empty. + */ +#define usb_dlist_first_entry(ptr, type, member) \ + usb_dlist_entry((ptr)->next, type, member) +/** + * dlist_first_entry_or_null - get the first element from a list + * @ptr: the list head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + * + * Note, that list is expected to be not empty. + */ +#define usb_dlist_first_entry_or_null(ptr, type, member) \ + (usb_dlist_isempty(ptr) ? NULL : usb_dlist_first_entry(ptr, type, member)) + +/** + * usb_dlist_for_each - iterate over a list + * @pos: the usb_dlist_t * to use as a loop cursor. + * @head: the head for your list. + */ +#define usb_dlist_for_each(pos, head) \ + for (pos = (head)->next; pos != (head); pos = pos->next) + +/** + * usb_dlist_for_each_prev - iterate over a list + * @pos: the dlist_t * to use as a loop cursor. + * @head: the head for your list. + */ +#define usb_dlist_for_each_prev(pos, head) \ + for (pos = (head)->prev; pos != (head); pos = pos->prev) + +/** + * usb_dlist_for_each_safe - iterate over a list safe against removal of list entry + * @pos: the dlist_t * to use as a loop cursor. + * @n: another dlist_t * to use as temporary storage + * @head: the head for your list. + */ +#define usb_dlist_for_each_safe(pos, n, head) \ + for (pos = (head)->next, n = pos->next; pos != (head); \ + pos = n, n = pos->next) + +#define usb_dlist_for_each_prev_safe(pos, n, head) \ + for (pos = (head)->prev, n = pos->prev; pos != (head); \ + pos = n, n = pos->prev) +/** + * usb_dlist_for_each_entry - iterate over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define usb_dlist_for_each_entry(pos, head, member) \ + for (pos = usb_dlist_entry((head)->next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = usb_dlist_entry(pos->member.next, typeof(*pos), member)) + +/** + * usb_usb_dlist_for_each_entry_reverse - iterate over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define usb_dlist_for_each_entry_reverse(pos, head, member) \ + for (pos = usb_dlist_entry((head)->prev, typeof(*pos), member); \ + &pos->member != (head); \ + pos = usb_dlist_entry(pos->member.prev, typeof(*pos), member)) + +/** + * usb_usb_dlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define usb_dlist_for_each_entry_safe(pos, n, head, member) \ + for (pos = usb_dlist_entry((head)->next, typeof(*pos), member), \ + n = usb_dlist_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = usb_dlist_entry(n->member.next, typeof(*n), member)) + +/** + * usb_usb_dlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define usb_dlist_for_each_entry_safe_reverse(pos, n, head, member) \ + for (pos = usb_dlist_entry((head)->prev, typeof(*pos), field), \ + n = usb_dlist_entry(pos->member.prev, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = usb_dlist_entry(pos->member.prev, typeof(*pos), member)) + +#ifdef __cplusplus +} +#endif + +#endif /* USB_LIST_H */ diff --git a/Code/DAP_X033/DAP/CherryUSB/common/usb_log.h b/Code/DAP_X033/DAP/CherryUSB/common/usb_log.h new file mode 100644 index 0000000..923e800 --- /dev/null +++ b/Code/DAP_X033/DAP/CherryUSB/common/usb_log.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_LOG_H +#define USB_LOG_H + +#include + +/* DEBUG level */ +#define USB_DBG_ERROR 0 +#define USB_DBG_WARNING 1 +#define USB_DBG_INFO 2 +#define USB_DBG_LOG 3 + +#ifndef USB_DBG_TAG +#define USB_DBG_TAG "USB" +#endif +/* + * The color for terminal (foreground) + * BLACK 30 + * RED 31 + * GREEN 32 + * YELLOW 33 + * BLUE 34 + * PURPLE 35 + * CYAN 36 + * WHITE 37 + */ + +#ifdef CONFIG_USB_PRINTF_COLOR_ENABLE +#define _USB_DBG_COLOR(n) CONFIG_USB_PRINTF("\033[" #n "m") +#define _USB_DBG_LOG_HDR(lvl_name, color_n) \ + CONFIG_USB_PRINTF("\033[" #color_n "m[" lvl_name "/" USB_DBG_TAG "] ") +#define _USB_DBG_LOG_X_END \ + CONFIG_USB_PRINTF("\033[0m") +#else +#define _USB_DBG_COLOR(n) +#define _USB_DBG_LOG_HDR(lvl_name, color_n) \ + CONFIG_USB_PRINTF("[" lvl_name "/" USB_DBG_TAG "] ") +#define _USB_DBG_LOG_X_END +#endif + +#define usb_dbg_log_line(lvl, color_n, fmt, ...) \ + do { \ + _USB_DBG_LOG_HDR(lvl, color_n); \ + CONFIG_USB_PRINTF(fmt, ##__VA_ARGS__); \ + _USB_DBG_LOG_X_END; \ + } while (0) + +#if (CONFIG_USB_DBG_LEVEL >= USB_DBG_LOG) +#define USB_LOG_DBG(fmt, ...) usb_dbg_log_line("D", 0, fmt, ##__VA_ARGS__) +#else +#define USB_LOG_DBG(...) {} +#endif + +#if (CONFIG_USB_DBG_LEVEL >= USB_DBG_INFO) +#define USB_LOG_INFO(fmt, ...) usb_dbg_log_line("I", 32, fmt, ##__VA_ARGS__) +#else +#define USB_LOG_INFO(...) {} +#endif + +#if (CONFIG_USB_DBG_LEVEL >= USB_DBG_WARNING) +#define USB_LOG_WRN(fmt, ...) usb_dbg_log_line("W", 33, fmt, ##__VA_ARGS__) +#else +#define USB_LOG_WRN(...) {} +#endif + +#if (CONFIG_USB_DBG_LEVEL >= USB_DBG_ERROR) +#define USB_LOG_ERR(fmt, ...) usb_dbg_log_line("E", 31, fmt, ##__VA_ARGS__) +#else +#define USB_LOG_ERR(...) {} +#endif + +#define USB_LOG_RAW(...) CONFIG_USB_PRINTF(__VA_ARGS__) + +void usb_assert(const char *filename, int linenum); +#define USB_ASSERT(f) \ + do { \ + if (!(f)) \ + usb_assert(__FILE__, __LINE__); \ + } while (0) + +#endif /* USB_LOG_H */ diff --git a/Code/DAP_X033/DAP/CherryUSB/common/usb_osal.h b/Code/DAP_X033/DAP/CherryUSB/common/usb_osal.h new file mode 100644 index 0000000..738efaa --- /dev/null +++ b/Code/DAP_X033/DAP/CherryUSB/common/usb_osal.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_OSAL_H +#define USB_OSAL_H + +#include +#include +#include + +#define USB_OSAL_WAITING_FOREVER (0xFFFFFFFFU) + +typedef void *usb_osal_thread_t; +typedef void *usb_osal_sem_t; +typedef void *usb_osal_mutex_t; +typedef void *usb_osal_mq_t; +typedef void (*usb_thread_entry_t)(void *argument); +typedef void (*usb_timer_handler_t)(void *argument); +struct usb_osal_timer { + usb_timer_handler_t handler; + void *argument; + void *timer; +}; + +/* + * Task with smaller priority value indicates higher task priority +*/ +usb_osal_thread_t usb_osal_thread_create(const char *name, uint32_t stack_size, uint32_t prio, usb_thread_entry_t entry, void *args); +void usb_osal_thread_delete(usb_osal_thread_t thread); + +usb_osal_sem_t usb_osal_sem_create(uint32_t initial_count); +void usb_osal_sem_delete(usb_osal_sem_t sem); +int usb_osal_sem_take(usb_osal_sem_t sem, uint32_t timeout); +int usb_osal_sem_give(usb_osal_sem_t sem); +void usb_osal_sem_reset(usb_osal_sem_t sem); + +usb_osal_mutex_t usb_osal_mutex_create(void); +void usb_osal_mutex_delete(usb_osal_mutex_t mutex); +int usb_osal_mutex_take(usb_osal_mutex_t mutex); +int usb_osal_mutex_give(usb_osal_mutex_t mutex); + +usb_osal_mq_t usb_osal_mq_create(uint32_t max_msgs); +void usb_osal_mq_delete(usb_osal_mq_t mq); +int usb_osal_mq_send(usb_osal_mq_t mq, uintptr_t addr); +int usb_osal_mq_recv(usb_osal_mq_t mq, uintptr_t *addr, uint32_t timeout); + +struct usb_osal_timer *usb_osal_timer_create(const char *name, uint32_t timeout_ms, usb_timer_handler_t handler, void *argument, bool is_period); +void usb_osal_timer_delete(struct usb_osal_timer *timer); +void usb_osal_timer_start(struct usb_osal_timer *timer); +void usb_osal_timer_stop(struct usb_osal_timer *timer); + +size_t usb_osal_enter_critical_section(void); +void usb_osal_leave_critical_section(size_t flag); + +void usb_osal_msleep(uint32_t delay); + +#endif /* USB_OSAL_H */ diff --git a/Code/DAP_X033/DAP/CherryUSB/common/usb_util.h b/Code/DAP_X033/DAP/CherryUSB/common/usb_util.h new file mode 100644 index 0000000..624cd9f --- /dev/null +++ b/Code/DAP_X033/DAP/CherryUSB/common/usb_util.h @@ -0,0 +1,210 @@ +/* + * Copyright (c) 2022-2023, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_UTIL_H +#define USB_UTIL_H + +#if defined(__CC_ARM) +#ifndef __USED +#define __USED __attribute__((used)) +#endif +#ifndef __WEAK +#define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED +#define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION +#define __PACKED_UNION __packed union +#endif +#ifndef __ALIGNED +#define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#elif defined(__GNUC__) +#ifndef __USED +#define __USED __attribute__((used)) +#endif +#ifndef __WEAK +#define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED +#define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION +#define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __ALIGNED +#define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#elif defined(__ICCARM__) || defined(__ICCRX__) || defined(__ICCRISCV__) +#ifndef __USED +#if defined(__ICCARM_V8) || defined(__ICCRISCV__) +#define __USED __attribute__((used)) +#else +#define __USED __root +#endif +#endif + +#ifndef __WEAK +#if defined(__ICCARM_V8) || defined(__ICCRISCV__) +#define __WEAK __attribute__((weak)) +#else +#define __WEAK _Pragma("__weak") +#endif +#endif + +#ifndef __PACKED +#if defined(__ICCARM_V8) || defined(__ICCRISCV__) +#define __PACKED __attribute__((packed, aligned(1))) +#else +/* Needs IAR language extensions */ +#define __PACKED __packed +#endif +#endif + +#ifndef __PACKED_STRUCT +#if defined(__ICCARM_V8) || defined(__ICCRISCV__) +#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#else +/* Needs IAR language extensions */ +#define __PACKED_STRUCT __packed struct +#endif +#endif + +#ifndef __PACKED_UNION +#if defined(__ICCARM_V8) || defined(__ICCRISCV__) +#define __PACKED_UNION union __attribute__((packed, aligned(1))) +#else +/* Needs IAR language extensions */ +#define __PACKED_UNION __packed union +#endif +#endif + +#ifndef __ALIGNED +#if defined(__ICCARM_V8) || defined(__ICCRISCV__) +#define __ALIGNED(x) __attribute__((aligned(x))) +#elif (__VER__ >= 7080000) +/* Needs IAR language extensions */ +#define __ALIGNED(x) __attribute__((aligned(x))) +#else +#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. +#define __ALIGNED(x) +#endif +#endif + +#endif + +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif +#ifndef __ALIGN_END +#define __ALIGN_END __attribute__((aligned(4))) +#endif + +#ifndef ARG_UNUSED +#define ARG_UNUSED(x) (void)(x) +#endif + +#ifndef LO_BYTE +#define LO_BYTE(x) ((uint8_t)(x & 0x00FF)) +#endif + +#ifndef HI_BYTE +#define HI_BYTE(x) ((uint8_t)((x & 0xFF00) >> 8)) +#endif + +#ifndef MAX +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif + +#ifndef MIN +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef BCD +#define BCD(x) ((((x) / 10) << 4) | ((x) % 10)) +#endif + +#ifdef BIT +#undef BIT +#define BIT(n) (1UL << (n)) +#else +#define BIT(n) (1UL << (n)) +#endif + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(array) \ + ((int)((sizeof(array) / sizeof((array)[0])))) +#endif + +#ifndef BSWAP16 +#define BSWAP16(u16) (__builtin_bswap16(u16)) +#endif +#ifndef BSWAP32 +#define BSWAP32(u32) (__builtin_bswap32(u32)) +#endif + +#define GET_BE16(field) \ + (((uint16_t)(field)[0] << 8) | ((uint16_t)(field)[1])) + +#define GET_BE32(field) \ + (((uint32_t)(field)[0] << 24) | ((uint32_t)(field)[1] << 16) | ((uint32_t)(field)[2] << 8) | ((uint32_t)(field)[3] << 0)) + +#define SET_BE16(field, value) \ + do { \ + (field)[0] = (uint8_t)((value) >> 8); \ + (field)[1] = (uint8_t)((value) >> 0); \ + } while (0) + +#define SET_BE24(field, value) \ + do { \ + (field)[0] = (uint8_t)((value) >> 16); \ + (field)[1] = (uint8_t)((value) >> 8); \ + (field)[2] = (uint8_t)((value) >> 0); \ + } while (0) + +#define SET_BE32(field, value) \ + do { \ + (field)[0] = (uint8_t)((value) >> 24); \ + (field)[1] = (uint8_t)((value) >> 16); \ + (field)[2] = (uint8_t)((value) >> 8); \ + (field)[3] = (uint8_t)((value) >> 0); \ + } while (0) + +#define WBVAL(x) (x & 0xFF), ((x >> 8) & 0xFF) +#define DBVAL(x) (x & 0xFF), ((x >> 8) & 0xFF), ((x >> 16) & 0xFF), ((x >> 24) & 0xFF) + +#define PP_NARG(...) \ + PP_NARG_(__VA_ARGS__, PP_RSEQ_N()) +#define PP_NARG_(...) \ + PP_ARG_N(__VA_ARGS__) +#define PP_ARG_N( \ + _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \ + _11, _12, _13, _14, _15, _16, _17, _18, _19, _20, \ + _21, _22, _23, _24, _25, _26, _27, _28, _29, _30, \ + _31, _32, _33, _34, _35, _36, _37, _38, _39, _40, \ + _41, _42, _43, _44, _45, _46, _47, _48, _49, _50, \ + _51, _52, _53, _54, _55, _56, _57, _58, _59, _60, \ + _61, _62, _63, N, ...) N +#define PP_RSEQ_N() \ + 63, 62, 61, 60, \ + 59, 58, 57, 56, 55, 54, 53, 52, 51, 50, \ + 49, 48, 47, 46, 45, 44, 43, 42, 41, 40, \ + 39, 38, 37, 36, 35, 34, 33, 32, 31, 30, \ + 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, \ + 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, \ + 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 + +#define USB_MEM_ALIGNX __attribute__((aligned(CONFIG_USB_ALIGN_SIZE))) + +#define USB_ALIGN_UP(size, align) (((size) + (align)-1) & ~((align)-1)) + +#endif /* USB_UTIL_H */ diff --git a/Code/DAP_X033/DAP/CherryUSB/core/usbd_core.c b/Code/DAP_X033/DAP/CherryUSB/core/usbd_core.c new file mode 100644 index 0000000..3d94a97 --- /dev/null +++ b/Code/DAP_X033/DAP/CherryUSB/core/usbd_core.c @@ -0,0 +1,1225 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" + +/* general descriptor field offsets */ +#define DESC_bLength 0 /** Length offset */ +#define DESC_bDescriptorType 1 /** Descriptor type offset */ + +/* config descriptor field offsets */ +#define CONF_DESC_wTotalLength 2 /** Total length offset */ +#define CONF_DESC_bConfigurationValue 5 /** Configuration value offset */ +#define CONF_DESC_bmAttributes 7 /** configuration characteristics */ + +/* interface descriptor field offsets */ +#define INTF_DESC_bInterfaceNumber 2 /** Interface number offset */ +#define INTF_DESC_bAlternateSetting 3 /** Alternate setting offset */ + +struct usbd_tx_rx_msg { + uint8_t ep; + uint32_t nbytes; + usbd_endpoint_callback cb; +}; + +USB_NOCACHE_RAM_SECTION struct usbd_core_priv { + /** Setup packet */ + USB_MEM_ALIGNX struct usb_setup_packet setup; + /** Pointer to data buffer */ + uint8_t *ep0_data_buf; + /** Remaining bytes in buffer */ + uint32_t ep0_data_buf_residue; + /** Total length of control transfer */ + uint32_t ep0_data_buf_len; + /** Zero length packet flag of control transfer */ + bool zlp_flag; + /** Pointer to registered descriptors */ +#ifdef CONFIG_USBDEV_ADVANCE_DESC + const struct usb_descriptor *descriptors; +#else + const uint8_t *descriptors; + struct usb_msosv1_descriptor *msosv1_desc; + struct usb_msosv2_descriptor *msosv2_desc; + struct usb_bos_descriptor *bos_desc; +#endif + /* Buffer used for storing standard, class and vendor request data */ + USB_MEM_ALIGNX uint8_t req_data[CONFIG_USBDEV_REQUEST_BUFFER_LEN]; + + /** Currently selected configuration */ + uint8_t configuration; + uint8_t speed; +#ifdef CONFIG_USBDEV_TEST_MODE + bool test_req; +#endif + struct usbd_interface *intf[8]; + uint8_t intf_offset; + + struct usbd_tx_rx_msg tx_msg[CONFIG_USBDEV_EP_NUM]; + struct usbd_tx_rx_msg rx_msg[CONFIG_USBDEV_EP_NUM]; + + void (*event_handler)(uint8_t busid, uint8_t event); +} g_usbd_core[CONFIG_USBDEV_MAX_BUS]; + +struct usbd_bus g_usbdev_bus[CONFIG_USBDEV_MAX_BUS]; + +static void usbd_class_event_notify_handler(uint8_t busid, uint8_t event, void *arg); + +static void usbd_print_setup(struct usb_setup_packet *setup) +{ + USB_LOG_INFO("Setup: " + "bmRequestType 0x%02x, bRequest 0x%02x, wValue 0x%04x, wIndex 0x%04x, wLength 0x%04x\r\n", + setup->bmRequestType, + setup->bRequest, + setup->wValue, + setup->wIndex, + setup->wLength); +} + +static bool is_device_configured(uint8_t busid) +{ + return (g_usbd_core[busid].configuration != 0); +} + +/** + * @brief configure and enable endpoint + * + * This function sets endpoint configuration according to one specified in USB + * endpoint descriptor and then enables it for data transfers. + * + * @param [in] ep Endpoint descriptor byte array + * + * @return true if successfully configured and enabled + */ +static bool usbd_set_endpoint(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + USB_LOG_INFO("Open ep:0x%02x type:%u mps:%u\r\n", + ep->bEndpointAddress, + USB_GET_ENDPOINT_TYPE(ep->bmAttributes), + USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize)); + + return usbd_ep_open(busid, ep) == 0 ? true : false; +} +/** + * @brief Disable endpoint for transferring data + * + * This function cancels transfers that are associated with endpoint and + * disabled endpoint itself. + * + * @param [in] ep Endpoint descriptor byte array + * + * @return true if successfully deconfigured and disabled + */ +static bool usbd_reset_endpoint(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + USB_LOG_INFO("Close ep:0x%02x type:%u\r\n", + ep->bEndpointAddress, + USB_GET_ENDPOINT_TYPE(ep->bmAttributes)); + + return usbd_ep_close(busid, ep->bEndpointAddress) == 0 ? true : false; +} + +/** + * @brief get specified USB descriptor + * + * This function parses the list of installed USB descriptors and attempts + * to find the specified USB descriptor. + * + * @param [in] type_index Type and index of the descriptor + * @param [out] data Descriptor data + * @param [out] len Descriptor length + * + * @return true if the descriptor was found, false otherwise + */ +#ifdef CONFIG_USBDEV_ADVANCE_DESC +static bool usbd_get_descriptor(uint8_t busid, uint16_t type_index, uint8_t **data, uint32_t *len) +{ + uint8_t type = 0U; + uint8_t index = 0U; + bool found = true; + uint32_t desc_len = 0; + const uint8_t *desc = NULL; + + type = HI_BYTE(type_index); + index = LO_BYTE(type_index); + + switch (type) { + case USB_DESCRIPTOR_TYPE_DEVICE: + desc = g_usbd_core[busid].descriptors->device_descriptor_callback(g_usbd_core[busid].speed); + if (desc == NULL) { + found = false; + break; + } + desc_len = desc[0]; + break; + case USB_DESCRIPTOR_TYPE_CONFIGURATION: + desc = g_usbd_core[busid].descriptors->config_descriptor_callback(g_usbd_core[busid].speed); + if (desc == NULL) { + found = false; + break; + } + desc_len = ((desc[CONF_DESC_wTotalLength]) | (desc[CONF_DESC_wTotalLength + 1] << 8)); + break; + case USB_DESCRIPTOR_TYPE_STRING: + if (index == USB_OSDESC_STRING_DESC_INDEX) { + USB_LOG_INFO("read MS OS 2.0 descriptor string\r\n"); + + if (!g_usbd_core[busid].descriptors->msosv1_descriptor) { + found = false; + break; + } + + desc = (uint8_t *)g_usbd_core[busid].descriptors->msosv1_descriptor->string; + desc_len = g_usbd_core[busid].descriptors->msosv1_descriptor->string[0]; + } else { + desc = g_usbd_core[busid].descriptors->string_descriptor_callback(g_usbd_core[busid].speed, index); + if (desc == NULL) { + found = false; + break; + } + desc_len = desc[0]; + } + break; + case USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER: + desc = g_usbd_core[busid].descriptors->device_quality_descriptor_callback(g_usbd_core[busid].speed); + if (desc == NULL) { + found = false; + break; + } + desc_len = desc[0]; + break; + case USB_DESCRIPTOR_TYPE_OTHER_SPEED: + desc = g_usbd_core[busid].descriptors->other_speed_descriptor_callback(g_usbd_core[busid].speed); + if (desc == NULL) { + found = false; + break; + } + desc_len = ((desc[CONF_DESC_wTotalLength]) | (desc[CONF_DESC_wTotalLength + 1] << 8)); + break; + + case USB_DESCRIPTOR_TYPE_BINARY_OBJECT_STORE: + USB_LOG_INFO("read BOS descriptor string\r\n"); + + if (!g_usbd_core[busid].descriptors->bos_descriptor) { + found = false; + break; + } + + desc = (uint8_t *)g_usbd_core[busid].descriptors->bos_descriptor->string; + desc_len = g_usbd_core[busid].descriptors->bos_descriptor->string_len; + break; + + default: + found = false; + break; + } + + if (found == false) { + /* nothing found */ + USB_LOG_ERR("descriptor not found!\r\n", type, index); + } else { + // *data = desc; + memcpy(*data, desc, desc_len); + *len = desc_len; + } + return found; +} +#else +static bool usbd_get_descriptor(uint8_t busid, uint16_t type_index, uint8_t **data, uint32_t *len) +{ + uint8_t type = 0U; + uint8_t index = 0U; + uint8_t *p = NULL; + uint32_t cur_index = 0U; + bool found = false; + + type = HI_BYTE(type_index); + index = LO_BYTE(type_index); + + if ((type == USB_DESCRIPTOR_TYPE_STRING) && (index == USB_OSDESC_STRING_DESC_INDEX)) { + USB_LOG_INFO("read MS OS 2.0 descriptor string\r\n"); + + if (!g_usbd_core[busid].msosv1_desc) { + return false; + } + + //*data = (uint8_t *)g_usbd_core[busid].msosv1_desc->string; + memcpy(*data, (uint8_t *)g_usbd_core[busid].msosv1_desc->string, g_usbd_core[busid].msosv1_desc->string[0]); + *len = g_usbd_core[busid].msosv1_desc->string[0]; + + return true; + } else if (type == USB_DESCRIPTOR_TYPE_BINARY_OBJECT_STORE) { + USB_LOG_INFO("read BOS descriptor string\r\n"); + + if (!g_usbd_core[busid].bos_desc) { + return false; + } + + //*data = g_usbd_core[busid].bos_desc->string; + memcpy(*data, (uint8_t *)g_usbd_core[busid].bos_desc->string, g_usbd_core[busid].bos_desc->string_len); + *len = g_usbd_core[busid].bos_desc->string_len; + return true; + } + /* + * Invalid types of descriptors, + * see USB Spec. Revision 2.0, 9.4.3 Get Descriptor + */ + else if ((type == USB_DESCRIPTOR_TYPE_INTERFACE) || (type == USB_DESCRIPTOR_TYPE_ENDPOINT) || +#ifndef CONFIG_USB_HS + (type > USB_DESCRIPTOR_TYPE_ENDPOINT)) { +#else + (type > USB_DESCRIPTOR_TYPE_OTHER_SPEED)) { +#endif + return false; + } + + p = (uint8_t *)g_usbd_core[busid].descriptors; + + cur_index = 0U; + + while (p[DESC_bLength] != 0U) { + if (p[DESC_bDescriptorType] == type) { + if (cur_index == index) { + found = true; + break; + } + + cur_index++; + } + + /* skip to next descriptor */ + p += p[DESC_bLength]; + } + + if (found) { + if ((type == USB_DESCRIPTOR_TYPE_CONFIGURATION) || ((type == USB_DESCRIPTOR_TYPE_OTHER_SPEED))) { + /* configuration or other speed descriptor is an + * exception, length is at offset 2 and 3 + */ + *len = (p[CONF_DESC_wTotalLength]) | + (p[CONF_DESC_wTotalLength + 1] << 8); + } else { + /* normally length is at offset 0 */ + *len = p[DESC_bLength]; + } + memcpy(*data, p, *len); + } else { + /* nothing found */ + USB_LOG_ERR("descriptor not found!\r\n", type, index); + } + + return found; +} +#endif + +/** + * @brief set USB configuration + * + * This function configures the device according to the specified configuration + * index and alternate setting by parsing the installed USB descriptor list. + * A configuration index of 0 unconfigures the device. + * + * @param [in] config_index Configuration index + * @param [in] alt_setting Alternate setting number + * + * @return true if successfully configured false if error or unconfigured + */ +static bool usbd_set_configuration(uint8_t busid, uint8_t config_index, uint8_t alt_setting) +{ + uint8_t cur_alt_setting = 0xFF; + uint8_t cur_config = 0xFF; + bool found = false; + const uint8_t *p; + uint32_t desc_len = 0; + uint32_t current_desc_len = 0; + +#ifdef CONFIG_USBDEV_ADVANCE_DESC + p = g_usbd_core[busid].descriptors->config_descriptor_callback(g_usbd_core[busid].speed); +#else + p = (uint8_t *)g_usbd_core[busid].descriptors; +#endif + /* configure endpoints for this configuration/altsetting */ + while (p[DESC_bLength] != 0U) { + switch (p[DESC_bDescriptorType]) { + case USB_DESCRIPTOR_TYPE_CONFIGURATION: + /* remember current configuration index */ + cur_config = p[CONF_DESC_bConfigurationValue]; + + if (cur_config == config_index) { + found = true; + + current_desc_len = 0; + desc_len = (p[CONF_DESC_wTotalLength]) | + (p[CONF_DESC_wTotalLength + 1] << 8); + } + + break; + + case USB_DESCRIPTOR_TYPE_INTERFACE: + /* remember current alternate setting */ + cur_alt_setting = + p[INTF_DESC_bAlternateSetting]; + break; + + case USB_DESCRIPTOR_TYPE_ENDPOINT: + if ((cur_config != config_index) || + (cur_alt_setting != alt_setting)) { + break; + } + + found = usbd_set_endpoint(busid, (struct usb_endpoint_descriptor *)p); + break; + + default: + break; + } + + /* skip to next descriptor */ + p += p[DESC_bLength]; + current_desc_len += p[DESC_bLength]; + if (current_desc_len >= desc_len && desc_len) { + break; + } + } + + return found; +} + +/** + * @brief set USB interface + * + * @param [in] iface Interface index + * @param [in] alt_setting Alternate setting number + * + * @return true if successfully configured false if error or unconfigured + */ +static bool usbd_set_interface(uint8_t busid, uint8_t iface, uint8_t alt_setting) +{ + const uint8_t *if_desc = NULL; + struct usb_endpoint_descriptor *ep_desc; + uint8_t cur_alt_setting = 0xFF; + uint8_t cur_iface = 0xFF; + bool ret = false; + const uint8_t *p; + uint32_t desc_len = 0; + uint32_t current_desc_len = 0; + +#ifdef CONFIG_USBDEV_ADVANCE_DESC + p = g_usbd_core[busid].descriptors->config_descriptor_callback(g_usbd_core[busid].speed); +#else + p = (uint8_t *)g_usbd_core[busid].descriptors; +#endif + USB_LOG_DBG("iface %u alt_setting %u\r\n", iface, alt_setting); + + while (p[DESC_bLength] != 0U) { + switch (p[DESC_bDescriptorType]) { + case USB_DESCRIPTOR_TYPE_CONFIGURATION: + current_desc_len = 0; + desc_len = (p[CONF_DESC_wTotalLength]) | + (p[CONF_DESC_wTotalLength + 1] << 8); + + break; + + case USB_DESCRIPTOR_TYPE_INTERFACE: + /* remember current alternate setting */ + cur_alt_setting = p[INTF_DESC_bAlternateSetting]; + cur_iface = p[INTF_DESC_bInterfaceNumber]; + + if (cur_iface == iface && + cur_alt_setting == alt_setting) { + if_desc = (void *)p; + } + + USB_LOG_DBG("Current iface %u alt setting %u", + cur_iface, cur_alt_setting); + break; + + case USB_DESCRIPTOR_TYPE_ENDPOINT: + if (cur_iface == iface) { + ep_desc = (struct usb_endpoint_descriptor *)p; + + if (cur_alt_setting != alt_setting) { + ret = usbd_reset_endpoint(busid, ep_desc); + } else { + ret = usbd_set_endpoint(busid, ep_desc); + } + } + + break; + + default: + break; + } + + /* skip to next descriptor */ + p += p[DESC_bLength]; + current_desc_len += p[DESC_bLength]; + if (current_desc_len >= desc_len && desc_len) { + break; + } + } + + usbd_class_event_notify_handler(busid, USBD_EVENT_SET_INTERFACE, (void *)if_desc); + + return ret; +} + +/** + * @brief handle a standard device request + * + * @param [in] setup The setup packet + * @param [in,out] data Data buffer + * @param [in,out] len Pointer to data length + * + * @return true if the request was handled successfully + */ +static bool usbd_std_device_req_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + uint16_t value = setup->wValue; + bool ret = true; + + switch (setup->bRequest) { + case USB_REQUEST_GET_STATUS: + /* bit 0: self-powered */ + /* bit 1: remote wakeup */ + (*data)[0] = 0x00; + (*data)[1] = 0x00; + *len = 2; + break; + + case USB_REQUEST_CLEAR_FEATURE: + case USB_REQUEST_SET_FEATURE: + if (value == USB_FEATURE_REMOTE_WAKEUP) { + if (setup->bRequest == USB_REQUEST_SET_FEATURE) { + g_usbd_core[busid].event_handler(busid, USBD_EVENT_SET_REMOTE_WAKEUP); + } else { + g_usbd_core[busid].event_handler(busid, USBD_EVENT_CLR_REMOTE_WAKEUP); + } + } else if (value == USB_FEATURE_TEST_MODE) { +#ifdef CONFIG_USBDEV_TEST_MODE + g_usbd_core[busid].test_req = true; +#endif + } + *len = 0; + break; + + case USB_REQUEST_SET_ADDRESS: + usbd_set_address(busid, value); + *len = 0; + break; + + case USB_REQUEST_GET_DESCRIPTOR: + ret = usbd_get_descriptor(busid, value, data, len); + break; + + case USB_REQUEST_SET_DESCRIPTOR: + ret = false; + break; + + case USB_REQUEST_GET_CONFIGURATION: + *data = (uint8_t *)&g_usbd_core[busid].configuration; + *len = 1; + break; + + case USB_REQUEST_SET_CONFIGURATION: + value &= 0xFF; + + if (!usbd_set_configuration(busid, value, 0)) { + ret = false; + } else { + g_usbd_core[busid].configuration = value; + usbd_class_event_notify_handler(busid, USBD_EVENT_CONFIGURED, NULL); + g_usbd_core[busid].event_handler(busid, USBD_EVENT_CONFIGURED); + } + *len = 0; + break; + + case USB_REQUEST_GET_INTERFACE: + case USB_REQUEST_SET_INTERFACE: + ret = false; + break; + + default: + ret = false; + break; + } + + return ret; +} + +/** + * @brief handle a standard interface request + * + * @param [in] setup The setup packet + * @param [in,out] data Data buffer + * @param [in,out] len Pointer to data length + * + * @return true if the request was handled successfully + */ +static bool usbd_std_interface_req_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + uint8_t type = HI_BYTE(setup->wValue); + uint8_t intf_num = LO_BYTE(setup->wIndex); + bool ret = true; + + /* Only when device is configured, then interface requests can be valid. */ + if (!is_device_configured(busid)) { + return false; + } + + switch (setup->bRequest) { + case USB_REQUEST_GET_STATUS: + (*data)[0] = 0x00; + (*data)[1] = 0x00; + *len = 2; + break; + + case USB_REQUEST_GET_DESCRIPTOR: + if (type == 0x22) { /* HID_DESCRIPTOR_TYPE_HID_REPORT */ + USB_LOG_INFO("read hid report descriptor\r\n"); + + for (uint8_t i = 0; i < g_usbd_core[busid].intf_offset; i++) { + struct usbd_interface *intf = g_usbd_core[busid].intf[i]; + + if (intf && (intf->intf_num == intf_num)) { + //*data = (uint8_t *)intf->hid_report_descriptor; + memcpy(*data, intf->hid_report_descriptor, intf->hid_report_descriptor_len); + *len = intf->hid_report_descriptor_len; + return true; + } + } + } + ret = false; + break; + case USB_REQUEST_CLEAR_FEATURE: + case USB_REQUEST_SET_FEATURE: + ret = false; + break; + case USB_REQUEST_GET_INTERFACE: + (*data)[0] = 0; + *len = 1; + break; + + case USB_REQUEST_SET_INTERFACE: + usbd_set_interface(busid, setup->wIndex, setup->wValue); + *len = 0; + break; + + default: + ret = false; + break; + } + + return ret; +} + +/** + * @brief handle a standard endpoint request + * + * @param [in] setup The setup packet + * @param [in,out] data Data buffer + * @param [in,out] len Pointer to data length + * + * @return true if the request was handled successfully + */ +static bool usbd_std_endpoint_req_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + uint8_t ep = (uint8_t)setup->wIndex; + bool ret = true; + + /* Only when device is configured, then endpoint requests can be valid. */ + if (!is_device_configured(busid)) { + return false; + } + + switch (setup->bRequest) { + case USB_REQUEST_GET_STATUS: + (*data)[0] = 0x00; + (*data)[1] = 0x00; + *len = 2; + break; + case USB_REQUEST_CLEAR_FEATURE: + if (setup->wValue == USB_FEATURE_ENDPOINT_HALT) { + USB_LOG_ERR("ep:%02x clear halt\r\n", ep); + + usbd_ep_clear_stall(busid, ep); + break; + } else { + ret = false; + } + *len = 0; + break; + case USB_REQUEST_SET_FEATURE: + if (setup->wValue == USB_FEATURE_ENDPOINT_HALT) { + USB_LOG_ERR("ep:%02x set halt\r\n", ep); + + usbd_ep_set_stall(busid, ep); + } else { + ret = false; + } + *len = 0; + break; + + case USB_REQUEST_SYNCH_FRAME: + ret = false; + break; + default: + ret = false; + break; + } + + return ret; +} + +/** + * @brief handle standard requests (list in chapter 9) + * + * @param [in] setup The setup packet + * @param [in,out] data Data buffer + * @param [in,out] len Pointer to data length + * + * @return true if the request was handled successfully + */ +static int usbd_standard_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + int rc = 0; + + switch (setup->bmRequestType & USB_REQUEST_RECIPIENT_MASK) { + case USB_REQUEST_RECIPIENT_DEVICE: + if (usbd_std_device_req_handler(busid, setup, data, len) == false) { + rc = -1; + } + + break; + + case USB_REQUEST_RECIPIENT_INTERFACE: + if (usbd_std_interface_req_handler(busid, setup, data, len) == false) { + rc = -1; + } + + break; + + case USB_REQUEST_RECIPIENT_ENDPOINT: + if (usbd_std_endpoint_req_handler(busid, setup, data, len) == false) { + rc = -1; + } + + break; + + default: + rc = -1; + break; + } + + return rc; +} + +/** + * @brief handler for class requests + * + * If a custom request handler was installed, this handler is called first. + * + * @param [in] setup The setup packet + * @param [in,out] data Data buffer + * @param [in,out] len Pointer to data length + * + * @return true if the request was handled successfully + */ +static int usbd_class_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + if ((setup->bmRequestType & USB_REQUEST_RECIPIENT_MASK) == USB_REQUEST_RECIPIENT_INTERFACE) { + for (uint8_t i = 0; i < g_usbd_core[busid].intf_offset; i++) { + struct usbd_interface *intf = g_usbd_core[busid].intf[i]; + + if (intf && intf->class_interface_handler && (intf->intf_num == (setup->wIndex & 0xFF))) { + return intf->class_interface_handler(busid, setup, data, len); + } + } + } else if ((setup->bmRequestType & USB_REQUEST_RECIPIENT_MASK) == USB_REQUEST_RECIPIENT_ENDPOINT) { + for (uint8_t i = 0; i < g_usbd_core[busid].intf_offset; i++) { + struct usbd_interface *intf = g_usbd_core[busid].intf[i]; + + if (intf && intf->class_endpoint_handler) { + return intf->class_endpoint_handler(busid, setup, data, len); + } + } + } + return -1; +} + +/** + * @brief handler for vendor requests + * + * If a custom request handler was installed, this handler is called first. + * + * @param [in] setup The setup packet + * @param [in,out] data Data buffer + * @param [in,out] len Pointer to data length + * + * @return true if the request was handled successfully + */ +static int usbd_vendor_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + uint32_t desclen; +#ifdef CONFIG_USBDEV_ADVANCE_DESC + if (g_usbd_core[busid].descriptors->msosv1_descriptor) { + if (setup->bRequest == g_usbd_core[busid].descriptors->msosv1_descriptor->vendor_code) { + switch (setup->wIndex) { + case 0x04: + USB_LOG_INFO("get Compat ID\r\n"); + desclen = g_usbd_core[busid].descriptors->msosv1_descriptor->compat_id[0] + + (g_usbd_core[busid].descriptors->msosv1_descriptor->compat_id[1] << 8) + + (g_usbd_core[busid].descriptors->msosv1_descriptor->compat_id[2] << 16) + + (g_usbd_core[busid].descriptors->msosv1_descriptor->compat_id[3] << 24); + + //*data = (uint8_t *)g_usbd_core[busid].descriptors->msosv1_descriptor->compat_id; + memcpy(*data, g_usbd_core[busid].descriptors->msosv1_descriptor->compat_id, desclen); + *len = desclen; + return 0; + case 0x05: + USB_LOG_INFO("get Compat id properties\r\n"); + desclen = g_usbd_core[busid].descriptors->msosv1_descriptor->comp_id_property[setup->wValue][0] + + (g_usbd_core[busid].descriptors->msosv1_descriptor->comp_id_property[setup->wValue][1] << 8) + + (g_usbd_core[busid].descriptors->msosv1_descriptor->comp_id_property[setup->wValue][2] << 16) + + (g_usbd_core[busid].descriptors->msosv1_descriptor->comp_id_property[setup->wValue][3] << 24); + + //*data = (uint8_t *)g_usbd_core[busid].descriptors->msosv1_descriptor->comp_id_property[setup->wValue]; + memcpy(*data, g_usbd_core[busid].descriptors->msosv1_descriptor->comp_id_property[setup->wValue], desclen); + *len = desclen; + return 0; + default: + USB_LOG_ERR("unknown vendor code\r\n"); + return -1; + } + } + } else if (g_usbd_core[busid].descriptors->msosv2_descriptor) { + if (setup->bRequest == g_usbd_core[busid].descriptors->msosv2_descriptor->vendor_code) { + switch (setup->wIndex) { + case WINUSB_REQUEST_GET_DESCRIPTOR_SET: + USB_LOG_INFO("GET MS OS 2.0 Descriptor\r\n"); + + desclen = g_usbd_core[busid].descriptors->msosv2_descriptor->compat_id_len; + //*data = (uint8_t *)g_usbd_core[busid].descriptors->msosv2_descriptor->compat_id; + memcpy(*data, g_usbd_core[busid].descriptors->msosv2_descriptor->compat_id, desclen); + *len = g_usbd_core[busid].descriptors->msosv2_descriptor->compat_id_len; + return 0; + default: + USB_LOG_ERR("unknown vendor code\r\n"); + return -1; + } + } + } else if (g_usbd_core[busid].descriptors->webusb_url_descriptor) { + if (setup->bRequest == g_usbd_core[busid].descriptors->webusb_url_descriptor->vendor_code) { + switch (setup->wIndex) { + case WINUSB_REQUEST_GET_DESCRIPTOR_SET: + USB_LOG_INFO("GET Webusb url Descriptor\r\n"); + + desclen = g_usbd_core[busid].descriptors->webusb_url_descriptor->string_len; + //*data = (uint8_t *)g_usbd_core[busid].descriptors->webusb_url_descriptor->string; + memcpy(*data, g_usbd_core[busid].descriptors->webusb_url_descriptor->string, desclen); + *len = desclen; + return 0; + default: + USB_LOG_ERR("unknown vendor code\r\n"); + return -1; + } + } + } +#else + if (g_usbd_core[busid].msosv1_desc) { + if (setup->bRequest == g_usbd_core[busid].msosv1_desc->vendor_code) { + switch (setup->wIndex) { + case 0x04: + USB_LOG_INFO("get Compat ID\r\n"); + //*data = (uint8_t *)msosv1_desc->compat_id; + desclen = g_usbd_core[busid].msosv1_desc->compat_id[0] + + (g_usbd_core[busid].msosv1_desc->compat_id[1] << 8) + + (g_usbd_core[busid].msosv1_desc->compat_id[2] << 16) + + (g_usbd_core[busid].msosv1_desc->compat_id[3] << 24); + memcpy(*data, g_usbd_core[busid].msosv1_desc->compat_id, desclen); + *len = desclen; + return 0; + case 0x05: + USB_LOG_INFO("get Compat id properties\r\n"); + //*data = (uint8_t *)msosv1_desc->comp_id_property[setup->wValue]; + desclen = g_usbd_core[busid].msosv1_desc->comp_id_property[setup->wValue][0] + + (g_usbd_core[busid].msosv1_desc->comp_id_property[setup->wValue][1] << 8) + + (g_usbd_core[busid].msosv1_desc->comp_id_property[setup->wValue][2] << 16) + + (g_usbd_core[busid].msosv1_desc->comp_id_property[setup->wValue][3] << 24); + memcpy(*data, g_usbd_core[busid].msosv1_desc->comp_id_property[setup->wValue], desclen); + *len = desclen; + return 0; + default: + USB_LOG_ERR("unknown vendor code\r\n"); + return -1; + } + } + } else if (g_usbd_core[busid].msosv2_desc) { + if (setup->bRequest == g_usbd_core[busid].msosv2_desc->vendor_code) { + switch (setup->wIndex) { + case WINUSB_REQUEST_GET_DESCRIPTOR_SET: + USB_LOG_INFO("GET MS OS 2.0 Descriptor\r\n"); + //*data = (uint8_t *)msosv2_desc->compat_id; + memcpy(*data, g_usbd_core[busid].msosv2_desc->compat_id, g_usbd_core[busid].msosv2_desc->compat_id_len); + *len = g_usbd_core[busid].msosv2_desc->compat_id_len; + return 0; + default: + USB_LOG_ERR("unknown vendor code\r\n"); + return -1; + } + } + } +#endif + for (uint8_t i = 0; i < g_usbd_core[busid].intf_offset; i++) { + struct usbd_interface *intf = g_usbd_core[busid].intf[i]; + + if (intf && intf->vendor_handler && (intf->vendor_handler(busid, setup, data, len) == 0)) { + return 0; + } + } + + return -1; +} + +/** + * @brief handle setup request( standard/class/vendor/other) + * + * @param [in] setup The setup packet + * @param [in,out] data Data buffer + * @param [in,out] len Pointer to data length + * + * @return true if the request was handles successfully + */ +static bool usbd_setup_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + switch (setup->bmRequestType & USB_REQUEST_TYPE_MASK) { + case USB_REQUEST_STANDARD: +#ifndef CONFIG_USB_HS + //g_usbd_core[busid].speed = USB_SPEED_FULL; /* next time will support getting device speed */ + if ((setup->bRequest == 0x06) && (setup->wValue == 0x0600) && (g_usbd_core[busid].speed <= USB_SPEED_FULL)) { + USB_LOG_WRN("Ignore DQD in fs\r\n"); /* Device Qualifier Descriptor */ + return false; + } +#endif + if (usbd_standard_request_handler(busid, setup, data, len) < 0) { + USB_LOG_ERR("standard request error\r\n"); + usbd_print_setup(setup); + return false; + } + break; + case USB_REQUEST_CLASS: + if (usbd_class_request_handler(busid, setup, data, len) < 0) { + USB_LOG_ERR("class request error\r\n"); + usbd_print_setup(setup); + return false; + } + break; + case USB_REQUEST_VENDOR: + if (usbd_vendor_request_handler(busid, setup, data, len) < 0) { + USB_LOG_ERR("vendor request error\r\n"); + usbd_print_setup(setup); + return false; + } + break; + + default: + return false; + } + + return true; +} + +static void usbd_class_event_notify_handler(uint8_t busid, uint8_t event, void *arg) +{ + for (uint8_t i = 0; i < g_usbd_core[busid].intf_offset; i++) { + struct usbd_interface *intf = g_usbd_core[busid].intf[i]; + + if (arg) { + struct usb_interface_descriptor *desc = (struct usb_interface_descriptor *)arg; + if (intf && intf->notify_handler && (desc->bInterfaceNumber == (intf->intf_num))) { + intf->notify_handler(busid, event, arg); + } + } else { + if (intf && intf->notify_handler) { + intf->notify_handler(busid, event, arg); + } + } + } +} + +void usbd_event_connect_handler(uint8_t busid) +{ + g_usbd_core[busid].event_handler(busid, USBD_EVENT_CONNECTED); +} + +void usbd_event_disconnect_handler(uint8_t busid) +{ + g_usbd_core[busid].event_handler(busid, USBD_EVENT_DISCONNECTED); +} + +void usbd_event_resume_handler(uint8_t busid) +{ + g_usbd_core[busid].event_handler(busid, USBD_EVENT_RESUME); +} + +void usbd_event_suspend_handler(uint8_t busid) +{ + g_usbd_core[busid].event_handler(busid, USBD_EVENT_SUSPEND); +} + +void usbd_event_reset_handler(uint8_t busid) +{ + usbd_set_address(busid, 0); + g_usbd_core[busid].configuration = 0; + struct usb_endpoint_descriptor ep0; + + ep0.bLength = 7; + ep0.bDescriptorType = USB_DESCRIPTOR_TYPE_ENDPOINT; + ep0.wMaxPacketSize = USB_CTRL_EP_MPS; + ep0.bmAttributes = USB_ENDPOINT_TYPE_CONTROL; + ep0.bEndpointAddress = USB_CONTROL_IN_EP0; + ep0.bInterval = 0; + usbd_ep_open(busid, &ep0); + + ep0.bEndpointAddress = USB_CONTROL_OUT_EP0; + usbd_ep_open(busid, &ep0); + + usbd_class_event_notify_handler(busid, USBD_EVENT_RESET, NULL); + g_usbd_core[busid].event_handler(busid, USBD_EVENT_RESET); +} + +void usbd_event_ep0_setup_complete_handler(uint8_t busid, uint8_t *psetup) +{ + struct usb_setup_packet *setup = &g_usbd_core[busid].setup; + + memcpy(setup, psetup, 8); +#ifdef CONFIG_USBDEV_SETUP_LOG_PRINT + usbd_print_setup(setup); +#endif + if (setup->wLength > CONFIG_USBDEV_REQUEST_BUFFER_LEN) { + if ((setup->bmRequestType & USB_REQUEST_DIR_MASK) == USB_REQUEST_DIR_OUT) { + USB_LOG_ERR("Request buffer too small\r\n"); + usbd_ep_set_stall(busid, USB_CONTROL_IN_EP0); + return; + } + } + + g_usbd_core[busid].ep0_data_buf = g_usbd_core[busid].req_data; + g_usbd_core[busid].ep0_data_buf_residue = setup->wLength; + g_usbd_core[busid].ep0_data_buf_len = setup->wLength; + g_usbd_core[busid].zlp_flag = false; + + /* handle class request when all the data is received */ + if (setup->wLength && ((setup->bmRequestType & USB_REQUEST_DIR_MASK) == USB_REQUEST_DIR_OUT)) { + USB_LOG_DBG("Start reading %d bytes from ep0\r\n", setup->wLength); + usbd_ep_start_read(busid, USB_CONTROL_OUT_EP0, g_usbd_core[busid].ep0_data_buf, setup->wLength); + return; + } + + /* Ask installed handler to process request */ + if (!usbd_setup_request_handler(busid, setup, &g_usbd_core[busid].ep0_data_buf, &g_usbd_core[busid].ep0_data_buf_len)) { + usbd_ep_set_stall(busid, USB_CONTROL_IN_EP0); + return; + } + + /* Send smallest of requested and offered length */ + g_usbd_core[busid].ep0_data_buf_residue = MIN(g_usbd_core[busid].ep0_data_buf_len, setup->wLength); + if (g_usbd_core[busid].ep0_data_buf_residue > CONFIG_USBDEV_REQUEST_BUFFER_LEN) { + USB_LOG_ERR("Request buffer too small\r\n"); + return; + } + + /* Send data or status to host */ + usbd_ep_start_write(busid, USB_CONTROL_IN_EP0, g_usbd_core[busid].ep0_data_buf, g_usbd_core[busid].ep0_data_buf_residue); + /* + * Set ZLP flag when host asks for a bigger length and the data size is + * multiplier of USB_CTRL_EP_MPS, to indicate the transfer done after zlp + * sent. + */ + if ((setup->wLength > g_usbd_core[busid].ep0_data_buf_len) && (!(g_usbd_core[busid].ep0_data_buf_len % USB_CTRL_EP_MPS))) { + g_usbd_core[busid].zlp_flag = true; + USB_LOG_DBG("EP0 Set zlp\r\n"); + } +} + +void usbd_event_ep0_in_complete_handler(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + struct usb_setup_packet *setup = &g_usbd_core[busid].setup; + + g_usbd_core[busid].ep0_data_buf += nbytes; + g_usbd_core[busid].ep0_data_buf_residue -= nbytes; + + USB_LOG_DBG("EP0 send %d bytes, %d remained\r\n", nbytes, g_usbd_core[busid].ep0_data_buf_residue); + + if (g_usbd_core[busid].ep0_data_buf_residue != 0) { + /* Start sending the remain data */ + usbd_ep_start_write(busid, USB_CONTROL_IN_EP0, g_usbd_core[busid].ep0_data_buf, g_usbd_core[busid].ep0_data_buf_residue); + } else { + if (g_usbd_core[busid].zlp_flag == true) { + g_usbd_core[busid].zlp_flag = false; + /* Send zlp to host */ + USB_LOG_DBG("EP0 Send zlp\r\n"); + usbd_ep_start_write(busid, USB_CONTROL_IN_EP0, NULL, 0); + } else { + /* Satisfying three conditions will jump here. + * 1. send status completely + * 2. send zlp completely + * 3. send last data completely. + */ + if (setup->wLength && ((setup->bmRequestType & USB_REQUEST_DIR_MASK) == USB_REQUEST_DIR_IN)) { + /* if all data has sent completely, start reading out status */ + usbd_ep_start_read(busid, USB_CONTROL_OUT_EP0, NULL, 0); + } + +#ifdef CONFIG_USBDEV_TEST_MODE + if (g_usbd_core[busid].test_req) { + usbd_execute_test_mode(busid, HI_BYTE(setup->wIndex)); + g_usbd_core[busid].test_req = false; + } +#endif + } + } +} + +void usbd_event_ep0_out_complete_handler(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + struct usb_setup_packet *setup = &g_usbd_core[busid].setup; + + if (nbytes > 0) { + g_usbd_core[busid].ep0_data_buf += nbytes; + g_usbd_core[busid].ep0_data_buf_residue -= nbytes; + + USB_LOG_DBG("EP0 recv %d bytes, %d remained\r\n", nbytes, g_usbd_core[busid].ep0_data_buf_residue); + + if (g_usbd_core[busid].ep0_data_buf_residue == 0) { + /* Received all, send data to handler */ + g_usbd_core[busid].ep0_data_buf = g_usbd_core[busid].req_data; + if (!usbd_setup_request_handler(busid, setup, &g_usbd_core[busid].ep0_data_buf, &g_usbd_core[busid].ep0_data_buf_len)) { + usbd_ep_set_stall(busid, USB_CONTROL_IN_EP0); + return; + } + + /*Send status to host*/ + usbd_ep_start_write(busid, USB_CONTROL_IN_EP0, NULL, 0); + } else { + /* Start reading the remain data */ + usbd_ep_start_read(busid, USB_CONTROL_OUT_EP0, g_usbd_core[busid].ep0_data_buf, g_usbd_core[busid].ep0_data_buf_residue); + } + } else { + /* Read out status completely, do nothing */ + USB_LOG_DBG("EP0 recv out status\r\n"); + } +} + +void usbd_event_ep_in_complete_handler(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + if (g_usbd_core[busid].tx_msg[ep & 0x7f].cb) { + g_usbd_core[busid].tx_msg[ep & 0x7f].cb(busid, ep, nbytes); + } +} + +void usbd_event_ep_out_complete_handler(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + if (g_usbd_core[busid].rx_msg[ep & 0x7f].cb) { + g_usbd_core[busid].rx_msg[ep & 0x7f].cb(busid, ep, nbytes); + } +} + +#ifdef CONFIG_USBDEV_ADVANCE_DESC +void usbd_desc_register(uint8_t busid, const struct usb_descriptor *desc) +{ + memset(&g_usbd_core[busid], 0, sizeof(struct usbd_core_priv)); + + g_usbd_core[busid].descriptors = desc; + g_usbd_core[busid].intf_offset = 0; + + g_usbd_core[busid].tx_msg[0].ep = 0x80; + g_usbd_core[busid].tx_msg[0].cb = usbd_event_ep0_in_complete_handler; + g_usbd_core[busid].rx_msg[0].ep = 0x00; + g_usbd_core[busid].rx_msg[0].cb = usbd_event_ep0_out_complete_handler; +} +#else +void usbd_desc_register(uint8_t busid, const uint8_t *desc) +{ + memset(&g_usbd_core[busid], 0, sizeof(struct usbd_core_priv)); + + g_usbd_core[busid].descriptors = desc; + g_usbd_core[busid].intf_offset = 0; + + g_usbd_core[busid].tx_msg[0].ep = 0x80; + g_usbd_core[busid].tx_msg[0].cb = usbd_event_ep0_in_complete_handler; + g_usbd_core[busid].rx_msg[0].ep = 0x00; + g_usbd_core[busid].rx_msg[0].cb = usbd_event_ep0_out_complete_handler; +} + +/* Register MS OS Descriptors version 1 */ +void usbd_msosv1_desc_register(uint8_t busid, struct usb_msosv1_descriptor *desc) +{ + g_usbd_core[busid].msosv1_desc = desc; +} + +/* Register MS OS Descriptors version 2 */ +void usbd_msosv2_desc_register(uint8_t busid, struct usb_msosv2_descriptor *desc) +{ + g_usbd_core[busid].msosv2_desc = desc; +} + +void usbd_bos_desc_register(uint8_t busid, struct usb_bos_descriptor *desc) +{ + g_usbd_core[busid].bos_desc = desc; +} +#endif + +void usbd_add_interface(uint8_t busid, struct usbd_interface *intf) +{ + intf->intf_num = g_usbd_core[busid].intf_offset; + g_usbd_core[busid].intf[g_usbd_core[busid].intf_offset] = intf; + g_usbd_core[busid].intf_offset++; +} + +void usbd_add_endpoint(uint8_t busid, struct usbd_endpoint *ep) +{ + if (ep->ep_addr & 0x80) { + g_usbd_core[busid].tx_msg[ep->ep_addr & 0x7f].ep = ep->ep_addr; + g_usbd_core[busid].tx_msg[ep->ep_addr & 0x7f].cb = ep->ep_cb; + } else { + g_usbd_core[busid].rx_msg[ep->ep_addr & 0x7f].ep = ep->ep_addr; + g_usbd_core[busid].rx_msg[ep->ep_addr & 0x7f].cb = ep->ep_cb; + } +} + +bool usb_device_is_configured(uint8_t busid) +{ + return g_usbd_core[busid].configuration; +} + +int usbd_initialize(uint8_t busid, uint32_t reg_base, void (*event_handler)(uint8_t busid, uint8_t event)) +{ + int ret; + struct usbd_bus *bus; + + if (busid >= CONFIG_USBDEV_MAX_BUS) { + USB_LOG_ERR("bus overflow\r\n"); + while (1) { + } + } + + bus = &g_usbdev_bus[busid]; + bus->reg_base = reg_base; + + g_usbd_core[busid].event_handler = event_handler; + ret = usb_dc_init(busid); + usbd_class_event_notify_handler(busid, USBD_EVENT_INIT, NULL); + g_usbd_core[busid].event_handler(busid, USBD_EVENT_INIT); + return ret; +} + +int usbd_deinitialize(uint8_t busid) +{ + g_usbd_core[busid].intf_offset = 0; + usb_dc_deinit(busid); + usbd_class_event_notify_handler(busid, USBD_EVENT_DEINIT, NULL); + g_usbd_core[busid].event_handler(busid, USBD_EVENT_DEINIT); + return 0; +} diff --git a/Code/DAP_X033/DAP/CherryUSB/core/usbd_core.h b/Code/DAP_X033/DAP/CherryUSB/core/usbd_core.h new file mode 100644 index 0000000..0014d96 --- /dev/null +++ b/Code/DAP_X033/DAP/CherryUSB/core/usbd_core.h @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_CORE_H +#define USBD_CORE_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include + +#include "usb_config.h" +#include "usb_util.h" +#include "usb_errno.h" +#include "usb_def.h" +#include "usb_list.h" +#include "usb_log.h" +#include "usb_dc.h" + +enum usbd_event_type { + /* USB DCD IRQ */ + USBD_EVENT_ERROR, /** USB error reported by the controller */ + USBD_EVENT_RESET, /** USB reset */ + USBD_EVENT_SOF, /** Start of Frame received */ + USBD_EVENT_CONNECTED, /** USB connected*/ + USBD_EVENT_DISCONNECTED, /** USB disconnected */ + USBD_EVENT_SUSPEND, /** USB connection suspended by the HOST */ + USBD_EVENT_RESUME, /** USB connection resumed by the HOST */ + + /* USB DEVICE STATUS */ + USBD_EVENT_CONFIGURED, /** USB configuration done */ + USBD_EVENT_SET_INTERFACE, /** USB interface selected */ + USBD_EVENT_SET_REMOTE_WAKEUP, /** USB set remote wakeup */ + USBD_EVENT_CLR_REMOTE_WAKEUP, /** USB clear remote wakeup */ + USBD_EVENT_INIT, /** USB init done when call usbd_initialize */ + USBD_EVENT_DEINIT, /** USB deinit done when call usbd_deinitialize */ + USBD_EVENT_UNKNOWN +}; + +typedef int (*usbd_request_handler)(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len); +typedef void (*usbd_endpoint_callback)(uint8_t busid, uint8_t ep, uint32_t nbytes); +typedef void (*usbd_notify_handler)(uint8_t busid, uint8_t event, void *arg); + +struct usbd_endpoint { + uint8_t ep_addr; + usbd_endpoint_callback ep_cb; +}; + +struct usbd_interface { + usbd_request_handler class_interface_handler; + usbd_request_handler class_endpoint_handler; + usbd_request_handler vendor_handler; + usbd_notify_handler notify_handler; + const uint8_t *hid_report_descriptor; + uint32_t hid_report_descriptor_len; + uint8_t intf_num; +}; + +struct usb_descriptor { + const uint8_t *(*device_descriptor_callback)(uint8_t speed); + const uint8_t *(*config_descriptor_callback)(uint8_t speed); + const uint8_t *(*device_quality_descriptor_callback)(uint8_t speed); + const uint8_t *(*other_speed_descriptor_callback)(uint8_t speed); + const uint8_t *(*string_descriptor_callback)(uint8_t speed, uint8_t index); + const struct usb_msosv1_descriptor *msosv1_descriptor; + const struct usb_msosv2_descriptor *msosv2_descriptor; + const struct usb_webusb_url_ex_descriptor *webusb_url_descriptor; + const struct usb_bos_descriptor *bos_descriptor; +}; + +struct usbd_bus { + uint8_t busid; + uint32_t reg_base; +}; + +extern struct usbd_bus g_usbdev_bus[]; + +#ifdef USBD_IRQHandler +#error USBD_IRQHandler is obsolete, please call USBD_IRQHandler(xxx) in your irq +#endif + +#ifdef CONFIG_USBDEV_ADVANCE_DESC +void usbd_desc_register(uint8_t busid, const struct usb_descriptor *desc); +#else +void usbd_desc_register(uint8_t busid, const uint8_t *desc); +void usbd_msosv1_desc_register(uint8_t busid, struct usb_msosv1_descriptor *desc); +void usbd_msosv2_desc_register(uint8_t busid, struct usb_msosv2_descriptor *desc); +void usbd_bos_desc_register(uint8_t busid, struct usb_bos_descriptor *desc); +#endif + +void usbd_add_interface(uint8_t busid, struct usbd_interface *intf); +void usbd_add_endpoint(uint8_t busid, struct usbd_endpoint *ep); + +bool usb_device_is_configured(uint8_t busid); +int usbd_initialize(uint8_t busid, uint32_t reg_base, void (*event_handler)(uint8_t busid, uint8_t event)); +int usbd_deinitialize(uint8_t busid); + +#ifdef __cplusplus +} +#endif + +#endif /* USBD_CORE_H */ diff --git a/Code/DAP_X033/DAP/CherryUSB/port/ch32/usb_ch58x_dc_usbfs.c b/Code/DAP_X033/DAP/CherryUSB/port/ch32/usb_ch58x_dc_usbfs.c new file mode 100644 index 0000000..66da75e --- /dev/null +++ b/Code/DAP_X033/DAP/CherryUSB/port/ch32/usb_ch58x_dc_usbfs.c @@ -0,0 +1,626 @@ +#include "usbd_core.h" +#include "usb_ch58x_usbfs_reg.h" + +/** + * @brief Related register macro + */ +#define USB0_BASE 0x40023400u +#define USB1_BASE 0x40008400u + +#ifndef USBD +#define USBD USB0_BASE +#endif +#define CH58x_USBFS_DEV ((USB_FS_TypeDef *)USBD) + +#ifndef USBD_IRQHandler +#define USBD_IRQHandler USBFS_IRQHandler //use actual usb irq name instead +#endif +void USBD_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); + +/*!< 8-bit value of endpoint control register */ +#define EPn_CTRL(epid) \ + *(volatile uint8_t *)(&(CH58x_USBFS_DEV->UEP0_CTRL) + epid * 4 + (epid / 5) * 48) + +/*!< The length register value of the endpoint send buffer */ +#define EPn_TX_LEN(epid) \ + *(volatile uint8_t *)(&(CH58x_USBFS_DEV->UEP0_T_LEN) + epid * 4 + (epid / 5) * 48) + +/*!< Read setup packet to use in ep0 in */ +#define GET_SETUP_PACKET(data_add) \ + *(struct usb_setup_packet *)data_add + +/*!< Set epid ep tx valid // Not an isochronous endpoint */ +#define EPn_SET_TX_VALID(epid) \ + EPn_CTRL(epid) = (EPn_CTRL(epid) & ~MASK_UEP_T_RES) | UEP_T_RES_ACK; +/*!< Set epid ep rx valid // Not an isochronous endpoint */ +#define EPn_SET_RX_VALID(epid) \ + EPn_CTRL(epid) = (EPn_CTRL(epid) & ~MASK_UEP_R_RES) | UEP_R_RES_ACK; +/*!< Set epid ep tx valid // Isochronous endpoint */ +#define EPn_SET_TX_ISO_VALID(epid) \ + EPn_CTRL(epid) = (EPn_CTRL(epid) & ~MASK_UEP_T_RES) | UEP_T_RES_TOUT; +/*!< Set epid ep rx valid // Isochronous endpoint */ +#define EPn_SET_RX_ISO_VALID(epid) \ + EPn_CTRL(epid) = (EPn_CTRL(epid) & ~MASK_UEP_R_RES) | UEP_R_RES_TOUT; +/*!< Set epid ep tx nak */ +#define EPn_SET_TX_NAK(epid) \ + EPn_CTRL(epid) = (EPn_CTRL(epid) & ~MASK_UEP_T_RES) | UEP_T_RES_NAK; +/*!< Set epid ep rx nak */ +#define EPn_SET_RX_NAK(epid) \ + EPn_CTRL(epid) = (EPn_CTRL(epid) & ~MASK_UEP_R_RES) | UEP_R_RES_NAK; +/*!< Set epid ep tx stall */ +#define EPn_SET_TX_STALL(epid) \ + EPn_CTRL(epid) = (EPn_CTRL(epid) & ~MASK_UEP_T_RES) | UEP_T_RES_STALL +/*!< Set epid ep rx stall */ +#define EPn_SET_RX_STALL(epid) \ + EPn_CTRL(epid) = (EPn_CTRL(epid) & ~MASK_UEP_R_RES) | UEP_R_RES_STALL +/*!< Clear epid ep tx stall */ +#define EPn_CLR_TX_STALL(epid) \ + EPn_CTRL(epid) = (EPn_CTRL(epid) & ~(RB_UEP_T_TOG | MASK_UEP_T_RES)) | UEP_T_RES_NAK +/*!< Clear epid ep rx stall */ +#define EPn_CLR_RX_STALL(epid) \ + EPn_CTRL(epid) = (EPn_CTRL(epid) & ~(RB_UEP_R_TOG | MASK_UEP_R_RES)) | UEP_R_RES_ACK +/*!< Set epid ep tx len */ +#define EPn_SET_TX_LEN(epid, len) \ + EPn_TX_LEN(epid) = len +/*!< Get epid ep rx len */ +#define EPn_GET_RX_LEN(epid) \ + CH58x_USBFS_DEV->USB_RX_LEN + +/*!< ep nums */ +#ifndef USB_NUM_BIDIR_ENDPOINTS +#define USB_NUM_BIDIR_ENDPOINTS 8 +#endif +/*!< ep mps */ +#define EP_MPS 64 +/*!< set ep4 in mps 64 */ +#define EP4_IN_MPS EP_MPS +/*!< set ep4 out mps 64 */ +#define EP4_OUT_MPS EP_MPS + +/*!< User defined assignment endpoint RAM */ +__attribute__((aligned(4))) uint8_t ep0_data_buff[64 + EP4_OUT_MPS + EP4_IN_MPS]; /*!< ep0(64)+ep4_out(64)+ep4_in(64) */ +__attribute__((aligned(4))) uint8_t ep1_data_buff[64 + 64]; /*!< ep1_out(64)+ep1_in(64) */ +__attribute__((aligned(4))) uint8_t ep2_data_buff[64 + 64]; /*!< ep2_out(64)+ep2_in(64) */ +__attribute__((aligned(4))) uint8_t ep3_data_buff[64 + 64]; /*!< ep3_out(64)+ep3_in(64) */ +#if (USB_NUM_BIDIR_ENDPOINTS == 8) +/** + * This dcd porting can be used on ch581, ch582, ch583, + * and also on ch571, ch572, and ch573. Note that only five endpoints are available for ch571, ch572, and ch573. + */ +__attribute__((aligned(4))) uint8_t ep5_data_buff[64 + 64]; /*!< ep5_out(64)+ep5_in(64) */ +__attribute__((aligned(4))) uint8_t ep6_data_buff[64 + 64]; /*!< ep6_out(64)+ep6_in(64) */ +__attribute__((aligned(4))) uint8_t ep7_data_buff[64 + 64]; /*!< ep7_out(64)+ep7_in(64) */ +#endif +/** + * @brief Endpoint information structure + */ +typedef struct _usbd_ep_info { + uint8_t mps; /*!< Maximum packet length of endpoint */ + uint8_t eptype; /*!< Endpoint Type */ + uint8_t *ep_ram_addr; /*!< Endpoint buffer address */ + + uint8_t ep_enable; /* Endpoint enable */ + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t actual_xfer_len; +} usbd_ep_info; + +/*!< ch58x usb */ +static struct _ch58x_core_prvi { + uint8_t address; /*!< Address */ + usbd_ep_info ep_in[USB_NUM_BIDIR_ENDPOINTS]; + usbd_ep_info ep_out[USB_NUM_BIDIR_ENDPOINTS]; + struct usb_setup_packet setup; +} usb_dc_cfg; + +__WEAK void usb_dc_low_level_init(void) +{ +} + +__WEAK void usb_dc_low_level_deinit(void) +{ +} + +/** + * @brief USB initialization + * @pre None + * @param[in] None + * @retval >=0 success otherwise failure + */ +int usb_dc_init(uint8_t busid) +{ + usb_dc_cfg.ep_in[0].ep_ram_addr = ep0_data_buff; + usb_dc_cfg.ep_out[0].ep_ram_addr = ep0_data_buff; + + usb_dc_cfg.ep_in[1].ep_ram_addr = ep1_data_buff + 64; + usb_dc_cfg.ep_out[1].ep_ram_addr = ep1_data_buff; + + usb_dc_cfg.ep_in[2].ep_ram_addr = ep2_data_buff + 64; + usb_dc_cfg.ep_out[2].ep_ram_addr = ep2_data_buff; + + usb_dc_cfg.ep_in[3].ep_ram_addr = ep3_data_buff + 64; + usb_dc_cfg.ep_out[3].ep_ram_addr = ep3_data_buff; + + usb_dc_cfg.ep_in[4].ep_ram_addr = ep0_data_buff + 64 + EP4_OUT_MPS; + usb_dc_cfg.ep_out[4].ep_ram_addr = ep0_data_buff + 64; +#if (USB_NUM_BIDIR_ENDPOINTS == 8) + usb_dc_cfg.ep_in[5].ep_ram_addr = ep5_data_buff + 64; + usb_dc_cfg.ep_out[5].ep_ram_addr = ep5_data_buff; + + usb_dc_cfg.ep_in[6].ep_ram_addr = ep6_data_buff + 64; + usb_dc_cfg.ep_out[6].ep_ram_addr = ep6_data_buff; + + usb_dc_cfg.ep_in[7].ep_ram_addr = ep7_data_buff + 64; + usb_dc_cfg.ep_out[7].ep_ram_addr = ep7_data_buff; +#endif + /*!< Set the mode first and cancel RB_UC_CLR_ALL */ + CH58x_USBFS_DEV->USB_CTRL = 0x00; + CH58x_USBFS_DEV->UEP4_1_MOD = RB_UEP4_RX_EN | RB_UEP4_TX_EN | RB_UEP1_RX_EN | RB_UEP1_TX_EN; /*!< EP4 OUT+IN EP1 OUT+IN */ + CH58x_USBFS_DEV->UEP2_3_MOD = RB_UEP2_RX_EN | RB_UEP2_TX_EN | RB_UEP3_RX_EN | RB_UEP3_TX_EN; /*!< EP2 OUT+IN EP3 OUT+IN */ +#if (USB_NUM_BIDIR_ENDPOINTS == 8) + CH58x_USBFS_DEV->UEP567_MOD = RB_UEP5_RX_EN | RB_UEP5_TX_EN | RB_UEP6_RX_EN | RB_UEP6_TX_EN | RB_UEP7_RX_EN | RB_UEP7_TX_EN; /*!< EP5 EP6 EP7 OUT+IN */ +#endif + CH58x_USBFS_DEV->UEP0_DMA = (uint16_t)(uint32_t)ep0_data_buff; + CH58x_USBFS_DEV->UEP1_DMA = (uint16_t)(uint32_t)ep1_data_buff; + CH58x_USBFS_DEV->UEP2_DMA = (uint16_t)(uint32_t)ep2_data_buff; + CH58x_USBFS_DEV->UEP3_DMA = (uint16_t)(uint32_t)ep3_data_buff; +#if (USB_NUM_BIDIR_ENDPOINTS == 8) + CH58x_USBFS_DEV->UEP5_DMA = (uint16_t)(uint32_t)ep5_data_buff; + CH58x_USBFS_DEV->UEP6_DMA = (uint16_t)(uint32_t)ep6_data_buff; + CH58x_USBFS_DEV->UEP7_DMA = (uint16_t)(uint32_t)ep7_data_buff; +#endif + CH58x_USBFS_DEV->UEP0_CTRL = UEP_R_RES_NAK | UEP_T_RES_NAK; + CH58x_USBFS_DEV->UEP1_CTRL = UEP_R_RES_NAK | UEP_T_RES_NAK | RB_UEP_AUTO_TOG; + CH58x_USBFS_DEV->UEP2_CTRL = UEP_R_RES_NAK | UEP_T_RES_NAK | RB_UEP_AUTO_TOG; + CH58x_USBFS_DEV->UEP3_CTRL = UEP_R_RES_NAK | UEP_T_RES_NAK | RB_UEP_AUTO_TOG; + CH58x_USBFS_DEV->UEP4_CTRL = UEP_R_RES_NAK | UEP_T_RES_NAK; +#if (USB_NUM_BIDIR_ENDPOINTS == 8) + CH58x_USBFS_DEV->UEP5_CTRL = UEP_R_RES_NAK | UEP_T_RES_NAK | RB_UEP_AUTO_TOG; + CH58x_USBFS_DEV->UEP6_CTRL = UEP_R_RES_NAK | UEP_T_RES_NAK | RB_UEP_AUTO_TOG; + CH58x_USBFS_DEV->UEP7_CTRL = UEP_R_RES_NAK | UEP_T_RES_NAK | RB_UEP_AUTO_TOG; +#endif + CH58x_USBFS_DEV->USB_DEV_AD = 0x00; + + /*!< Start the USB device and DMA, and automatically return to NAK before the interrupt flag is cleared during the interrupt */ + CH58x_USBFS_DEV->USB_CTRL = RB_UC_DEV_PU_EN | RB_UC_INT_BUSY | RB_UC_DMA_EN; + if ((uint32_t) & (CH58x_USBFS_DEV->USB_CTRL) == (uint32_t)USB0_BASE) { + /*!< USB0 */ + R16_PIN_ANALOG_IE |= RB_PIN_USB_IE | RB_PIN_USB_DP_PU; + } else if ((uint32_t) & (CH58x_USBFS_DEV->USB_CTRL) == (uint32_t)USB1_BASE) { + /*!< USB1 */ + R16_PIN_ANALOG_IE |= RB_PIN_USB2_IE | RB_PIN_USB2_DP_PU; + } + + CH58x_USBFS_DEV->USB_INT_FG = 0xff; /*!< Clear interrupt flag */ + CH58x_USBFS_DEV->UDEV_CTRL = RB_UD_PD_DIS | RB_UD_PORT_EN; /*!< Allow USB port */ + CH58x_USBFS_DEV->USB_INT_EN = RB_UIE_SUSPEND | RB_UIE_BUS_RST | RB_UIE_TRANSFER; + + usb_dc_low_level_init(); + return 0; +} + +int usb_dc_deinit(uint8_t busid) +{ + return 0; +} + +/** + * @brief Set address + * @pre None + * @param[in] address ：8-bit valid address + * @retval >=0 success otherwise failure + */ +int usbd_set_address(uint8_t busid, const uint8_t address) +{ + if (address == 0) { + CH58x_USBFS_DEV->USB_DEV_AD = (CH58x_USBFS_DEV->USB_DEV_AD & 0x80) | address; + } + usb_dc_cfg.address = address; + return 0; +} + +uint8_t usbd_get_port_speed(uint8_t busid, const uint8_t port) +{ + return USB_SPEED_FULL; +} + +/** + * @brief Open endpoint + * @pre None + * @param[in] ep_cfg : Endpoint configuration structure pointer + * @retval >=0 success otherwise failure + */ +int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + /*!< ep id */ + uint8_t epid = USB_EP_GET_IDX(ep->bEndpointAddress); + if (epid > (USB_NUM_BIDIR_ENDPOINTS - 1)) { + /** + * If you use ch58x, you can change the USB_NUM_BIDIR_ENDPOINTS set to 8 + */ + USB_LOG_ERR("Ep addr %02x overflow\r\n", ep->bEndpointAddress); + return -1; + } + + /*!< ep max packet length */ + uint8_t mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + /*!< update ep max packet length */ + if (USB_EP_DIR_IS_IN(ep->bEndpointAddress)) { + /*!< in */ + usb_dc_cfg.ep_in[epid].ep_enable = true; + usb_dc_cfg.ep_in[epid].mps = mps; + usb_dc_cfg.ep_in[epid].eptype = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + } else if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress)) { + /*!< out */ + usb_dc_cfg.ep_out[epid].ep_enable = true; + usb_dc_cfg.ep_out[epid].mps = mps; + usb_dc_cfg.ep_out[epid].eptype = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + } + return 0; +} + +/** + * @brief Close endpoint + * @pre None + * @param[in] ep ： Endpoint address + * @retval >=0 success otherwise failure + */ +int usbd_ep_close(uint8_t busid, const uint8_t ep) +{ + /*!< ep id */ + uint8_t epid = USB_EP_GET_IDX(ep); + if (USB_EP_DIR_IS_IN(ep)) { + /*!< in */ + usb_dc_cfg.ep_in[epid].ep_enable = false; + } else if (USB_EP_DIR_IS_OUT(ep)) { + /*!< out */ + usb_dc_cfg.ep_out[epid].ep_enable = false; + } + return 0; +} + + +/** + * @brief Endpoint setting stall + * @pre None + * @param[in] ep ： Endpoint address + * @retval >=0 success otherwise failure + */ +int usbd_ep_set_stall(uint8_t busid, const uint8_t ep) +{ + /*!< ep id */ + uint8_t epid = USB_EP_GET_IDX(ep); + if (USB_EP_DIR_IS_OUT(ep)) { + EPn_SET_RX_STALL(epid); + } else { + EPn_SET_TX_STALL(epid); + } + return 0; +} + +/** + * @brief Endpoint clear stall + * @pre None + * @param[in] ep ： Endpoint address + * @retval >=0 success otherwise failure + */ +int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t epid = USB_EP_GET_IDX(ep); + if (USB_EP_DIR_IS_OUT(ep)) { + EPn_CLR_RX_STALL(epid); + } else { + EPn_CLR_TX_STALL(epid); + } + return 0; +} + +/** + * @brief Check endpoint status + * @pre None + * @param[in] ep ： Endpoint address + * @param[out] stalled ： Outgoing endpoint status + * @retval >=0 success otherwise failure + */ +int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled) +{ + if (USB_EP_DIR_IS_OUT(ep)) { + } else { + } + return 0; +} + +/** + * @brief Setup in ep transfer setting and start transfer. + * + * This function is asynchronous. + * This function is similar to uart with tx dma. + * + * This function is called to write data to the specified endpoint. The + * supplied usbd_endpoint_callback function will be called when data is transmitted + * out. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data Pointer to data to write + * @param[in] data_len Length of the data requested to write. This may + * be zero for a zero length status packet. + * @return 0 on success, negative errno code on fail. + */ +int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + if (!usb_dc_cfg.ep_in[ep_idx].ep_enable) { + return -2; + } + if ((uint32_t)data & 0x03) { + return -3; + } + + usb_dc_cfg.ep_in[ep_idx].xfer_buf = (uint8_t *)data; + usb_dc_cfg.ep_in[ep_idx].xfer_len = data_len; + usb_dc_cfg.ep_in[ep_idx].actual_xfer_len = 0; + + if (data_len == 0) { + /*!< write 0 len data */ + EPn_SET_TX_LEN(ep_idx, 0); + /*!< enable tx */ + if (usb_dc_cfg.ep_in[ep_idx].eptype != USB_ENDPOINT_TYPE_ISOCHRONOUS) { + EPn_SET_TX_VALID(ep_idx); + } else { + EPn_SET_TX_ISO_VALID(ep_idx); + } + /*!< return */ + return 0; + } else { + /*!< Not zlp */ + data_len = MIN(data_len, usb_dc_cfg.ep_in[ep_idx].mps); + /*!< write buff */ + memcpy(usb_dc_cfg.ep_in[ep_idx].ep_ram_addr, data, data_len); + /*!< write real_wt_nums len data */ + EPn_SET_TX_LEN(ep_idx, data_len); + /*!< enable tx */ + if (usb_dc_cfg.ep_in[ep_idx].eptype != USB_ENDPOINT_TYPE_ISOCHRONOUS) { + EPn_SET_TX_VALID(ep_idx); + } else { + EPn_SET_TX_ISO_VALID(ep_idx); + } + } + return 0; +} + +/** + * @brief Setup out ep transfer setting and start transfer. + * + * This function is asynchronous. + * This function is similar to uart with rx dma. + * + * This function is called to read data to the specified endpoint. The + * supplied usbd_endpoint_callback function will be called when data is received + * in. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data Pointer to data to read + * @param[in] data_len Max length of the data requested to read. + * + * @return 0 on success, negative errno code on fail. + */ +int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + if (!usb_dc_cfg.ep_out[ep_idx].ep_enable) { + return -2; + } + if ((uint32_t)data & 0x03) { + return -3; + } + + usb_dc_cfg.ep_out[ep_idx].xfer_buf = (uint8_t *)data; + usb_dc_cfg.ep_out[ep_idx].xfer_len = data_len; + usb_dc_cfg.ep_out[ep_idx].actual_xfer_len = 0; + + if (data_len == 0) { + } else { + data_len = MIN(data_len, usb_dc_cfg.ep_out[ep_idx].mps); + } + + if (usb_dc_cfg.ep_out[ep_idx].eptype != USB_ENDPOINT_TYPE_ISOCHRONOUS) { + EPn_SET_RX_VALID(ep_idx); + } else { + EPn_SET_RX_ISO_VALID(ep_idx); + } + return 0; +} + +/** + * @brief USB interrupt processing function + * @pre None + * @param[in] None + * @retval None + */ +void USBD_IRQHandler(void) +{ + volatile uint8_t intflag = 0; + intflag = CH58x_USBFS_DEV->USB_INT_FG; + + if (intflag & RB_UIF_TRANSFER) { + if ((CH58x_USBFS_DEV->USB_INT_ST & MASK_UIS_TOKEN) != MASK_UIS_TOKEN) { + uint8_t epid = ((CH58x_USBFS_DEV->USB_INT_ST & (MASK_UIS_TOKEN | MASK_UIS_ENDP)) & 0x0f); + switch ((CH58x_USBFS_DEV->USB_INT_ST & (MASK_UIS_TOKEN | MASK_UIS_ENDP)) & 0xf0) { + case UIS_TOKEN_IN: + if (epid == 0) { + /** + * IN The host takes away the data that has been stored in FIFO + */ + switch (usb_dc_cfg.setup.bmRequestType >> USB_REQUEST_DIR_SHIFT) { + case 1: + /*!< Get */ + CH58x_USBFS_DEV->UEP0_CTRL ^= RB_UEP_T_TOG; + /** + * Here is to take away the last data, and the IN interrupt will be triggered only after it is successfully taken away. + * Therefore, the status of the in endpoint is set to NAK here. If there is data transmission, + * the endpoint status will be set to ack again in the in handler of EP0. + */ + EPn_SET_TX_NAK(0); + + /*!< IN */ + if (usb_dc_cfg.ep_in[0].xfer_len > usb_dc_cfg.ep_in[0].mps) { + usb_dc_cfg.ep_in[0].xfer_len -= usb_dc_cfg.ep_in[0].mps; + usb_dc_cfg.ep_in[0].actual_xfer_len += usb_dc_cfg.ep_in[0].mps; + usbd_event_ep_in_complete_handler(0, 0 | 0x80, usb_dc_cfg.ep_in[0].actual_xfer_len); + } else { + usb_dc_cfg.ep_in[0].actual_xfer_len += usb_dc_cfg.ep_in[0].xfer_len; + usb_dc_cfg.ep_in[0].xfer_len = 0; + usbd_event_ep_in_complete_handler(0, 0 | 0x80, usb_dc_cfg.ep_in[0].actual_xfer_len); + } + break; + case 0: + /*!< Set */ + switch (usb_dc_cfg.setup.bRequest) { + case USB_REQUEST_SET_ADDRESS: + /*!< Fill in the equipment address */ + CH58x_USBFS_DEV->USB_DEV_AD = (CH58x_USBFS_DEV->USB_DEV_AD & RB_UDA_GP_BIT) | usb_dc_cfg.address; + /** + * In the state phase after setting the address, the host has sent an in token packet of data1 to take the packet of 0 length, + * Ch58x USB IP needs to manually set the status of the in endpoint to NAK + */ + EPn_SET_TX_NAK(0); + EPn_SET_RX_VALID(0); + break; + default: + /*!< Normal out state phase */ + /** + * The host has sent an in token packet of data1 and taken the packet of 0 length. + * Here, you only need to set the status of the in endpoint to NAK and out endpoint ACK + */ + EPn_SET_TX_NAK(0); + EPn_SET_RX_VALID(0); + break; + } + break; + } + } else { + if (epid == 4) { + CH58x_USBFS_DEV->UEP4_CTRL ^= RB_UEP_T_TOG; + } + EPn_SET_TX_NAK(epid); + if (usb_dc_cfg.ep_in[epid].xfer_len > usb_dc_cfg.ep_in[epid].mps) { + /*!< Need start in again */ + usb_dc_cfg.ep_in[epid].xfer_buf += usb_dc_cfg.ep_in[epid].mps; + usb_dc_cfg.ep_in[epid].xfer_len -= usb_dc_cfg.ep_in[epid].mps; + usb_dc_cfg.ep_in[epid].actual_xfer_len += usb_dc_cfg.ep_in[epid].mps; + if (usb_dc_cfg.ep_in[epid].xfer_len > usb_dc_cfg.ep_in[epid].mps) { + memcpy(usb_dc_cfg.ep_in[epid].ep_ram_addr, usb_dc_cfg.ep_in[epid].xfer_buf, usb_dc_cfg.ep_in[epid].mps); + } else { + memcpy(usb_dc_cfg.ep_in[epid].ep_ram_addr, usb_dc_cfg.ep_in[epid].xfer_buf, usb_dc_cfg.ep_in[epid].xfer_len); + } + if (usb_dc_cfg.ep_in[epid].eptype != USB_ENDPOINT_TYPE_ISOCHRONOUS) { + EPn_SET_TX_VALID(epid); + } else { + EPn_SET_TX_ISO_VALID(epid); + } + } else { + usb_dc_cfg.ep_in[epid].actual_xfer_len += usb_dc_cfg.ep_in[epid].xfer_len; + usb_dc_cfg.ep_in[epid].xfer_len = 0; + usbd_event_ep_in_complete_handler(0, epid | 0x80, usb_dc_cfg.ep_in[epid].actual_xfer_len); + } + } + break; + case UIS_TOKEN_OUT: + if (epid == 0) { + /*!< ep0 out */ + CH58x_USBFS_DEV->UEP0_CTRL ^= RB_UEP_R_TOG; + uint32_t read_count = EPn_GET_RX_LEN(0); + memcpy(usb_dc_cfg.ep_out[epid].xfer_buf, usb_dc_cfg.ep_out[epid].ep_ram_addr, read_count); + + usb_dc_cfg.ep_out[0].actual_xfer_len += read_count; + usb_dc_cfg.ep_out[0].xfer_len -= read_count; + usbd_event_ep_out_complete_handler(0, 0x00, usb_dc_cfg.ep_out[0].actual_xfer_len); + if (read_count == 0) { + /*!< Out status, start reading setup */ + EPn_SET_RX_VALID(0); + } + } else { + if ((CH58x_USBFS_DEV->USB_INT_ST) & RB_UIS_TOG_OK) { + EPn_SET_RX_NAK(epid); + if (epid == 4) { + CH58x_USBFS_DEV->UEP4_CTRL ^= RB_UEP_R_TOG; + } + uint32_t read_count = EPn_GET_RX_LEN(epid); + memcpy(usb_dc_cfg.ep_out[epid].xfer_buf, usb_dc_cfg.ep_out[epid].ep_ram_addr, read_count); + usb_dc_cfg.ep_out[epid].xfer_buf += read_count; + usb_dc_cfg.ep_out[epid].actual_xfer_len += read_count; + usb_dc_cfg.ep_out[epid].xfer_len -= read_count; + + if ((read_count < usb_dc_cfg.ep_out[epid].mps) || (usb_dc_cfg.ep_out[epid].xfer_len == 0)) { + + usbd_event_ep_out_complete_handler(0, ((epid)&0x7f), usb_dc_cfg.ep_out[epid].actual_xfer_len); + } else { + if (usb_dc_cfg.ep_out[epid].eptype != USB_ENDPOINT_TYPE_ISOCHRONOUS) { + EPn_SET_RX_VALID(epid); + } else { + EPn_SET_RX_ISO_VALID(epid); + } + } + } + } + break; + default: + break; + } + CH58x_USBFS_DEV->USB_INT_FG = RB_UIF_TRANSFER; + } + + if (CH58x_USBFS_DEV->USB_INT_ST & RB_UIS_SETUP_ACT) { + /*!< Setup */ + /** + * Setup the device must respond with ACK, and the next data phase is DATA1 + * If it is sent, the data1 packet will be sent. + * If it is received, the data1 packet is expected to be received. + * If it is in, the host will send the data1 out packet to complete the status phase after the in completes. + * If it is out, the host will send the data1 in packet to complete the status phase after the out completes. + */ + CH58x_USBFS_DEV->UEP0_CTRL = RB_UEP_R_TOG | RB_UEP_T_TOG | UEP_T_RES_NAK; + /*!< get setup packet */ + usb_dc_cfg.setup = GET_SETUP_PACKET(usb_dc_cfg.ep_out[0].ep_ram_addr); + if (usb_dc_cfg.setup.bmRequestType >> USB_REQUEST_DIR_SHIFT == 0) { + /** + * Ep0 The next in must be the status stage. + * The device must reply to the host data 0 length packet. + * Here, set the transmission length to 0 and the transmission status to ACK, + * and wait for the host to send the in token to retrieve + */ + EPn_SET_TX_LEN(0, 0); + EPn_SET_TX_VALID(0); + } + EPn_SET_RX_NAK(0); + usbd_event_ep0_setup_complete_handler(0, (uint8_t *)&(usb_dc_cfg.setup)); + CH58x_USBFS_DEV->USB_INT_FG = RB_UIF_TRANSFER; + } + } else if (intflag & RB_UIF_BUS_RST) { + /*!< Reset */ + CH58x_USBFS_DEV->USB_DEV_AD = 0; + usbd_event_reset_handler(0); + /*!< Set ep0 rx vaild to start receive setup packet */ + EPn_SET_RX_VALID(0); + CH58x_USBFS_DEV->USB_INT_FG = RB_UIF_BUS_RST; + } else if (intflag & RB_UIF_SUSPEND) { + if (CH58x_USBFS_DEV->USB_MIS_ST & RB_UMS_SUSPEND) { + /*!< Suspend */ + } else { + /*!< Wake up */ + } + CH58x_USBFS_DEV->USB_INT_FG = RB_UIF_SUSPEND; + } else { + CH58x_USBFS_DEV->USB_INT_FG = intflag; + } +} diff --git a/Code/DAP_X033/DAP/CherryUSB/port/ch32/usb_ch58x_usbfs_reg.h b/Code/DAP_X033/DAP/CherryUSB/port/ch32/usb_ch58x_usbfs_reg.h new file mode 100644 index 0000000..93d87d1 --- /dev/null +++ b/Code/DAP_X033/DAP/CherryUSB/port/ch32/usb_ch58x_usbfs_reg.h @@ -0,0 +1,244 @@ +#pragma once + +#define __IO volatile +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define RB_UC_HOST_MODE 0x80 // enable USB host mode: 0=device mode, 1=host mode +#define RB_UC_LOW_SPEED 0x40 // enable USB low speed: 0=12Mbps, 1=1.5Mbps +#define RB_UC_DEV_PU_EN 0x20 // USB device enable and internal pullup resistance enable +#define RB_UC_SYS_CTRL1 0x20 // USB system control high bit +#define RB_UC_SYS_CTRL0 0x10 // USB system control low bit +#define MASK_UC_SYS_CTRL 0x30 // bit mask of USB system control +#define RB_UC_INT_BUSY 0x08 // enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid +#define RB_UC_RESET_SIE 0x04 // force reset USB SIE, need software clear +#define RB_UC_CLR_ALL 0x02 // force clear FIFO and count of USB +#define RB_UC_DMA_EN 0x01 // DMA enable and DMA interrupt enable for USB + +#define RB_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define RB_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define RB_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define RB_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed +#define RB_UD_GP_BIT 0x02 // general purpose bit +#define RB_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable + +#define RB_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define RB_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define RB_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define RB_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed +#define RB_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset +#define RB_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached + +#define RB_UIE_DEV_SOF 0x80 // enable interrupt for SOF received for USB device mode +#define RB_UIE_DEV_NAK 0x40 // enable interrupt for NAK responded for USB device mode +#define RB_UIE_FIFO_OV 0x10 // enable interrupt for FIFO overflow +#define RB_UIE_HST_SOF 0x08 // enable interrupt for host SOF timer action for USB host mode +#define RB_UIE_SUSPEND 0x04 // enable interrupt for USB suspend or resume event +#define RB_UIE_TRANSFER 0x02 // enable interrupt for USB transfer completion +#define RB_UIE_DETECT 0x01 // enable interrupt for USB device detected event for USB host mode +#define RB_UIE_BUS_RST 0x01 // enable interrupt for USB bus reset event for USB device mode + +#define RB_UDA_GP_BIT 0x80 // general purpose bit +#define MASK_USB_ADDR 0x7F // bit mask for USB device address + +#define RB_UMS_SOF_PRES 0x80 // RO, indicate host SOF timer presage status +#define RB_UMS_SOF_ACT 0x40 // RO, indicate host SOF timer action status for USB host +#define RB_UMS_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define RB_UMS_R_FIFO_RDY 0x10 // RO, indicate USB receiving FIFO ready status (not empty) +#define RB_UMS_BUS_RESET 0x08 // RO, indicate USB bus reset status +#define RB_UMS_SUSPEND 0x04 // RO, indicate USB suspend status +#define RB_UMS_DM_LEVEL 0x02 // RO, indicate UDM level saved at device attached to USB host +#define RB_UMS_DEV_ATTACH 0x01 // RO, indicate device attached status on USB host + +#define RB_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received +#define RB_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define RB_U_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define RB_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear +#define RB_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear +#define RB_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear +#define RB_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear +#define RB_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear +#define RB_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear + +#define RB_UIS_SETUP_ACT 0x80 // RO, indicate SETUP token & 8 bytes setup request received for USB device mode +#define RB_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define RB_UIS_TOKEN1 0x20 // RO, current token PID code bit 1 received for USB device mode +#define RB_UIS_TOKEN0 0x10 // RO, current token PID code bit 0 received for USB device mode +#define MASK_UIS_TOKEN 0x30 // RO, bit mask of current token PID code received for USB device mode +#define UIS_TOKEN_OUT 0x00 +#define UIS_TOKEN_SOF 0x10 +#define UIS_TOKEN_IN 0x20 +#define UIS_TOKEN_SETUP 0x30 + +#define MASK_UIS_ENDP 0x0F // RO, bit mask of current transfer endpoint number for USB device mode +#define MASK_UIS_H_RES 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received + +#define R8_USB_RX_LEN (*((uint8_t *)0x40008008)) // USB receiving length +#define RB_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT) +#define RB_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN) +#define RB_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1 + +#define RB_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT) +#define RB_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN) + +#define RB_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT) +#define RB_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN) +#define RB_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3 +#define RB_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT) +#define RB_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN) +#define RB_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2 + +#define RB_UEP7_RX_EN 0x20 // enable USB endpoint 7 receiving (OUT) +#define RB_UEP7_TX_EN 0x10 // enable USB endpoint 7 transmittal (IN) +#define RB_UEP6_RX_EN 0x08 // enable USB endpoint 6 receiving (OUT) +#define RB_UEP6_TX_EN 0x04 // enable USB endpoint 6 transmittal (IN) +#define RB_UEP5_RX_EN 0x02 // enable USB endpoint 5 receiving (OUT) +#define RB_UEP5_TX_EN 0x01 // enable USB endpoint 5 transmittal (IN) + +#define RB_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal +#define RB_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint + +#define RB_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving +#define RB_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint + +#define RB_UEP_R_TOG 0x80 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 +#define RB_UEP_T_TOG 0x40 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 +#define RB_UEP_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define RB_UEP_R_RES1 0x08 // handshake response type high bit for USB endpoint X receiving (OUT) +#define RB_UEP_R_RES0 0x04 // handshake response type low bit for USB endpoint X receiving (OUT) +#define MASK_UEP_R_RES 0x0C // bit mask of handshake response type for USB endpoint X receiving (OUT) +#define UEP_R_RES_ACK 0x00 +#define UEP_R_RES_TOUT 0x04 +#define UEP_R_RES_NAK 0x08 +#define UEP_R_RES_STALL 0x0C + +#define RB_UEP_T_RES1 0x02 // handshake response type high bit for USB endpoint X transmittal (IN) +#define RB_UEP_T_RES0 0x01 // handshake response type low bit for USB endpoint X transmittal (IN) +#define MASK_UEP_T_RES 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN) +#define UEP_T_RES_ACK 0x00 +#define UEP_T_RES_TOUT 0x01 +#define UEP_T_RES_NAK 0x02 +#define UEP_T_RES_STALL 0x03 + +#define RB_UH_PRE_PID_EN 0x80 // USB host PRE PID enable for low speed device via hub +#define RB_UH_SOF_EN 0x40 // USB host automatic SOF enable + +#define R8_UH_EP_PID R8_UEP2_T_LEN // host endpoint and PID +#define MASK_UH_TOKEN 0xF0 // bit mask of token PID for USB host transfer +#define MASK_UH_ENDP 0x0F // bit mask of endpoint number for USB host transfer + +#define R8_UH_RX_CTRL R8_UEP2_CTRL // host receiver endpoint control +#define RB_UH_R_TOG 0x80 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 +#define RB_UH_R_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define RB_UH_R_RES 0x04 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions + +#define R8_UH_TX_LEN R8_UEP3_T_LEN // host transmittal endpoint transmittal length + +#define RB_UH_T_TOG 0x40 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1 +#define RB_UH_T_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define RB_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions + +#define R16_PIN_ANALOG_IE (*((uint16_t *)0x4000101A)) // RW, analog pin enable and digital input disable +#define RB_PIN_USB_IE 0x80 // RW, USB analog I/O enable: 0=analog I/O disable, 1=analog I/O enable +#define RB_PIN_USB_DP_PU 0x40 // RW, USB UDP internal pullup resistance enable: 0=enable/disable by RB_UC_DEV_PU_EN, 1=enable pullup, replace RB_UC_DEV_PU_EN under sleep mode +#define RB_PIN_USB2_IE 0x20 // RW, USB2 analog I/O enable: 0=analog I/O disable, 1=analog I/O enable +#define RB_PIN_USB2_DP_PU 0x10 // RW, USB2 UDP internal pullup resistance enable: 0=enable/disable by RB_UC_DEV_PU_EN, 1=enable pullup, replace RB_UC_DEV_PU_EN under sleep mode +/*!< USB Regs */ +typedef struct +{ + __IO uint8_t USB_CTRL; /*!< 0x40008000 */ + union { + __IO uint8_t UDEV_CTRL; /*!< 0x40008001 */ + __IO uint8_t UHOST_CTRL; /*!< 0x40008001 */ + }; + __IO uint8_t USB_INT_EN; /*!< 0x40008002 */ + __IO uint8_t USB_DEV_AD; /*!< 0x40008003 */ + __IO uint8_t USB_STATUS0; /*!< 0x40008004 */ + __IO uint8_t USB_MIS_ST; /*!< 0x40008005 */ + __IO uint8_t USB_INT_FG; /*!< 0x40008006 */ + __IO uint8_t USB_INT_ST; /*!< 0x40008007 */ + __IO uint8_t USB_RX_LEN; /*!< 0x40008008 */ + __IO uint8_t Reserve1; /*!< 0x40008009 */ + __IO uint8_t Reserve2; /*!< 0x4000800a */ + __IO uint8_t Reserve3; /*!< 0x4000800b */ + __IO uint8_t UEP4_1_MOD; /*!< 0x4000800c */ + union { + __IO uint8_t UEP2_3_MOD; /*!< 0x4000800d */ + __IO uint8_t UH_EP_MOD; /*!< 0x4000800d */ + }; + __IO uint8_t UEP567_MOD; /*!< 0x4000800e */ + __IO uint8_t Reserve4; /*!< 0x4000800f */ + __IO uint16_t UEP0_DMA; /*!< 0x40008010 */ + __IO uint16_t Reserve5; /*!< 0x40008012 */ + __IO uint16_t UEP1_DMA; /*!< 0x40008014 */ + __IO uint16_t Reserve6; /*!< 0x40008016 */ + union { + __IO uint16_t UEP2_DMA; /*!< 0x40008018 */ + __IO uint16_t UH_RX_DMA; /*!< 0x40008018 */ + }; + __IO uint16_t Reserve7; /*!< 0x4000801a */ + union { + __IO uint16_t UEP3_DMA; /*!< 0x4000801c */ + __IO uint16_t UH_TX_DMA; /*!< 0x4000801c */ + }; + __IO uint16_t Reserve8; /*!< 0x4000801e */ + __IO uint8_t UEP0_T_LEN; /*!< 0x40008020 */ + __IO uint8_t Reserve9; /*!< 0x40008021 */ + __IO uint8_t UEP0_CTRL; /*!< 0x40008022 */ + __IO uint8_t Reserve10; /*!< 0x40008023 */ + __IO uint8_t UEP1_T_LEN; /*!< 0x40008024 */ + __IO uint8_t Reserve11; /*!< 0x40008025 */ + union { + __IO uint8_t UEP1_CTRL; /*!< 0x40008026 */ + __IO uint8_t UH_SETUP; /*!< 0x40008026 */ + }; + __IO uint8_t Reserve12; /*!< 0x40008027 */ + union { + __IO uint8_t UEP2_T_LEN; /*!< 0x40008028 */ + __IO uint8_t UH_EP_PID; /*!< 0x40008028 */ + }; + __IO uint8_t Reserve13; /*!< 0x40008029 */ + union { + __IO uint8_t UEP2_CTRL; /*!< 0x4000802a */ + __IO uint8_t UH_RX_CTRL; /*!< 0x4000802a */ + }; + __IO uint8_t Reserve14; /*!< 0x4000802b */ + union { + __IO uint8_t UEP3_T_LEN; /*!< 0x4000802c */ + __IO uint8_t UH_TX_LEN; /*!< 0x4000802c */ + }; + __IO uint8_t Reserve15; /*!< 0x4000802d */ + union { + __IO uint8_t UEP3_CTRL; /*!< 0x4000802e */ + __IO uint8_t UH_TX_CTRL; /*!< 0x4000802e */ + }; + __IO uint8_t Reserve16; /*!< 0x4000802f */ + __IO uint8_t UEP4_T_LEN; /*!< 0x40008030 */ + __IO uint8_t Reserve17; /*!< 0x40008031 */ + __IO uint8_t UEP4_CTRL; /*!< 0x40008032 */ + __IO uint8_t Reserve18[33]; /*!< 0x40008033 */ + __IO uint16_t UEP5_DMA; /*!< 0x40008054 */ + __IO uint16_t Reserve19; /*!< 0x40008056 */ + __IO uint16_t UEP6_DMA; /*!< 0x40008058 */ + __IO uint16_t Reserve20; /*!< 0x4000805a */ + __IO uint16_t UEP7_DMA; /*!< 0x4000805c */ + __IO uint8_t Reserve21[6]; /*!< 0x4000805e */ + __IO uint8_t UEP5_T_LEN; /*!< 0x40008064 */ + __IO uint8_t Reserve22; /*!< 0x40008065 */ + __IO uint8_t UEP5_CTRL; /*!< 0x40008066 */ + __IO uint8_t Reserve23; /*!< 0x40008067 */ + __IO uint8_t UEP6_T_LEN; /*!< 0x40008068 */ + __IO uint8_t Reserve24; /*!< 0x40008069 */ + __IO uint8_t UEP6_CTRL; /*!< 0x4000806a */ + __IO uint8_t Reserve25; /*!< 0x4000806b */ + __IO uint8_t UEP7_T_LEN; /*!< 0x4000806c */ + __IO uint8_t Reserve26; /*!< 0x4000806d */ + __IO uint8_t UEP7_CTRL; /*!< 0x4000806e */ +} USB_FS_TypeDef; + +#ifdef __cplusplus +} +#endif diff --git a/Code/DAP_X033/DAP/CherryUSB/usb_config.h b/Code/DAP_X033/DAP/CherryUSB/usb_config.h new file mode 100644 index 0000000..ba46eb9 --- /dev/null +++ b/Code/DAP_X033/DAP/CherryUSB/usb_config.h @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef CHERRYUSB_CONFIG_H +#define CHERRYUSB_CONFIG_H + +#define CHERRYUSB_VERSION 0x010200 +#define CHERRYUSB_VERSION_STR "v1.2.0" + +/* ================ USB common Configuration ================ */ + +#define CONFIG_USB_PRINTF(...) //printf(__VA_ARGS__) + +#define usb_malloc(size) malloc(size) +#define usb_free(ptr) free(ptr) + +#ifndef CONFIG_USB_DBG_LEVEL +#define CONFIG_USB_DBG_LEVEL USB_DBG_ERROR +#endif + +/* Enable print with color */ +#define CONFIG_USB_PRINTF_COLOR_ENABLE + +/* data align size when use dma */ +#ifndef CONFIG_USB_ALIGN_SIZE +#define CONFIG_USB_ALIGN_SIZE 4 +#endif + +/* attribute data into no cache ram */ +#define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable"))) + +/* ================= USB Device Stack Configuration ================ */ + +#define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip + +/* Ep0 max transfer buffer, specially for receiving data from ep0 out */ +#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 256 + +/* Setup packet log for debug */ +// #define CONFIG_USBDEV_SETUP_LOG_PRINT + +/* Check if the input descriptor is correct */ +// #define CONFIG_USBDEV_DESC_CHECK + +/* Enable test mode */ +// #define CONFIG_USBDEV_TEST_MODE + +#ifndef CONFIG_USBDEV_MSC_MAX_LUN +#define CONFIG_USBDEV_MSC_MAX_LUN 1 +#endif + +#ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE +#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512 +#endif + +#ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING +#define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING +#define CONFIG_USBDEV_MSC_PRODUCT_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_VERSION_STRING +#define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" +#endif + +// #define CONFIG_USBDEV_MSC_THREAD + +#ifndef CONFIG_USBDEV_MSC_PRIO +#define CONFIG_USBDEV_MSC_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_MSC_STACKSIZE +#define CONFIG_USBDEV_MSC_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE +#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE +#define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1536 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID +#define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC +#define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB" +#endif + +#define CONFIG_USBDEV_RNDIS_USING_LWIP + +/* ================ USB HOST Stack Configuration ================== */ + +#define CONFIG_USBHOST_MAX_BUS 1 +#define CONFIG_USBHOST_MAX_RHPORTS 1 +#define CONFIG_USBHOST_MAX_EXTHUBS 1 +#define CONFIG_USBHOST_MAX_EHPORTS 4 +#define CONFIG_USBHOST_MAX_INTERFACES 8 +#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8 +#define CONFIG_USBHOST_MAX_ENDPOINTS 4 + +#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4 +#define CONFIG_USBHOST_MAX_HID_CLASS 4 +#define CONFIG_USBHOST_MAX_MSC_CLASS 2 +#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1 +#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1 + +#define CONFIG_USBHOST_DEV_NAMELEN 16 + +#ifndef CONFIG_USBHOST_PSC_PRIO +#define CONFIG_USBHOST_PSC_PRIO 0 +#endif +#ifndef CONFIG_USBHOST_PSC_STACKSIZE +#define CONFIG_USBHOST_PSC_STACKSIZE 2048 +#endif + +//#define CONFIG_USBHOST_GET_STRING_DESC + +// #define CONFIG_USBHOST_MSOS_ENABLE +#define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00 + +/* Ep0 max transfer buffer */ +#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 + +#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT +#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 +#endif + +#ifndef CONFIG_USBHOST_MSC_TIMEOUT +#define CONFIG_USBHOST_MSC_TIMEOUT 5000 +#endif + +#define CONFIG_USBHOST_BLUETOOTH_HCI_H4 +// #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG + +#ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE +#define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048 +#endif +#ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE +#define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048 +#endif + +/* ================ USB Device Port Configuration ================*/ + +#ifndef CONFIG_USBDEV_EP_NUM +#define CONFIG_USBDEV_EP_NUM 8 +#endif + +/* ================ USB Host Port Configuration ==================*/ + +// #define CONFIG_USBHOST_PIPE_NUM 10 + +/* ================ EHCI Configuration ================ */ + +#define CONFIG_USB_EHCI_HCCR_OFFSET (0x0) +#define CONFIG_USB_EHCI_HCOR_OFFSET (0x10) +#define CONFIG_USB_EHCI_FRAME_LIST_SIZE 1024 +// #define CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE +// #define CONFIG_USB_EHCI_CONFIGFLAG +// #define CONFIG_USB_EHCI_PORT_POWER +// #define CONFIG_USB_EHCI_PRINT_HW_PARAM + +#endif diff --git a/Code/DAP_X033/DAP/DAP_Core/DAP.c b/Code/DAP_X033/DAP/DAP_Core/DAP.c new file mode 100644 index 0000000..0813d2c --- /dev/null +++ b/Code/DAP_X033/DAP/DAP_Core/DAP.c @@ -0,0 +1,1814 @@ +/* + * Copyright (c) 2013-2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 26. April 2022 + * $Revision: V2.1.1 + * + * Project: CMSIS-DAP Source + * Title: DAP.c CMSIS-DAP Commands + * + *---------------------------------------------------------------------------*/ + +#include +#include "DAP_config.h" +#include "DAP.h" + + +#if (DAP_PACKET_SIZE < 64U) +#error "Minimum Packet Size is 64!" +#endif +#if (DAP_PACKET_SIZE > 32768U) +#error "Maximum Packet Size is 32768!" +#endif +#if (DAP_PACKET_COUNT < 1U) +#error "Minimum Packet Count is 1!" +#endif +#if (DAP_PACKET_COUNT > 255U) +#error "Maximum Packet Count is 255!" +#endif + + +// Clock Macros +#define MAX_SWJ_CLOCK(delay_cycles) \ + ((CPU_CLOCK/2U) / (IO_PORT_WRITE_CYCLES + delay_cycles)) + + + DAP_Data_t DAP_Data; // DAP Data +volatile uint8_t DAP_TransferAbort; // Transfer Abort Flag + + +static const char DAP_FW_Ver [] = DAP_FW_VER; + + +// Common clock delay calculation routine +// clock: requested SWJ frequency in Hertz +static void Set_Clock_Delay(uint32_t clock) { + uint32_t delay; + + if (clock >= MAX_SWJ_CLOCK(DELAY_FAST_CYCLES)) { + DAP_Data.fast_clock = 1U; + DAP_Data.clock_delay = 1U; + } else { + DAP_Data.fast_clock = 0U; + + delay = ((CPU_CLOCK/2U) + (clock - 1U)) / clock; + if (delay > IO_PORT_WRITE_CYCLES) { + delay -= IO_PORT_WRITE_CYCLES; + delay = (delay + (DELAY_SLOW_CYCLES - 1U)) / DELAY_SLOW_CYCLES; + } else { + delay = 1U; + } + + DAP_Data.clock_delay = delay; + } +} + + +// Get DAP Information +// id: info identifier +// info: pointer to info data +// return: number of bytes in info data +static uint8_t DAP_Info(uint8_t id, uint8_t *info) { + uint8_t length = 0U; + + switch (id) { + case DAP_ID_VENDOR: + length = DAP_GetVendorString((char *)info); + break; + case DAP_ID_PRODUCT: + length = DAP_GetProductString((char *)info); + break; + case DAP_ID_SER_NUM: + length = DAP_GetSerNumString((char *)info); + break; + case DAP_ID_DAP_FW_VER: + length = (uint8_t)sizeof(DAP_FW_Ver); + memcpy(info, DAP_FW_Ver, length); + break; + case DAP_ID_DEVICE_VENDOR: + length = DAP_GetTargetDeviceVendorString((char *)info); + break; + case DAP_ID_DEVICE_NAME: + length = DAP_GetTargetDeviceNameString((char *)info); + break; + case DAP_ID_BOARD_VENDOR: + length = DAP_GetTargetBoardVendorString((char *)info); + break; + case DAP_ID_BOARD_NAME: + length = DAP_GetTargetBoardNameString((char *)info); + break; + case DAP_ID_PRODUCT_FW_VER: + length = DAP_GetProductFirmwareVersionString((char *)info); + break; + case DAP_ID_CAPABILITIES: + info[0] = ((DAP_SWD != 0) ? (1U << 0) : 0U) | + ((DAP_JTAG != 0) ? (1U << 1) : 0U) | + ((SWO_UART != 0) ? (1U << 2) : 0U) | + ((SWO_MANCHESTER != 0) ? (1U << 3) : 0U) | + /* Atomic Commands */ (1U << 4) | + ((TIMESTAMP_CLOCK != 0U) ? (1U << 5) : 0U) | + ((SWO_STREAM != 0U) ? (1U << 6) : 0U) | + ((DAP_UART != 0U) ? (1U << 7) : 0U); + + info[1] = ((DAP_UART_USB_COM_PORT != 0) ? (1U << 0) : 0U); + length = 2U; + break; + case DAP_ID_TIMESTAMP_CLOCK: +#if (TIMESTAMP_CLOCK != 0U) + info[0] = (uint8_t)(TIMESTAMP_CLOCK >> 0); + info[1] = (uint8_t)(TIMESTAMP_CLOCK >> 8); + info[2] = (uint8_t)(TIMESTAMP_CLOCK >> 16); + info[3] = (uint8_t)(TIMESTAMP_CLOCK >> 24); + length = 4U; +#endif + break; + case DAP_ID_UART_RX_BUFFER_SIZE: +#if (DAP_UART != 0) + info[0] = (uint8_t)(DAP_UART_RX_BUFFER_SIZE >> 0); + info[1] = (uint8_t)(DAP_UART_RX_BUFFER_SIZE >> 8); + info[2] = (uint8_t)(DAP_UART_RX_BUFFER_SIZE >> 16); + info[3] = (uint8_t)(DAP_UART_RX_BUFFER_SIZE >> 24); + length = 4U; +#endif + break; + case DAP_ID_UART_TX_BUFFER_SIZE: +#if (DAP_UART != 0) + info[0] = (uint8_t)(DAP_UART_TX_BUFFER_SIZE >> 0); + info[1] = (uint8_t)(DAP_UART_TX_BUFFER_SIZE >> 8); + info[2] = (uint8_t)(DAP_UART_TX_BUFFER_SIZE >> 16); + info[3] = (uint8_t)(DAP_UART_TX_BUFFER_SIZE >> 24); + length = 4U; +#endif + break; + case DAP_ID_SWO_BUFFER_SIZE: +#if ((SWO_UART != 0) || (SWO_MANCHESTER != 0)) + info[0] = (uint8_t)(SWO_BUFFER_SIZE >> 0); + info[1] = (uint8_t)(SWO_BUFFER_SIZE >> 8); + info[2] = (uint8_t)(SWO_BUFFER_SIZE >> 16); + info[3] = (uint8_t)(SWO_BUFFER_SIZE >> 24); + length = 4U; +#endif + break; + case DAP_ID_PACKET_SIZE: + info[0] = (uint8_t)(DAP_PACKET_SIZE >> 0); + info[1] = (uint8_t)(DAP_PACKET_SIZE >> 8); + length = 2U; + break; + case DAP_ID_PACKET_COUNT: + info[0] = DAP_PACKET_COUNT; + length = 1U; + break; + default: + break; + } + + return (length); +} + + +// Delay for specified time +// delay: delay time in ms +void Delayms(uint32_t delay) { + delay *= ((CPU_CLOCK/1000U) + (DELAY_SLOW_CYCLES-1U)) / DELAY_SLOW_CYCLES; + PIN_DELAY_SLOW(delay); +} + + +// Process Delay command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_Delay(const uint8_t *request, uint8_t *response) { + uint32_t delay; + + delay = (uint32_t)(*(request+0)) | + (uint32_t)(*(request+1) << 8); + delay *= ((CPU_CLOCK/1000000U) + (DELAY_SLOW_CYCLES-1U)) / DELAY_SLOW_CYCLES; + + PIN_DELAY_SLOW(delay); + + *response = DAP_OK; + return ((2U << 16) | 1U); +} + + +// Process Host Status command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_HostStatus(const uint8_t *request, uint8_t *response) { + + switch (*request) { + case DAP_DEBUGGER_CONNECTED: + LED_CONNECTED_OUT((*(request+1) & 1U)); + break; + case DAP_TARGET_RUNNING: + LED_RUNNING_OUT((*(request+1) & 1U)); + break; + default: + *response = DAP_ERROR; + return ((2U << 16) | 1U); + } + + *response = DAP_OK; + return ((2U << 16) | 1U); +} + + +// Process Connect command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_Connect(const uint8_t *request, uint8_t *response) { + uint32_t port; + + if (*request == DAP_PORT_AUTODETECT) { + port = DAP_DEFAULT_PORT; + } else { + port = *request; + } + + switch (port) { +#if (DAP_SWD != 0) + case DAP_PORT_SWD: + DAP_Data.debug_port = DAP_PORT_SWD; + PORT_SWD_SETUP(); + break; +#endif +#if (DAP_JTAG != 0) + case DAP_PORT_JTAG: + DAP_Data.debug_port = DAP_PORT_JTAG; + PORT_JTAG_SETUP(); + break; +#endif + default: + port = DAP_PORT_DISABLED; + break; + } + + *response = (uint8_t)port; + return ((1U << 16) | 1U); +} + + +// Process Disconnect command and prepare response +// response: pointer to response data +// return: number of bytes in response +static uint32_t DAP_Disconnect(uint8_t *response) { + + DAP_Data.debug_port = DAP_PORT_DISABLED; + PORT_OFF(); + + *response = DAP_OK; + return (1U); +} + + +// Process Reset Target command and prepare response +// response: pointer to response data +// return: number of bytes in response +static uint32_t DAP_ResetTarget(uint8_t *response) { + + *(response+1) = RESET_TARGET(); + *(response+0) = DAP_OK; + return (2U); +} + + +// Process SWJ Pins command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_SWJ_Pins(const uint8_t *request, uint8_t *response) { +#if ((DAP_SWD != 0) || (DAP_JTAG != 0)) + uint32_t value; + uint32_t select; + uint32_t wait; + uint32_t timestamp; + + value = (uint32_t) *(request+0); + select = (uint32_t) *(request+1); + wait = (uint32_t)(*(request+2) << 0) | + (uint32_t)(*(request+3) << 8) | + (uint32_t)(*(request+4) << 16) | + (uint32_t)(*(request+5) << 24); + + if ((select & (1U << DAP_SWJ_SWCLK_TCK)) != 0U) { + if ((value & (1U << DAP_SWJ_SWCLK_TCK)) != 0U) { + PIN_SWCLK_TCK_SET(); + } else { + PIN_SWCLK_TCK_CLR(); + } + } + if ((select & (1U << DAP_SWJ_SWDIO_TMS)) != 0U) { + if ((value & (1U << DAP_SWJ_SWDIO_TMS)) != 0U) { + PIN_SWDIO_TMS_SET(); + } else { + PIN_SWDIO_TMS_CLR(); + } + } + if ((select & (1U << DAP_SWJ_TDI)) != 0U) { + PIN_TDI_OUT(value >> DAP_SWJ_TDI); + } + if ((select & (1U << DAP_SWJ_nTRST)) != 0U) { + PIN_nTRST_OUT(value >> DAP_SWJ_nTRST); + } + if ((select & (1U << DAP_SWJ_nRESET)) != 0U){ + PIN_nRESET_OUT(value >> DAP_SWJ_nRESET); + } + + if (wait != 0U) { +#if (TIMESTAMP_CLOCK != 0U) + if (wait > 3000000U) { + wait = 3000000U; + } +#if (TIMESTAMP_CLOCK >= 1000000U) + wait *= TIMESTAMP_CLOCK / 1000000U; +#else + wait /= 1000000U / TIMESTAMP_CLOCK; +#endif +#else + wait = 1U; +#endif + timestamp = TIMESTAMP_GET(); + do { + if ((select & (1U << DAP_SWJ_SWCLK_TCK)) != 0U) { + if ((value >> DAP_SWJ_SWCLK_TCK) ^ PIN_SWCLK_TCK_IN()) { + continue; + } + } + if ((select & (1U << DAP_SWJ_SWDIO_TMS)) != 0U) { + if ((value >> DAP_SWJ_SWDIO_TMS) ^ PIN_SWDIO_TMS_IN()) { + continue; + } + } + if ((select & (1U << DAP_SWJ_TDI)) != 0U) { + if ((value >> DAP_SWJ_TDI) ^ PIN_TDI_IN()) { + continue; + } + } + if ((select & (1U << DAP_SWJ_nTRST)) != 0U) { + if ((value >> DAP_SWJ_nTRST) ^ PIN_nTRST_IN()) { + continue; + } + } + if ((select & (1U << DAP_SWJ_nRESET)) != 0U) { + if ((value >> DAP_SWJ_nRESET) ^ PIN_nRESET_IN()) { + continue; + } + } + break; + } while ((TIMESTAMP_GET() - timestamp) < wait); + } + + value = (PIN_SWCLK_TCK_IN() << DAP_SWJ_SWCLK_TCK) | + (PIN_SWDIO_TMS_IN() << DAP_SWJ_SWDIO_TMS) | + (PIN_TDI_IN() << DAP_SWJ_TDI) | + (PIN_TDO_IN() << DAP_SWJ_TDO) | + (PIN_nTRST_IN() << DAP_SWJ_nTRST) | + (PIN_nRESET_IN() << DAP_SWJ_nRESET); + + *response = (uint8_t)value; +#else + *response = 0U; +#endif + + return ((6U << 16) | 1U); +} + + +// Process SWJ Clock command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_SWJ_Clock(const uint8_t *request, uint8_t *response) { +#if ((DAP_SWD != 0) || (DAP_JTAG != 0)) + uint32_t clock; +// uint32_t delay; + + clock = (uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8) | + (uint32_t)(*(request+2) << 16) | + (uint32_t)(*(request+3) << 24); + + clock *= 10; + + if (clock == 0U) { + *response = DAP_ERROR; + return ((4U << 16) | 1U); + } + + Set_Clock_Delay(clock); + + *response = DAP_OK; +#else + *response = DAP_ERROR; +#endif + + return ((4U << 16) | 1U); +} + + +// Process SWJ Sequence command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_SWJ_Sequence(const uint8_t *request, uint8_t *response) { + uint32_t count; + + count = *request++; + if (count == 0U) { + count = 256U; + } + +#if ((DAP_SWD != 0) || (DAP_JTAG != 0)) + SWJ_Sequence(count, request); + *response = DAP_OK; +#else + *response = DAP_ERROR; +#endif + + count = (count + 7U) >> 3; + + return (((count + 1U) << 16) | 1U); +} + + +// Process SWD Configure command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_SWD_Configure(const uint8_t *request, uint8_t *response) { +#if (DAP_SWD != 0) + uint8_t value; + + value = *request; + DAP_Data.swd_conf.turnaround = (value & 0x03U) + 1U; + DAP_Data.swd_conf.data_phase = (value & 0x04U) ? 1U : 0U; + + *response = DAP_OK; +#else + *response = DAP_ERROR; +#endif + + return ((1U << 16) | 1U); +} + + +// Process SWD Sequence command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_SWD_Sequence(const uint8_t *request, uint8_t *response) { + uint32_t sequence_info; + uint32_t sequence_count; + uint32_t request_count; + uint32_t response_count; + uint32_t count; + +#if (DAP_SWD != 0) + *response++ = DAP_OK; +#else + *response++ = DAP_ERROR; +#endif + request_count = 1U; + response_count = 1U; + + sequence_count = *request++; + while (sequence_count--) { + sequence_info = *request++; + count = sequence_info & SWD_SEQUENCE_CLK; + if (count == 0U) { + count = 64U; + } + count = (count + 7U) / 8U; +#if (DAP_SWD != 0) + if ((sequence_info & SWD_SEQUENCE_DIN) != 0U) { + PIN_SWDIO_OUT_DISABLE(); + } else { + PIN_SWDIO_OUT_ENABLE(); + } + SWD_Sequence(sequence_info, request, response); + if (sequence_count == 0U) { + PIN_SWDIO_OUT_ENABLE(); + } +#endif + if ((sequence_info & SWD_SEQUENCE_DIN) != 0U) { + request_count++; +#if (DAP_SWD != 0) + response += count; + response_count += count; +#endif + } else { + request += count; + request_count += count + 1U; + } + } + + return ((request_count << 16) | response_count); +} + + +// Process JTAG Sequence command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_JTAG_Sequence(const uint8_t *request, uint8_t *response) { + uint32_t sequence_info; + uint32_t sequence_count; + uint32_t request_count; + uint32_t response_count; + uint32_t count; + +#if (DAP_JTAG != 0) + *response++ = DAP_OK; +#else + *response++ = DAP_ERROR; +#endif + request_count = 1U; + response_count = 1U; + + sequence_count = *request++; + while (sequence_count--) { + sequence_info = *request++; + count = sequence_info & JTAG_SEQUENCE_TCK; + if (count == 0U) { + count = 64U; + } + count = (count + 7U) / 8U; +#if (DAP_JTAG != 0) + JTAG_Sequence(sequence_info, request, response); +#endif + request += count; + request_count += count + 1U; +#if (DAP_JTAG != 0) + if ((sequence_info & JTAG_SEQUENCE_TDO) != 0U) { + response += count; + response_count += count; + } +#endif + } + + return ((request_count << 16) | response_count); +} + + +// Process JTAG Configure command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_JTAG_Configure(const uint8_t *request, uint8_t *response) { + uint32_t count; +#if (DAP_JTAG != 0) + uint32_t length; + uint32_t bits; + uint32_t n; + + count = *request++; + DAP_Data.jtag_dev.count = (uint8_t)count; + + bits = 0U; + for (n = 0U; n < count; n++) { + length = *request++; + DAP_Data.jtag_dev.ir_length[n] = (uint8_t)length; + DAP_Data.jtag_dev.ir_before[n] = (uint16_t)bits; + bits += length; + } + for (n = 0U; n < count; n++) { + bits -= DAP_Data.jtag_dev.ir_length[n]; + DAP_Data.jtag_dev.ir_after[n] = (uint16_t)bits; + } + + *response = DAP_OK; +#else + count = *request; + *response = DAP_ERROR; +#endif + + return (((count + 1U) << 16) | 1U); +} + + +// Process JTAG IDCODE command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_JTAG_IDCode(const uint8_t *request, uint8_t *response) { +#if (DAP_JTAG != 0) + uint32_t data; + + if (DAP_Data.debug_port != DAP_PORT_JTAG) { + goto id_error; + } + + // Device index (JTAP TAP) + DAP_Data.jtag_dev.index = *request; + if (DAP_Data.jtag_dev.index >= DAP_Data.jtag_dev.count) { + goto id_error; + } + + // Select JTAG chain + JTAG_IR(JTAG_IDCODE); + + // Read IDCODE register + data = JTAG_ReadIDCode(); + + // Store Data + *(response+0) = DAP_OK; + *(response+1) = (uint8_t)(data >> 0); + *(response+2) = (uint8_t)(data >> 8); + *(response+3) = (uint8_t)(data >> 16); + *(response+4) = (uint8_t)(data >> 24); + + return ((1U << 16) | 5U); + +id_error: +#endif + *response = DAP_ERROR; + return ((1U << 16) | 1U); +} + + +// Process Transfer Configure command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_TransferConfigure(const uint8_t *request, uint8_t *response) { + + DAP_Data.transfer.idle_cycles = *(request+0); + DAP_Data.transfer.retry_count = (uint16_t) *(request+1) | + (uint16_t)(*(request+2) << 8); + DAP_Data.transfer.match_retry = (uint16_t) *(request+3) | + (uint16_t)(*(request+4) << 8); + + *response = DAP_OK; + return ((5U << 16) | 1U); +} + + +// Process SWD Transfer command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +#if (DAP_SWD != 0) +static uint32_t DAP_SWD_Transfer(const uint8_t *request, uint8_t *response) { + const + uint8_t *request_head; + uint32_t request_count; + uint32_t request_value; + uint8_t *response_head; + uint32_t response_count; + uint32_t response_value; + uint32_t post_read; + uint32_t check_write; + uint32_t match_value; + uint32_t match_retry; + uint32_t retry; + uint32_t data; +#if (TIMESTAMP_CLOCK != 0U) + uint32_t timestamp; +#endif + + request_head = request; + + response_count = 0U; + response_value = 0U; + response_head = response; + response += 2; + + DAP_TransferAbort = 0U; + + post_read = 0U; + check_write = 0U; + + request++; // Ignore DAP index + + request_count = *request++; + + for (; request_count != 0U; request_count--) { + request_value = *request++; + if ((request_value & DAP_TRANSFER_RnW) != 0U) { + // Read register + if (post_read) { + // Read was posted before + retry = DAP_Data.transfer.retry_count; + if ((request_value & (DAP_TRANSFER_APnDP | DAP_TRANSFER_MATCH_VALUE)) == DAP_TRANSFER_APnDP) { + // Read previous AP data and post next AP read + do { + response_value = SWD_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + } else { + // Read previous AP data + do { + response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + post_read = 0U; + } + if (response_value != DAP_TRANSFER_OK) { + break; + } + // Store previous AP data + *response++ = (uint8_t) data; + *response++ = (uint8_t)(data >> 8); + *response++ = (uint8_t)(data >> 16); + *response++ = (uint8_t)(data >> 24); +#if (TIMESTAMP_CLOCK != 0U) + if (post_read) { + // Store Timestamp of next AP read + if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) { + timestamp = DAP_Data.timestamp; + *response++ = (uint8_t) timestamp; + *response++ = (uint8_t)(timestamp >> 8); + *response++ = (uint8_t)(timestamp >> 16); + *response++ = (uint8_t)(timestamp >> 24); + } + } +#endif + } + if ((request_value & DAP_TRANSFER_MATCH_VALUE) != 0U) { + // Read with value match + match_value = (uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8) | + (uint32_t)(*(request+2) << 16) | + (uint32_t)(*(request+3) << 24); + request += 4; + match_retry = DAP_Data.transfer.match_retry; + if ((request_value & DAP_TRANSFER_APnDP) != 0U) { + // Post AP read + retry = DAP_Data.transfer.retry_count; + do { + response_value = SWD_Transfer(request_value, NULL); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } + } + do { + // Read register until its value matches or retry counter expires + retry = DAP_Data.transfer.retry_count; + do { + response_value = SWD_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } + } while (((data & DAP_Data.transfer.match_mask) != match_value) && match_retry-- && !DAP_TransferAbort); + if ((data & DAP_Data.transfer.match_mask) != match_value) { + response_value |= DAP_TRANSFER_MISMATCH; + } + if (response_value != DAP_TRANSFER_OK) { + break; + } + } else { + // Normal read + retry = DAP_Data.transfer.retry_count; + if ((request_value & DAP_TRANSFER_APnDP) != 0U) { + // Read AP register + if (post_read == 0U) { + // Post AP read + do { + response_value = SWD_Transfer(request_value, NULL); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } +#if (TIMESTAMP_CLOCK != 0U) + // Store Timestamp + if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) { + timestamp = DAP_Data.timestamp; + *response++ = (uint8_t) timestamp; + *response++ = (uint8_t)(timestamp >> 8); + *response++ = (uint8_t)(timestamp >> 16); + *response++ = (uint8_t)(timestamp >> 24); + } +#endif + post_read = 1U; + } + } else { + // Read DP register + do { + response_value = SWD_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } +#if (TIMESTAMP_CLOCK != 0U) + // Store Timestamp + if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) { + timestamp = DAP_Data.timestamp; + *response++ = (uint8_t) timestamp; + *response++ = (uint8_t)(timestamp >> 8); + *response++ = (uint8_t)(timestamp >> 16); + *response++ = (uint8_t)(timestamp >> 24); + } +#endif + // Store data + *response++ = (uint8_t) data; + *response++ = (uint8_t)(data >> 8); + *response++ = (uint8_t)(data >> 16); + *response++ = (uint8_t)(data >> 24); + } + } + check_write = 0U; + } else { + // Write register + if (post_read) { + // Read previous data + retry = DAP_Data.transfer.retry_count; + do { + response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } + // Store previous data + *response++ = (uint8_t) data; + *response++ = (uint8_t)(data >> 8); + *response++ = (uint8_t)(data >> 16); + *response++ = (uint8_t)(data >> 24); + post_read = 0U; + } + // Load data + data = (uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8) | + (uint32_t)(*(request+2) << 16) | + (uint32_t)(*(request+3) << 24); + request += 4; + if ((request_value & DAP_TRANSFER_MATCH_MASK) != 0U) { + // Write match mask + DAP_Data.transfer.match_mask = data; + response_value = DAP_TRANSFER_OK; + } else { + // Write DP/AP register + retry = DAP_Data.transfer.retry_count; + do { + response_value = SWD_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } +#if (TIMESTAMP_CLOCK != 0U) + // Store Timestamp + if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) { + timestamp = DAP_Data.timestamp; + *response++ = (uint8_t) timestamp; + *response++ = (uint8_t)(timestamp >> 8); + *response++ = (uint8_t)(timestamp >> 16); + *response++ = (uint8_t)(timestamp >> 24); + } +#endif + check_write = 1U; + } + } + response_count++; + if (DAP_TransferAbort) { + break; + } + } + + for (; request_count != 0U; request_count--) { + // Process canceled requests + request_value = *request++; + if ((request_value & DAP_TRANSFER_RnW) != 0U) { + // Read register + if ((request_value & DAP_TRANSFER_MATCH_VALUE) != 0U) { + // Read with value match + request += 4; + } + } else { + // Write register + request += 4; + } + } + + if (response_value == DAP_TRANSFER_OK) { + if (post_read) { + // Read previous data + retry = DAP_Data.transfer.retry_count; + do { + response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + goto end; + } + // Store previous data + *response++ = (uint8_t) data; + *response++ = (uint8_t)(data >> 8); + *response++ = (uint8_t)(data >> 16); + *response++ = (uint8_t)(data >> 24); + } else if (check_write) { + // Check last write + retry = DAP_Data.transfer.retry_count; + do { + response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, NULL); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + } + } + +end: + *(response_head+0) = (uint8_t)response_count; + *(response_head+1) = (uint8_t)response_value; + + return (((uint32_t)(request - request_head) << 16) | (uint32_t)(response - response_head)); +} +#endif + + +// Process JTAG Transfer command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +#if (DAP_JTAG != 0) +static uint32_t DAP_JTAG_Transfer(const uint8_t *request, uint8_t *response) { + const + uint8_t *request_head; + uint32_t request_count; + uint32_t request_value; + uint32_t request_ir; + uint8_t *response_head; + uint32_t response_count; + uint32_t response_value; + uint32_t post_read; + uint32_t match_value; + uint32_t match_retry; + uint32_t retry; + uint32_t data; + uint32_t ir; +#if (TIMESTAMP_CLOCK != 0U) + uint32_t timestamp; +#endif + + request_head = request; + + response_count = 0U; + response_value = 0U; + response_head = response; + response += 2; + + DAP_TransferAbort = 0U; + + ir = 0U; + post_read = 0U; + + // Device index (JTAP TAP) + DAP_Data.jtag_dev.index = *request++; + if (DAP_Data.jtag_dev.index >= DAP_Data.jtag_dev.count) { + goto end; + } + + request_count = *request++; + + for (; request_count != 0U; request_count--) { + request_value = *request++; + request_ir = (request_value & DAP_TRANSFER_APnDP) ? JTAG_APACC : JTAG_DPACC; + if ((request_value & DAP_TRANSFER_RnW) != 0U) { + // Read register + if (post_read) { + // Read was posted before + retry = DAP_Data.transfer.retry_count; + if ((ir == request_ir) && ((request_value & DAP_TRANSFER_MATCH_VALUE) == 0U)) { + // Read previous data and post next read + do { + response_value = JTAG_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + } else { + // Select JTAG chain + if (ir != JTAG_DPACC) { + ir = JTAG_DPACC; + JTAG_IR(ir); + } + // Read previous data + do { + response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + post_read = 0U; + } + if (response_value != DAP_TRANSFER_OK) { + break; + } + // Store previous data + *response++ = (uint8_t) data; + *response++ = (uint8_t)(data >> 8); + *response++ = (uint8_t)(data >> 16); + *response++ = (uint8_t)(data >> 24); +#if (TIMESTAMP_CLOCK != 0U) + if (post_read) { + // Store Timestamp of next AP read + if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) { + timestamp = DAP_Data.timestamp; + *response++ = (uint8_t) timestamp; + *response++ = (uint8_t)(timestamp >> 8); + *response++ = (uint8_t)(timestamp >> 16); + *response++ = (uint8_t)(timestamp >> 24); + } + } +#endif + } + if ((request_value & DAP_TRANSFER_MATCH_VALUE) != 0U) { + // Read with value match + match_value = (uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8) | + (uint32_t)(*(request+2) << 16) | + (uint32_t)(*(request+3) << 24); + request += 4; + match_retry = DAP_Data.transfer.match_retry; + // Select JTAG chain + if (ir != request_ir) { + ir = request_ir; + JTAG_IR(ir); + } + // Post DP/AP read + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(request_value, NULL); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } + do { + // Read register until its value matches or retry counter expires + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } + } while (((data & DAP_Data.transfer.match_mask) != match_value) && match_retry-- && !DAP_TransferAbort); + if ((data & DAP_Data.transfer.match_mask) != match_value) { + response_value |= DAP_TRANSFER_MISMATCH; + } + if (response_value != DAP_TRANSFER_OK) { + break; + } + } else { + // Normal read + if (post_read == 0U) { + // Select JTAG chain + if (ir != request_ir) { + ir = request_ir; + JTAG_IR(ir); + } + // Post DP/AP read + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(request_value, NULL); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } +#if (TIMESTAMP_CLOCK != 0U) + // Store Timestamp + if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) { + timestamp = DAP_Data.timestamp; + *response++ = (uint8_t) timestamp; + *response++ = (uint8_t)(timestamp >> 8); + *response++ = (uint8_t)(timestamp >> 16); + *response++ = (uint8_t)(timestamp >> 24); + } +#endif + post_read = 1U; + } + } + } else { + // Write register + if (post_read) { + // Select JTAG chain + if (ir != JTAG_DPACC) { + ir = JTAG_DPACC; + JTAG_IR(ir); + } + // Read previous data + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } + // Store previous data + *response++ = (uint8_t) data; + *response++ = (uint8_t)(data >> 8); + *response++ = (uint8_t)(data >> 16); + *response++ = (uint8_t)(data >> 24); + post_read = 0U; + } + // Load data + data = (uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8) | + (uint32_t)(*(request+2) << 16) | + (uint32_t)(*(request+3) << 24); + request += 4; + if ((request_value & DAP_TRANSFER_MATCH_MASK) != 0U) { + // Write match mask + DAP_Data.transfer.match_mask = data; + response_value = DAP_TRANSFER_OK; + } else { + // Select JTAG chain + if (ir != request_ir) { + ir = request_ir; + JTAG_IR(ir); + } + // Write DP/AP register + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } +#if (TIMESTAMP_CLOCK != 0U) + // Store Timestamp + if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) { + timestamp = DAP_Data.timestamp; + *response++ = (uint8_t) timestamp; + *response++ = (uint8_t)(timestamp >> 8); + *response++ = (uint8_t)(timestamp >> 16); + *response++ = (uint8_t)(timestamp >> 24); + } +#endif + } + } + response_count++; + if (DAP_TransferAbort) { + break; + } + } + + for (; request_count != 0U; request_count--) { + // Process canceled requests + request_value = *request++; + if ((request_value & DAP_TRANSFER_RnW) != 0U) { + // Read register + if ((request_value & DAP_TRANSFER_MATCH_VALUE) != 0U) { + // Read with value match + request += 4; + } + } else { + // Write register + request += 4; + } + } + + if (response_value == DAP_TRANSFER_OK) { + // Select JTAG chain + if (ir != JTAG_DPACC) { + ir = JTAG_DPACC; + JTAG_IR(ir); + } + if (post_read) { + // Read previous data + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + goto end; + } + // Store previous data + *response++ = (uint8_t) data; + *response++ = (uint8_t)(data >> 8); + *response++ = (uint8_t)(data >> 16); + *response++ = (uint8_t)(data >> 24); + } else { + // Check last write + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, NULL); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + } + } + +end: + *(response_head+0) = (uint8_t)response_count; + *(response_head+1) = (uint8_t)response_value; + + return (((uint32_t)(request - request_head) << 16) | (uint32_t)(response - response_head)); +} +#endif + + +// Process Dummy Transfer command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_Dummy_Transfer(const uint8_t *request, uint8_t *response) { + const + uint8_t *request_head; + uint32_t request_count; + uint32_t request_value; + + request_head = request; + + request++; // Ignore DAP index + + request_count = *request++; + + for (; request_count != 0U; request_count--) { + // Process dummy requests + request_value = *request++; + if ((request_value & DAP_TRANSFER_RnW) != 0U) { + // Read register + if ((request_value & DAP_TRANSFER_MATCH_VALUE) != 0U) { + // Read with value match + request += 4; + } + } else { + // Write register + request += 4; + } + } + + *(response+0) = 0U; // Response count + *(response+1) = 0U; // Response value + + return (((uint32_t)(request - request_head) << 16) | 2U); +} + + +// Process Transfer command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_Transfer(const uint8_t *request, uint8_t *response) { + uint32_t num; + + switch (DAP_Data.debug_port) { +#if (DAP_SWD != 0) + case DAP_PORT_SWD: + num = DAP_SWD_Transfer(request, response); + break; +#endif +#if (DAP_JTAG != 0) + case DAP_PORT_JTAG: + num = DAP_JTAG_Transfer(request, response); + break; +#endif + default: + num = DAP_Dummy_Transfer(request, response); + break; + } + + return (num); +} + + +// Process SWD Transfer Block command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response +#if (DAP_SWD != 0) +static uint32_t DAP_SWD_TransferBlock(const uint8_t *request, uint8_t *response) { + uint32_t request_count; + uint32_t request_value; + uint32_t response_count; + uint32_t response_value; + uint8_t *response_head; + uint32_t retry; + uint32_t data; + + response_count = 0U; + response_value = 0U; + response_head = response; + response += 3; + + DAP_TransferAbort = 0U; + + request++; // Ignore DAP index + + request_count = (uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8); + request += 2; + if (request_count == 0U) { + goto end; + } + + request_value = *request++; + if ((request_value & DAP_TRANSFER_RnW) != 0U) { + // Read register block + if ((request_value & DAP_TRANSFER_APnDP) != 0U) { + // Post AP read + retry = DAP_Data.transfer.retry_count; + do { + response_value = SWD_Transfer(request_value, NULL); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + goto end; + } + } + while (request_count--) { + // Read DP/AP register + if ((request_count == 0U) && ((request_value & DAP_TRANSFER_APnDP) != 0U)) { + // Last AP read + request_value = DP_RDBUFF | DAP_TRANSFER_RnW; + } + retry = DAP_Data.transfer.retry_count; + do { + response_value = SWD_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + goto end; + } + // Store data + *response++ = (uint8_t) data; + *response++ = (uint8_t)(data >> 8); + *response++ = (uint8_t)(data >> 16); + *response++ = (uint8_t)(data >> 24); + response_count++; + } + } else { + // Write register block + while (request_count--) { + // Load data + data = (uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8) | + (uint32_t)(*(request+2) << 16) | + (uint32_t)(*(request+3) << 24); + request += 4; + // Write DP/AP register + retry = DAP_Data.transfer.retry_count; + do { + response_value = SWD_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + goto end; + } + response_count++; + } + // Check last write + retry = DAP_Data.transfer.retry_count; + do { + response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, NULL); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + } + +end: + *(response_head+0) = (uint8_t)(response_count >> 0); + *(response_head+1) = (uint8_t)(response_count >> 8); + *(response_head+2) = (uint8_t) response_value; + + return ((uint32_t)(response - response_head)); +} +#endif + + +// Process JTAG Transfer Block command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response +#if (DAP_JTAG != 0) +static uint32_t DAP_JTAG_TransferBlock(const uint8_t *request, uint8_t *response) { + uint32_t request_count; + uint32_t request_value; + uint32_t response_count; + uint32_t response_value; + uint8_t *response_head; + uint32_t retry; + uint32_t data; + uint32_t ir; + + response_count = 0U; + response_value = 0U; + response_head = response; + response += 3; + + DAP_TransferAbort = 0U; + + // Device index (JTAP TAP) + DAP_Data.jtag_dev.index = *request++; + if (DAP_Data.jtag_dev.index >= DAP_Data.jtag_dev.count) { + goto end; + } + + request_count = (uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8); + request += 2; + if (request_count == 0U) { + goto end; + } + + request_value = *request++; + + // Select JTAG chain + ir = (request_value & DAP_TRANSFER_APnDP) ? JTAG_APACC : JTAG_DPACC; + JTAG_IR(ir); + + if ((request_value & DAP_TRANSFER_RnW) != 0U) { + // Post read + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(request_value, NULL); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + goto end; + } + // Read register block + while (request_count--) { + // Read DP/AP register + if (request_count == 0U) { + // Last read + if (ir != JTAG_DPACC) { + JTAG_IR(JTAG_DPACC); + } + request_value = DP_RDBUFF | DAP_TRANSFER_RnW; + } + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + goto end; + } + // Store data + *response++ = (uint8_t) data; + *response++ = (uint8_t)(data >> 8); + *response++ = (uint8_t)(data >> 16); + *response++ = (uint8_t)(data >> 24); + response_count++; + } + } else { + // Write register block + while (request_count--) { + // Load data + data = (uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8) | + (uint32_t)(*(request+2) << 16) | + (uint32_t)(*(request+3) << 24); + request += 4; + // Write DP/AP register + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + goto end; + } + response_count++; + } + // Check last write + if (ir != JTAG_DPACC) { + JTAG_IR(JTAG_DPACC); + } + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, NULL); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + } + +end: + *(response_head+0) = (uint8_t)(response_count >> 0); + *(response_head+1) = (uint8_t)(response_count >> 8); + *(response_head+2) = (uint8_t) response_value; + + return ((uint32_t)(response - response_head)); +} +#endif + + +// Process Transfer Block command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_TransferBlock(const uint8_t *request, uint8_t *response) { + uint32_t num; + + switch (DAP_Data.debug_port) { +#if (DAP_SWD != 0) + case DAP_PORT_SWD: + num = DAP_SWD_TransferBlock (request, response); + break; +#endif +#if (DAP_JTAG != 0) + case DAP_PORT_JTAG: + num = DAP_JTAG_TransferBlock(request, response); + break; +#endif + default: + *(response+0) = 0U; // Response count [7:0] + *(response+1) = 0U; // Response count[15:8] + *(response+2) = 0U; // Response value + num = 3U; + break; + } + + if ((*(request+3) & DAP_TRANSFER_RnW) != 0U) { + // Read register block + num |= 4U << 16; + } else { + // Write register block + num |= (4U + (((uint32_t)(*(request+1)) | (uint32_t)(*(request+2) << 8)) * 4)) << 16; + } + + return (num); +} + + +// Process SWD Write ABORT command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response +#if (DAP_SWD != 0) +static uint32_t DAP_SWD_WriteAbort(const uint8_t *request, uint8_t *response) { + uint32_t data; + + // Load data (Ignore DAP index) + data = (uint32_t)(*(request+1) << 0) | + (uint32_t)(*(request+2) << 8) | + (uint32_t)(*(request+3) << 16) | + (uint32_t)(*(request+4) << 24); + + // Write Abort register + SWD_Transfer(DP_ABORT, &data); + + *response = DAP_OK; + return (1U); +} +#endif + + +// Process JTAG Write ABORT command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response +#if (DAP_JTAG != 0) +static uint32_t DAP_JTAG_WriteAbort(const uint8_t *request, uint8_t *response) { + uint32_t data; + + // Device index (JTAP TAP) + DAP_Data.jtag_dev.index = *request; + if (DAP_Data.jtag_dev.index >= DAP_Data.jtag_dev.count) { + *response = DAP_ERROR; + return (1U); + } + + // Select JTAG chain + JTAG_IR(JTAG_ABORT); + + // Load data + data = (uint32_t)(*(request+1) << 0) | + (uint32_t)(*(request+2) << 8) | + (uint32_t)(*(request+3) << 16) | + (uint32_t)(*(request+4) << 24); + + // Write Abort register + JTAG_WriteAbort(data); + + *response = DAP_OK; + return (1U); +} +#endif + + +// Process Write ABORT command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_WriteAbort(const uint8_t *request, uint8_t *response) { + uint32_t num; + + switch (DAP_Data.debug_port) { +#if (DAP_SWD != 0) + case DAP_PORT_SWD: + num = DAP_SWD_WriteAbort (request, response); + break; +#endif +#if (DAP_JTAG != 0) + case DAP_PORT_JTAG: + num = DAP_JTAG_WriteAbort(request, response); + break; +#endif + default: + *response = DAP_ERROR; + num = 1U; + break; + } + return ((5U << 16) | num); +} + + +// Process DAP Vendor command request and prepare response +// Default function (can be overridden) +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +__WEAK uint32_t DAP_ProcessVendorCommand(const uint8_t *request, uint8_t *response) { + (void)request; + *response = ID_DAP_Invalid; + return ((1U << 16) | 1U); +} + + +// Process DAP command request and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t DAP_ProcessCommand(const uint8_t *request, uint8_t *response) { + uint32_t num; + + if ((*request >= ID_DAP_Vendor0) && (*request <= ID_DAP_Vendor31)) { + return DAP_ProcessVendorCommand(request, response); + } + + *response++ = *request; + + switch (*request++) { + case ID_DAP_Info: + num = DAP_Info(*request, response+1); + *response = (uint8_t)num; + return ((2U << 16) + 2U + num); + + case ID_DAP_HostStatus: + num = DAP_HostStatus(request, response); + break; + + case ID_DAP_Connect: + num = DAP_Connect(request, response); + break; + case ID_DAP_Disconnect: + num = DAP_Disconnect(response); + break; + + case ID_DAP_Delay: + num = DAP_Delay(request, response); + break; + + case ID_DAP_ResetTarget: + num = DAP_ResetTarget(response); + break; + + case ID_DAP_SWJ_Pins: + num = DAP_SWJ_Pins(request, response); + break; + case ID_DAP_SWJ_Clock: + num = DAP_SWJ_Clock(request, response); + break; + case ID_DAP_SWJ_Sequence: + num = DAP_SWJ_Sequence(request, response); + break; + + case ID_DAP_SWD_Configure: + num = DAP_SWD_Configure(request, response); + break; + case ID_DAP_SWD_Sequence: + num = DAP_SWD_Sequence(request, response); + break; + + case ID_DAP_JTAG_Sequence: + num = DAP_JTAG_Sequence(request, response); + break; + case ID_DAP_JTAG_Configure: + num = DAP_JTAG_Configure(request, response); + break; + case ID_DAP_JTAG_IDCODE: + num = DAP_JTAG_IDCode(request, response); + break; + + case ID_DAP_TransferConfigure: + num = DAP_TransferConfigure(request, response); + break; + case ID_DAP_Transfer: + num = DAP_Transfer(request, response); + break; + case ID_DAP_TransferBlock: + num = DAP_TransferBlock(request, response); + break; + + case ID_DAP_WriteABORT: + num = DAP_WriteAbort(request, response); + break; + +#if ((SWO_UART != 0) || (SWO_MANCHESTER != 0)) + case ID_DAP_SWO_Transport: + num = SWO_Transport(request, response); + break; + case ID_DAP_SWO_Mode: + num = SWO_Mode(request, response); + break; + case ID_DAP_SWO_Baudrate: + num = SWO_Baudrate(request, response); + break; + case ID_DAP_SWO_Control: + num = SWO_Control(request, response); + break; + case ID_DAP_SWO_Status: + num = SWO_Status(response); + break; + case ID_DAP_SWO_ExtendedStatus: + num = SWO_ExtendedStatus(request, response); + break; + case ID_DAP_SWO_Data: + num = SWO_Data(request, response); + break; +#endif + +#if (DAP_UART != 0) + case ID_DAP_UART_Transport: + num = UART_Transport(request, response); + break; + case ID_DAP_UART_Configure: + num = UART_Configure(request, response); + break; + case ID_DAP_UART_Control: + num = UART_Control(request, response); + break; + case ID_DAP_UART_Status: + num = UART_Status(response); + break; + case ID_DAP_UART_Transfer: + num = UART_Transfer(request, response); + break; +#endif + + default: + *(response-1) = ID_DAP_Invalid; + return ((1U << 16) | 1U); + } + + return ((1U << 16) + 1U + num); +} + + +// Execute DAP command (process request and prepare response) +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t DAP_ExecuteCommand(const uint8_t *request, uint8_t *response) { + uint32_t cnt, num, n; + + if (*request == ID_DAP_ExecuteCommands) { + *response++ = *request++; + cnt = *request++; + *response++ = (uint8_t)cnt; + num = (2U << 16) | 2U; + while (cnt--) { + n = DAP_ProcessCommand(request, response); + num += n; + request += (uint16_t)(n >> 16); + response += (uint16_t) n; + } + return (num); + } + + return DAP_ProcessCommand(request, response); +} + + +// Setup DAP +void DAP_Setup(void) { + + // Default settings + DAP_Data.debug_port = 0U; + DAP_Data.transfer.idle_cycles = 0U; + DAP_Data.transfer.retry_count = 100U; + DAP_Data.transfer.match_retry = 0U; + DAP_Data.transfer.match_mask = 0x00000000U; +#if (DAP_SWD != 0) + DAP_Data.swd_conf.turnaround = 1U; + DAP_Data.swd_conf.data_phase = 0U; +#endif +#if (DAP_JTAG != 0) + DAP_Data.jtag_dev.count = 0U; +#endif + + // Sets DAP_Data.fast_clock and DAP_Data.clock_delay. + Set_Clock_Delay(DAP_DEFAULT_SWJ_CLOCK); + + DAP_SETUP(); // Device specific setup +} diff --git a/Code/DAP_X033/DAP/DAP_Core/DAP.h b/Code/DAP_X033/DAP/DAP_Core/DAP.h new file mode 100644 index 0000000..d56628d --- /dev/null +++ b/Code/DAP_X033/DAP/DAP_Core/DAP.h @@ -0,0 +1,352 @@ +/* + * Copyright (c) 2013-2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 26. April 2022 + * $Revision: V2.1.1 + * + * Project: CMSIS-DAP Include + * Title: DAP.h Definitions + * + *---------------------------------------------------------------------------*/ + +#ifndef __DAP_H__ +#define __DAP_H__ + +#include "DAP_config.h" + +// DAP Firmware Version +#define DAP_FW_VER "X033 v0.1" + +// DAP Command IDs +#define ID_DAP_Info 0x00U +#define ID_DAP_HostStatus 0x01U +#define ID_DAP_Connect 0x02U +#define ID_DAP_Disconnect 0x03U +#define ID_DAP_TransferConfigure 0x04U +#define ID_DAP_Transfer 0x05U +#define ID_DAP_TransferBlock 0x06U +#define ID_DAP_TransferAbort 0x07U +#define ID_DAP_WriteABORT 0x08U +#define ID_DAP_Delay 0x09U +#define ID_DAP_ResetTarget 0x0AU +#define ID_DAP_SWJ_Pins 0x10U +#define ID_DAP_SWJ_Clock 0x11U +#define ID_DAP_SWJ_Sequence 0x12U +#define ID_DAP_SWD_Configure 0x13U +#define ID_DAP_SWD_Sequence 0x1DU +#define ID_DAP_JTAG_Sequence 0x14U +#define ID_DAP_JTAG_Configure 0x15U +#define ID_DAP_JTAG_IDCODE 0x16U +#define ID_DAP_SWO_Transport 0x17U +#define ID_DAP_SWO_Mode 0x18U +#define ID_DAP_SWO_Baudrate 0x19U +#define ID_DAP_SWO_Control 0x1AU +#define ID_DAP_SWO_Status 0x1BU +#define ID_DAP_SWO_ExtendedStatus 0x1EU +#define ID_DAP_SWO_Data 0x1CU +#define ID_DAP_UART_Transport 0x1FU +#define ID_DAP_UART_Configure 0x20U +#define ID_DAP_UART_Control 0x22U +#define ID_DAP_UART_Status 0x23U +#define ID_DAP_UART_Transfer 0x21U + +#define ID_DAP_QueueCommands 0x7EU +#define ID_DAP_ExecuteCommands 0x7FU + +// DAP Vendor Command IDs +#define ID_DAP_Vendor0 0x80U +#define ID_DAP_Vendor1 0x81U +#define ID_DAP_Vendor2 0x82U +#define ID_DAP_Vendor3 0x83U +#define ID_DAP_Vendor4 0x84U +#define ID_DAP_Vendor5 0x85U +#define ID_DAP_Vendor6 0x86U +#define ID_DAP_Vendor7 0x87U +#define ID_DAP_Vendor8 0x88U +#define ID_DAP_Vendor9 0x89U +#define ID_DAP_Vendor10 0x8AU +#define ID_DAP_Vendor11 0x8BU +#define ID_DAP_Vendor12 0x8CU +#define ID_DAP_Vendor13 0x8DU +#define ID_DAP_Vendor14 0x8EU +#define ID_DAP_Vendor15 0x8FU +#define ID_DAP_Vendor16 0x90U +#define ID_DAP_Vendor17 0x91U +#define ID_DAP_Vendor18 0x92U +#define ID_DAP_Vendor19 0x93U +#define ID_DAP_Vendor20 0x94U +#define ID_DAP_Vendor21 0x95U +#define ID_DAP_Vendor22 0x96U +#define ID_DAP_Vendor23 0x97U +#define ID_DAP_Vendor24 0x98U +#define ID_DAP_Vendor25 0x99U +#define ID_DAP_Vendor26 0x9AU +#define ID_DAP_Vendor27 0x9BU +#define ID_DAP_Vendor28 0x9CU +#define ID_DAP_Vendor29 0x9DU +#define ID_DAP_Vendor30 0x9EU +#define ID_DAP_Vendor31 0x9FU + +#define ID_DAP_Invalid 0xFFU + +// DAP Status Code +#define DAP_OK 0U +#define DAP_ERROR 0xFFU + +// DAP ID +#define DAP_ID_VENDOR 1U +#define DAP_ID_PRODUCT 2U +#define DAP_ID_SER_NUM 3U +#define DAP_ID_DAP_FW_VER 4U +#define DAP_ID_DEVICE_VENDOR 5U +#define DAP_ID_DEVICE_NAME 6U +#define DAP_ID_BOARD_VENDOR 7U +#define DAP_ID_BOARD_NAME 8U +#define DAP_ID_PRODUCT_FW_VER 9U +#define DAP_ID_CAPABILITIES 0xF0U +#define DAP_ID_TIMESTAMP_CLOCK 0xF1U +#define DAP_ID_UART_RX_BUFFER_SIZE 0xFBU +#define DAP_ID_UART_TX_BUFFER_SIZE 0xFCU +#define DAP_ID_SWO_BUFFER_SIZE 0xFDU +#define DAP_ID_PACKET_COUNT 0xFEU +#define DAP_ID_PACKET_SIZE 0xFFU + +// DAP Host Status +#define DAP_DEBUGGER_CONNECTED 0U +#define DAP_TARGET_RUNNING 1U + +// DAP Port +#define DAP_PORT_AUTODETECT 0U // Autodetect Port +#define DAP_PORT_DISABLED 0U // Port Disabled (I/O pins in High-Z) +#define DAP_PORT_SWD 1U // SWD Port (SWCLK, SWDIO) + nRESET +#define DAP_PORT_JTAG 2U // JTAG Port (TCK, TMS, TDI, TDO, nTRST) + nRESET + +// DAP SWJ Pins +#define DAP_SWJ_SWCLK_TCK 0 // SWCLK/TCK +#define DAP_SWJ_SWDIO_TMS 1 // SWDIO/TMS +#define DAP_SWJ_TDI 2 // TDI +#define DAP_SWJ_TDO 3 // TDO +#define DAP_SWJ_nTRST 5 // nTRST +#define DAP_SWJ_nRESET 7 // nRESET + +// DAP Transfer Request +#define DAP_TRANSFER_APnDP (1U<<0) +#define DAP_TRANSFER_RnW (1U<<1) +#define DAP_TRANSFER_A2 (1U<<2) +#define DAP_TRANSFER_A3 (1U<<3) +#define DAP_TRANSFER_MATCH_VALUE (1U<<4) +#define DAP_TRANSFER_MATCH_MASK (1U<<5) +#define DAP_TRANSFER_TIMESTAMP (1U<<7) + +// DAP Transfer Response +#define DAP_TRANSFER_OK (1U<<0) +#define DAP_TRANSFER_WAIT (1U<<1) +#define DAP_TRANSFER_FAULT (1U<<2) +#define DAP_TRANSFER_ERROR (1U<<3) +#define DAP_TRANSFER_MISMATCH (1U<<4) + +// DAP SWO Trace Mode +#define DAP_SWO_OFF 0U +#define DAP_SWO_UART 1U +#define DAP_SWO_MANCHESTER 2U + +// DAP SWO Trace Status +#define DAP_SWO_CAPTURE_ACTIVE (1U<<0) +#define DAP_SWO_CAPTURE_PAUSED (1U<<1) +#define DAP_SWO_STREAM_ERROR (1U<<6) +#define DAP_SWO_BUFFER_OVERRUN (1U<<7) + +// DAP UART Transport +#define DAP_UART_TRANSPORT_NONE 0U +#define DAP_UART_TRANSPORT_USB_COM_PORT 1U +#define DAP_UART_TRANSPORT_DAP_COMMAND 2U + +// DAP UART Control +#define DAP_UART_CONTROL_RX_ENABLE (1U<<0) +#define DAP_UART_CONTROL_RX_DISABLE (1U<<1) +#define DAP_UART_CONTROL_RX_BUF_FLUSH (1U<<2) +#define DAP_UART_CONTROL_TX_ENABLE (1U<<4) +#define DAP_UART_CONTROL_TX_DISABLE (1U<<5) +#define DAP_UART_CONTROL_TX_BUF_FLUSH (1U<<6) + +// DAP UART Status +#define DAP_UART_STATUS_RX_ENABLED (1U<<0) +#define DAP_UART_STATUS_RX_DATA_LOST (1U<<1) +#define DAP_UART_STATUS_FRAMING_ERROR (1U<<2) +#define DAP_UART_STATUS_PARITY_ERROR (1U<<3) +#define DAP_UART_STATUS_TX_ENABLED (1U<<4) + +// DAP UART Configure Error +#define DAP_UART_CFG_ERROR_DATA_BITS (1U<<0) +#define DAP_UART_CFG_ERROR_PARITY (1U<<1) +#define DAP_UART_CFG_ERROR_STOP_BITS (1U<<2) + +// Debug Port Register Addresses +#define DP_IDCODE 0x00U // IDCODE Register (SW Read only) +#define DP_ABORT 0x00U // Abort Register (SW Write only) +#define DP_CTRL_STAT 0x04U // Control & Status +#define DP_WCR 0x04U // Wire Control Register (SW Only) +#define DP_SELECT 0x08U // Select Register (JTAG R/W & SW W) +#define DP_RESEND 0x08U // Resend (SW Read Only) +#define DP_RDBUFF 0x0CU // Read Buffer (Read Only) + +// JTAG IR Codes +#define JTAG_ABORT 0x08U +#define JTAG_DPACC 0x0AU +#define JTAG_APACC 0x0BU +#define JTAG_IDCODE 0x0EU +#define JTAG_BYPASS 0x0FU + +// JTAG Sequence Info +#define JTAG_SEQUENCE_TCK 0x3FU // TCK count +#define JTAG_SEQUENCE_TMS 0x40U // TMS value +#define JTAG_SEQUENCE_TDO 0x80U // TDO capture + +// SWD Sequence Info +#define SWD_SEQUENCE_CLK 0x3FU // SWCLK count +#define SWD_SEQUENCE_DIN 0x80U // SWDIO capture + + +#include +#include + +// DAP Data structure +typedef struct { + uint8_t debug_port; // Debug Port + uint8_t fast_clock; // Fast Clock Flag + uint8_t padding[2]; + uint32_t clock_delay; // Clock Delay + uint32_t timestamp; // Last captured Timestamp + struct { // Transfer Configuration + uint8_t idle_cycles; // Idle cycles after transfer + uint8_t padding[3]; + uint16_t retry_count; // Number of retries after WAIT response + uint16_t match_retry; // Number of retries if read value does not match + uint32_t match_mask; // Match Mask + } transfer; +#if (DAP_SWD != 0) + struct { // SWD Configuration + uint8_t turnaround; // Turnaround period + uint8_t data_phase; // Always generate Data Phase + } swd_conf; +#endif +#if (DAP_JTAG != 0) + struct { // JTAG Device Chain + uint8_t count; // Number of devices + uint8_t index; // Device index (device at TDO has index 0) +#if (DAP_JTAG_DEV_CNT != 0) + uint8_t ir_length[DAP_JTAG_DEV_CNT]; // IR Length in bits + uint16_t ir_before[DAP_JTAG_DEV_CNT]; // Bits before IR + uint16_t ir_after [DAP_JTAG_DEV_CNT]; // Bits after IR +#endif + } jtag_dev; +#endif +} DAP_Data_t; + +extern DAP_Data_t DAP_Data; // DAP Data +extern volatile uint8_t DAP_TransferAbort; // Transfer Abort Flag + + +#ifdef __cplusplus +extern "C" +{ +#endif + +// Functions +extern void SWJ_Sequence (uint32_t count, const uint8_t *data); +extern void SWD_Sequence (uint32_t info, const uint8_t *swdo, uint8_t *swdi); +extern void JTAG_Sequence (uint32_t info, const uint8_t *tdi, uint8_t *tdo); +extern void JTAG_IR (uint32_t ir); +extern uint32_t JTAG_ReadIDCode (void); +extern void JTAG_WriteAbort (uint32_t data); +extern uint8_t JTAG_Transfer (uint32_t request, uint32_t *data); +extern uint8_t SWD_Transfer (uint32_t request, uint32_t *data); + +extern void Delayms (uint32_t delay); + +extern uint32_t SWO_Transport (const uint8_t *request, uint8_t *response); +extern uint32_t SWO_Mode (const uint8_t *request, uint8_t *response); +extern uint32_t SWO_Baudrate (const uint8_t *request, uint8_t *response); +extern uint32_t SWO_Control (const uint8_t *request, uint8_t *response); +extern uint32_t SWO_Status (uint8_t *response); +extern uint32_t SWO_ExtendedStatus (const uint8_t *request, uint8_t *response); +extern uint32_t SWO_Data (const uint8_t *request, uint8_t *response); + +extern void SWO_QueueTransfer (uint8_t *buf, uint32_t num); +extern void SWO_AbortTransfer (void); +extern void SWO_TransferComplete (void); + +extern uint32_t SWO_Mode_UART (uint32_t enable); +extern uint32_t SWO_Baudrate_UART (uint32_t baudrate); +extern uint32_t SWO_Control_UART (uint32_t active); +extern void SWO_Capture_UART (uint8_t *buf, uint32_t num); +extern uint32_t SWO_GetCount_UART (void); + +extern uint32_t SWO_Mode_Manchester (uint32_t enable); +extern uint32_t SWO_Baudrate_Manchester (uint32_t baudrate); +extern uint32_t SWO_Control_Manchester (uint32_t active); +extern void SWO_Capture_Manchester (uint8_t *buf, uint32_t num); +extern uint32_t SWO_GetCount_Manchester (void); + +extern uint32_t UART_Transport (const uint8_t *request, uint8_t *response); +extern uint32_t UART_Configure (const uint8_t *request, uint8_t *response); +extern uint32_t UART_Control (const uint8_t *request, uint8_t *response); +extern uint32_t UART_Status (uint8_t *response); +extern uint32_t UART_Transfer (const uint8_t *request, uint8_t *response); + +extern uint8_t USB_COM_PORT_Activate (uint32_t cmd); + +extern uint32_t DAP_ProcessVendorCommand (const uint8_t *request, uint8_t *response); +extern uint32_t DAP_ProcessCommand (const uint8_t *request, uint8_t *response); +extern uint32_t DAP_ExecuteCommand (const uint8_t *request, uint8_t *response); + +extern void DAP_Setup (void); + +// Configurable delay for clock generation +#ifndef DELAY_SLOW_CYCLES +#define DELAY_SLOW_CYCLES 3U // Number of cycles for one iteration +#endif + +__STATIC_FORCEINLINE void PIN_DELAY_SLOW (uint32_t delay) { + volatile uint32_t count = delay; + while (--count); +} + +// Fixed delay for fast clock generation +#ifndef DELAY_FAST_CYCLES +#define DELAY_FAST_CYCLES 0U // Number of cycles: 0..3 +#endif +__STATIC_FORCEINLINE void PIN_DELAY_FAST (void) { +#if (DELAY_FAST_CYCLES >= 1U) + __NOP(); +#endif +#if (DELAY_FAST_CYCLES >= 2U) + __NOP(); +#endif +#if (DELAY_FAST_CYCLES >= 3U) + __NOP(); +#endif +} + +#ifdef __cplusplus +} +#endif + + +#endif /* __DAP_H__ */ diff --git a/Code/DAP_X033/DAP/DAP_Core/DAP_config.h b/Code/DAP_X033/DAP/DAP_Core/DAP_config.h new file mode 100644 index 0000000..a711c7e --- /dev/null +++ b/Code/DAP_X033/DAP/DAP_Core/DAP_config.h @@ -0,0 +1,675 @@ +/* + * Copyright (c) 2013-2021 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 16. June 2021 + * $Revision: V2.1.0 + * + * Project: CMSIS-DAP Configuration + * Title: DAP_config.h CMSIS-DAP Configuration File (Template) + * + *---------------------------------------------------------------------------*/ + +#ifndef __DAP_CONFIG_H__ +#define __DAP_CONFIG_H__ + +#define __STATIC_INLINE static inline +#define __STATIC_FORCEINLINE static inline __attribute__((always_inline)) +#define __WEAK __attribute__((weak)) + +//************************************************************************************************** +/** +\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information +\ingroup DAP_ConfigIO_gr +@{ +Provides definitions about the hardware and configuration of the Debug Unit. + +This information includes: + - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit. + - Debug Unit Identification strings (Vendor, Product, Serial Number). + - Debug Unit communication packet size. + - Debug Access Port supported modes and settings (JTAG/SWD and SWO). + - Optional information about a connected Target Device (for Evaluation Boards). +*/ + +#include "ch32x035.h" +#include "dap_main.h" + +/// Processor Clock of the Cortex-M MCU used in the Debug Unit. +/// This value is used to calculate the SWD/JTAG clock speed. +#define CPU_CLOCK 48000000U ///< Specifies the CPU Clock in Hz. + +/// Number of processor cycles for I/O Port write operations. +/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O +/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors +/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses +/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be +/// required. +#define IO_PORT_WRITE_CYCLES 1U ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0. + +/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available. + +/// Indicate that JTAG communication mode is available at the Debug Port. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_JTAG 1 ///< JTAG Mode: 1 = available, 0 = not available. + +/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port. +/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255. +#define DAP_JTAG_DEV_CNT 8U ///< Maximum number of JTAG devices on scan chain. + +/// Default communication mode on the Debug Access Port. +/// Used for the command \ref DAP_Connect when Port Default mode is selected. +#define DAP_DEFAULT_PORT 1U ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG. + +/// Default communication speed on the Debug Access Port for SWD and JTAG mode. +/// Used to initialize the default SWD/JTAG clock frequency. +/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting. +#define DAP_DEFAULT_SWJ_CLOCK 1000000U ///< Default SWD/JTAG clock frequency in Hz. + +/// Maximum Package Size for Command and Response data. +/// This configuration settings is used to optimize the communication performance with the +/// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or WinUSB, +/// 1024 for High-speed USB HID and 512 for High-speed USB WinUSB. +#define DAP_PACKET_SIZE 64U ///< Specifies Packet Size in bytes. + +/// Maximum Package Buffers for Command and Response data. +/// This configuration settings is used to optimize the communication performance with the +/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the +/// setting can be reduced (valid range is 1 .. 255). +#define DAP_PACKET_COUNT 8U ///< Specifies number of packets buffered. + +/// Indicate that UART Serial Wire Output (SWO) trace is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available. + +/// USART Driver instance number for the UART SWO. +#define SWO_UART_DRIVER 0 ///< USART Driver instance number (Driver_USART#). + +/// Maximum SWO UART Baudrate. +#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz. + +/// Indicate that Manchester Serial Wire Output (SWO) trace is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available. + +/// SWO Trace Buffer Size. +#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n). + +/// SWO Streaming Trace. +#define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available. + +/// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET. +#define TIMESTAMP_CLOCK 0 ///< Timestamp clock in Hz (0 = timestamps not supported). + +/// Indicate that UART Communication Port is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_UART 0 ///< DAP UART: 1 = available, 0 = not available. + +/// USART Driver instance number for the UART Communication Port. +#define DAP_UART_DRIVER 1 ///< USART Driver instance number (Driver_USART#). + +/// UART Receive Buffer Size. +#define DAP_UART_RX_BUFFER_SIZE 1024U ///< Uart Receive Buffer Size in bytes (must be 2^n). + +/// UART Transmit Buffer Size. +#define DAP_UART_TX_BUFFER_SIZE 1024U ///< Uart Transmit Buffer Size in bytes (must be 2^n). + +/// Indicate that UART Communication via USB COM Port is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_UART_USB_COM_PORT 1 ///< USB COM Port: 1 = available, 0 = not available. + +/// Debug Unit is connected to fixed Target Device. +/// The Debug Unit may be part of an evaluation board and always connected to a fixed +/// known device. In this case a Device Vendor, Device Name, Board Vendor and Board Name strings +/// are stored and may be used by the debugger or IDE to configure device parameters. +#define TARGET_FIXED 0 ///< Target: 1 = known, 0 = unknown; + +#define TARGET_DEVICE_VENDOR "Arm" ///< String indicating the Silicon Vendor +#define TARGET_DEVICE_NAME "Cortex-M" ///< String indicating the Target Device +#define TARGET_BOARD_VENDOR "Arm" ///< String indicating the Board Vendor +#define TARGET_BOARD_NAME "Arm board" ///< String indicating the Board Name + +#if TARGET_FIXED != 0 +#include +static const char TargetDeviceVendor [] = TARGET_DEVICE_VENDOR; +static const char TargetDeviceName [] = TARGET_DEVICE_NAME; +static const char TargetBoardVendor [] = TARGET_BOARD_VENDOR; +static const char TargetBoardName [] = TARGET_BOARD_NAME; +#endif + +/** Get Vendor Name string. +\param str Pointer to buffer to store the string (max 60 characters). +\return String length (including terminating NULL character) or 0 (no string). +*/ +__STATIC_INLINE uint8_t DAP_GetVendorString (char *str) { + (void)str; + return (0U); +} + +/** Get Product Name string. +\param str Pointer to buffer to store the string (max 60 characters). +\return String length (including terminating NULL character) or 0 (no string). +*/ +__STATIC_INLINE uint8_t DAP_GetProductString (char *str) { + (void)str; + return (0U); +} + +/** Get Serial Number string. +\param str Pointer to buffer to store the string (max 60 characters). +\return String length (including terminating NULL character) or 0 (no string). +*/ +__STATIC_INLINE uint8_t DAP_GetSerNumString (char *str) { + (void)str; + return (0U); +} + +/** Get Target Device Vendor string. +\param str Pointer to buffer to store the string (max 60 characters). +\return String length (including terminating NULL character) or 0 (no string). +*/ +__STATIC_INLINE uint8_t DAP_GetTargetDeviceVendorString (char *str) { +#if TARGET_FIXED != 0 + uint8_t len; + + strcpy(str, TargetDeviceVendor); + len = (uint8_t)(strlen(TargetDeviceVendor) + 1U); + return (len); +#else + (void)str; + return (0U); +#endif +} + +/** Get Target Device Name string. +\param str Pointer to buffer to store the string (max 60 characters). +\return String length (including terminating NULL character) or 0 (no string). +*/ +__STATIC_INLINE uint8_t DAP_GetTargetDeviceNameString (char *str) { +#if TARGET_FIXED != 0 + uint8_t len; + + strcpy(str, TargetDeviceName); + len = (uint8_t)(strlen(TargetDeviceName) + 1U); + return (len); +#else + (void)str; + return (0U); +#endif +} + +/** Get Target Board Vendor string. +\param str Pointer to buffer to store the string (max 60 characters). +\return String length (including terminating NULL character) or 0 (no string). +*/ +__STATIC_INLINE uint8_t DAP_GetTargetBoardVendorString (char *str) { +#if TARGET_FIXED != 0 + uint8_t len; + + strcpy(str, TargetBoardVendor); + len = (uint8_t)(strlen(TargetBoardVendor) + 1U); + return (len); +#else + (void)str; + return (0U); +#endif +} + +/** Get Target Board Name string. +\param str Pointer to buffer to store the string (max 60 characters). +\return String length (including terminating NULL character) or 0 (no string). +*/ +__STATIC_INLINE uint8_t DAP_GetTargetBoardNameString (char *str) { +#if TARGET_FIXED != 0 + uint8_t len; + + strcpy(str, TargetBoardName); + len = (uint8_t)(strlen(TargetBoardName) + 1U); + return (len); +#else + (void)str; + return (0U); +#endif +} + +/** Get Product Firmware Version string. +\param str Pointer to buffer to store the string (max 60 characters). +\return String length (including terminating NULL character) or 0 (no string). +*/ +__STATIC_INLINE uint8_t DAP_GetProductFirmwareVersionString (char *str) { + (void)str; + return (0U); +} + +///@} + + +//************************************************************************************************** +/** +\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access +\ingroup DAP_ConfigIO_gr +@{ + +Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode +and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug +interface of a device. The following I/O Pins are provided: + +JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode +---------------------------- | -------------------- | --------------------------------------------- +TCK: Test Clock | SWCLK: Clock | Output Push/Pull +TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data) +TDI: Test Data Input | | Output Push/Pull +TDO: Test Data Output | | Input +nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor +nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor + + +DAP Hardware I/O Pin Access Functions +------------------------------------- +The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to +these I/O Pins. + +For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only. +This functions are provided to achieve faster I/O that is possible with some advanced GPIO +peripherals that can independently write/read a single I/O pin without affecting any other pins +of the same I/O port. The following SWDIO I/O Pin functions are provided: + - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware. + - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware. + - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed. + - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed. +*/ + + +// Configure DAP I/O pins ------------------------------ + +/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET. +Configures the DAP Hardware I/O pins for JTAG mode: + - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level. + - TDO to input mode. +*/ +__STATIC_INLINE void PORT_JTAG_SETUP (void) { + RCC->APB2PCENR|=RCC_APB2Periph_GPIOA; + + GPIOA->CFGHR&=~(0x0F<<(4*3));//CLK,GPIOA11 + GPIOA->CFGHR|=0x03<<(4*3); + GPIOA->BSHR=1<<11; + + GPIOA->CFGHR&=~(0x0F<<(4*2));//DIO,GPIOA10 + GPIOA->CFGHR|=0x03<<(4*2); + GPIOA->BSHR=1<<10; + + GPIOA->CFGLR&=~(0x0F<<(4*4));//RST,GPIOA4 + GPIOA->CFGLR|=0x03<<(4*4); + GPIOA->BSHR=1<<4; + + GPIOA->CFGLR&=~(0x0F<<(4*2));//TDI,GPIOA2 + GPIOA->CFGLR|=0x03<<(4*2); + GPIOA->BSHR=1<<2; + + GPIOA->CFGLR&=~(0x0F<<(4*3));//TDO,GPIOA3 + GPIOA->CFGLR|=0x08<<(4*3); + GPIOA->BSHR=1<<3; + +// if (DIR_IsEN == 1) +// { +// GPIOA->CFGLR&=~(0x0F<<(4*5));//DIR,GPIOA5 +// GPIOA->CFGLR|=0x03<<(4*5); +// GPIOA->BCR=1<<5; +// } +} + +/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET. +Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode: + - SWCLK, SWDIO, nRESET to output mode and set to default high level. + - TDI, nTRST to HighZ mode (pins are unused in SWD mode). +*/ +__STATIC_INLINE void PORT_SWD_SETUP (void) { + RCC->APB2PCENR|=RCC_APB2Periph_GPIOA; + + GPIOA->CFGHR&=~(0x0F<<(4*3));//CLK,GPIOA11 + GPIOA->CFGHR|=0x03<<(4*3); + GPIOA->BSHR=1<<11; + + GPIOA->CFGHR&=~(0x0F<<(4*2));//DIO,GPIOA10 + GPIOA->CFGHR|=0x03<<(4*2); + GPIOA->BSHR=1<<10; + + GPIOA->CFGLR&=~(0x0F<<(4*4));//RST,GPIOA4 + GPIOA->CFGLR|=0x03<<(4*4); + GPIOA->BSHR=1<<4; + +// if (DIR_IsEN == 1) +// { +// GPIOA->CFGLR&=~(0x0F<<(4*5));//DIR,GPIOA5 +// GPIOA->CFGLR|=0x03<<(4*5); +// GPIOA->BCR=1<<5; +// } +} + +/** Disable JTAG/SWD I/O Pins. +Disables the DAP Hardware I/O pins which configures: + - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode. +*/ +__STATIC_INLINE void PORT_OFF (void) { + RCC->APB2PCENR|=RCC_APB2Periph_GPIOA; + + GPIOA->CFGHR&=~(0x0F<<(4*3));//CLK,GPIOA11 +// GPIOA->CFGHR|=0x08<<(4*3); +// GPIOA->BSHR=1<<11; + + GPIOA->CFGHR&=~(0x0F<<(4*2));//DIO,GPIOA10 +// GPIOA->CFGHR|=0x08<<(4*2); +// GPIOA->BSHR=1<<10; + + GPIOA->CFGLR&=~(0x0F<<(4*4));//RST,GPIOA4 +// GPIOA->CFGLR|=0x08<<(4*4); +// GPIOA->BSHR=1<<4; + + GPIOA->CFGLR&=~(0x0F<<(4*2));//TDI,GPIOA2 +// GPIOA->CFGLR|=0x08<<(4*2); +// GPIOA->BSHR=1<<2; + + GPIOA->CFGLR&=~(0x0F<<(4*3));//TDO,GPIOA3 +// GPIOA->CFGLR|=0x08<<(4*3); +// GPIOA->BSHR=1<<3; + +// if (DIR_IsEN == 1) +// { +// GPIOA->CFGLR&=~(0x0F<<(4*5));//DIR,GPIOA5 +// GPIOA->CFGLR|=0x08<<(4*5); +// GPIOA->BSHR=1<<5; +// } +} + +// SWCLK/TCK I/O pin ------------------------------------- + +/** SWCLK/TCK I/O pin: Get Input. +\return Current status of the SWCLK/TCK DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN (void) { + return((GPIOA->OUTDR>>11)&0x01); + return 0; +} + +/** SWCLK/TCK I/O pin: Set Output to High. +Set the SWCLK/TCK DAP hardware I/O pin to high level. +*/ +__STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET (void) { + GPIOA->BSHR=1<<11; +} + +/** SWCLK/TCK I/O pin: Set Output to Low. +Set the SWCLK/TCK DAP hardware I/O pin to low level. +*/ +__STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR (void) { + GPIOA->BCR=1<<11; +} + + +// SWDIO/TMS Pin I/O -------------------------------------- + +/** SWDIO/TMS I/O pin: Get Input. +\return Current status of the SWDIO/TMS DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN (void) { + return((GPIOA->INDR>>10)&0x01); + return 0; +} + +/** SWDIO/TMS I/O pin: Set Output to High. +Set the SWDIO/TMS DAP hardware I/O pin to high level. +*/ +__STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET (void) { + GPIOA->BSHR=1<<10; +} + +/** SWDIO/TMS I/O pin: Set Output to Low. +Set the SWDIO/TMS DAP hardware I/O pin to low level. +*/ +__STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR (void) { + GPIOA->BCR=1<<10; +} + +/** SWDIO I/O pin: Get Input (used in SWD mode only). +\return Current status of the SWDIO DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN (void) { + return((GPIOA->INDR>>10)&0x01); + return 0; +} + +/** SWDIO I/O pin: Set Output (used in SWD mode only). +\param bit Output value for the SWDIO DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE void PIN_SWDIO_OUT (uint32_t bit) { + if (bit & 0x01) + { + GPIOA->BSHR=1<<10; + } + else + { + GPIOA->BCR=1<<10; + } +} + +/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only). +Configure the SWDIO DAP hardware I/O pin to output mode. This function is +called prior \ref PIN_SWDIO_OUT function calls. +*/ +__STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE (void) { + GPIOA->CFGHR&=~(0x0F<<(4*2));//DIO,GPIOA10 + GPIOA->CFGHR|=0x03<<(4*2); + +// if (DIR_IsEN == 1) +// { +// GPIOA->BCR=1<<5;//DIR,GPIOA5 +// } +} + +/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only). +Configure the SWDIO DAP hardware I/O pin to input mode. This function is +called prior \ref PIN_SWDIO_IN function calls. +*/ +__STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE (void) { + GPIOA->CFGHR&=~(0x0F<<(4*2));//DIO,GPIOA10 + GPIOA->CFGHR|=0x08<<(4*2); + +// if (DIR_IsEN == 1) +// { +// GPIOA->BSHR=1<<5;//DIR,GPIOA5 +// } +} + + +// TDI Pin I/O --------------------------------------------- + +/** TDI I/O pin: Get Input. +\return Current status of the TDI DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_TDI_IN (void) { + return((GPIOA->OUTDR>>2)&0x01); + return 0; +} + +/** TDI I/O pin: Set Output. +\param bit Output value for the TDI DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE void PIN_TDI_OUT (uint32_t bit) { + if (bit & 0x01) + { + GPIOA->BSHR=1<<2; + } + else + { + GPIOA->BCR=1<<2; + } +} + + +// TDO Pin I/O --------------------------------------------- + +/** TDO I/O pin: Get Input. +\return Current status of the TDO DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_TDO_IN (void) { + return((GPIOA->INDR>>3)&0x01); + return 0; +} + + +// nTRST Pin I/O ------------------------------------------- + +/** nTRST I/O pin: Get Input. +\return Current status of the nTRST DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_nTRST_IN (void) { + return 0; +} + +/** nTRST I/O pin: Set Output. +\param bit JTAG TRST Test Reset pin status: + - 0: issue a JTAG TRST Test Reset. + - 1: release JTAG TRST Test Reset. +*/ +__STATIC_FORCEINLINE void PIN_nTRST_OUT (uint32_t bit) { + +} + +// nRESET Pin I/O------------------------------------------ + +/** nRESET I/O pin: Get Input. +\return Current status of the nRESET DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_nRESET_IN (void) { + return((GPIOA->OUTDR>>4)&0x01); + return 0; +} + +/** nRESET I/O pin: Set Output. +\param bit target device hardware reset pin status: + - 0: issue a device hardware reset. + - 1: release device hardware reset. +*/ +extern uint8_t SWD_Transfer(uint32_t request, uint32_t *data); +__STATIC_FORCEINLINE void PIN_nRESET_OUT (uint32_t bit) { + uint32_t write_data; + if(bit&0x01) + { + write_data = 0x05fa0004;SWD_Transfer(0x0d,&write_data); + GPIOA->BSHR=1<<4; + } + else + { + write_data = 0xe000ed0c;SWD_Transfer(0x05,&write_data); + GPIOA->BCR=1<<4; + } +} + +///@} + + +//************************************************************************************************** +/** +\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs +\ingroup DAP_ConfigIO_gr +@{ + +CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit. + +It is recommended to provide the following LEDs for status indication: + - Connect LED: is active when the DAP hardware is connected to a debugger. + - Running LED: is active when the debugger has put the target device into running state. +*/ + +/** Debug Unit: Set status of Connected LED. +\param bit status of the Connect LED. + - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit. + - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit. +*/ +__STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit) {} + +/** Debug Unit: Set status Target Running LED. +\param bit status of the Target Running LED. + - 1: Target Running LED ON: program execution in target started. + - 0: Target Running LED OFF: program execution in target stopped. +*/ +__STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit) {} + +///@} + + +//************************************************************************************************** +/** +\defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp +\ingroup DAP_ConfigIO_gr +@{ +Access function for Test Domain Timer. + +The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By +default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK. + +*/ + +/** Get timestamp of Test Domain Timer. +\return Current timestamp value. +*/ +__STATIC_INLINE uint32_t TIMESTAMP_GET (void) { + return 0; +} + +///@} + + +//************************************************************************************************** +/** +\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization +\ingroup DAP_ConfigIO_gr +@{ + +CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP. +*/ + +/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized). +This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the +Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set: + - I/O clock system enabled. + - all I/O pins: input buffer enabled, output pins are set to HighZ mode. + - for nTRST, nRESET a weak pull-up (if available) is enabled. + - LED output pins are enabled and LEDs are turned off. +*/ +__STATIC_INLINE void DAP_SETUP (void) { + PORT_OFF(); +} + +/** Reset Target Device with custom specific I/O pin or command sequence. +This function allows the optional implementation of a device specific reset sequence. +It is called when the command \ref DAP_ResetTarget and is for example required +when a device needs a time-critical unlock sequence that enables the debug port. +\return 0 = no device specific reset sequence is implemented.\n + 1 = a device specific reset sequence is implemented. +*/ +__STATIC_INLINE uint8_t RESET_TARGET (void) { + return (0U); // change to '1' when a device reset sequence is implemented +} + +///@} + + +#endif /* __DAP_CONFIG_H__ */ diff --git a/Code/DAP_X033/DAP/DAP_Core/JTAG_DP.c b/Code/DAP_X033/DAP/DAP_Core/JTAG_DP.c new file mode 100644 index 0000000..f5de0c2 --- /dev/null +++ b/Code/DAP_X033/DAP/DAP_Core/JTAG_DP.c @@ -0,0 +1,370 @@ +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 1. December 2017 + * $Revision: V2.0.0 + * + * Project: CMSIS-DAP Source + * Title: JTAG_DP.c CMSIS-DAP JTAG DP I/O + * + *---------------------------------------------------------------------------*/ + +#include "DAP_config.h" +#include "DAP.h" + + +// JTAG Macros + +#define PIN_TCK_SET PIN_SWCLK_TCK_SET +#define PIN_TCK_CLR PIN_SWCLK_TCK_CLR +#define PIN_TMS_SET PIN_SWDIO_TMS_SET +#define PIN_TMS_CLR PIN_SWDIO_TMS_CLR + +#define JTAG_CYCLE_TCK() \ + PIN_TCK_CLR(); \ + PIN_DELAY(); \ + PIN_TCK_SET(); \ + PIN_DELAY() + +#define JTAG_CYCLE_TDI(tdi) \ + PIN_TDI_OUT(tdi); \ + PIN_TCK_CLR(); \ + PIN_DELAY(); \ + PIN_TCK_SET(); \ + PIN_DELAY() + +#define JTAG_CYCLE_TDO(tdo) \ + PIN_TCK_CLR(); \ + PIN_DELAY(); \ + tdo = PIN_TDO_IN(); \ + PIN_TCK_SET(); \ + PIN_DELAY() + +#define JTAG_CYCLE_TDIO(tdi,tdo) \ + PIN_TDI_OUT(tdi); \ + PIN_TCK_CLR(); \ + PIN_DELAY(); \ + tdo = PIN_TDO_IN(); \ + PIN_TCK_SET(); \ + PIN_DELAY() + +#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay) + + +#if (DAP_JTAG != 0) + + +// Generate JTAG Sequence +// info: sequence information +// tdi: pointer to TDI generated data +// tdo: pointer to TDO captured data +// return: none +void JTAG_Sequence (uint32_t info, const uint8_t *tdi, uint8_t *tdo) { + uint32_t i_val; + uint32_t o_val; + uint32_t bit; + uint32_t n, k; + + n = info & JTAG_SEQUENCE_TCK; + if (n == 0U) { + n = 64U; + } + + if (info & JTAG_SEQUENCE_TMS) { + PIN_TMS_SET(); + } else { + PIN_TMS_CLR(); + } + + while (n) { + i_val = *tdi++; + o_val = 0U; + for (k = 8U; k && n; k--, n--) { + JTAG_CYCLE_TDIO(i_val, bit); + i_val >>= 1; + o_val >>= 1; + o_val |= bit << 7; + } + o_val >>= k; + if (info & JTAG_SEQUENCE_TDO) { + *tdo++ = (uint8_t)o_val; + } + } +} + + +// JTAG Set IR +// ir: IR value +// return: none +#define JTAG_IR_Function(speed) /**/ \ +static void JTAG_IR_##speed (uint32_t ir) { \ + uint32_t n; \ + \ + PIN_TMS_SET(); \ + JTAG_CYCLE_TCK(); /* Select-DR-Scan */ \ + JTAG_CYCLE_TCK(); /* Select-IR-Scan */ \ + PIN_TMS_CLR(); \ + JTAG_CYCLE_TCK(); /* Capture-IR */ \ + JTAG_CYCLE_TCK(); /* Shift-IR */ \ + \ + PIN_TDI_OUT(1U); \ + for (n = DAP_Data.jtag_dev.ir_before[DAP_Data.jtag_dev.index]; n; n--) { \ + JTAG_CYCLE_TCK(); /* Bypass before data */ \ + } \ + for (n = DAP_Data.jtag_dev.ir_length[DAP_Data.jtag_dev.index] - 1U; n; n--) { \ + JTAG_CYCLE_TDI(ir); /* Set IR bits (except last) */ \ + ir >>= 1; \ + } \ + n = DAP_Data.jtag_dev.ir_after[DAP_Data.jtag_dev.index]; \ + if (n) { \ + JTAG_CYCLE_TDI(ir); /* Set last IR bit */ \ + PIN_TDI_OUT(1U); \ + for (--n; n; n--) { \ + JTAG_CYCLE_TCK(); /* Bypass after data */ \ + } \ + PIN_TMS_SET(); \ + JTAG_CYCLE_TCK(); /* Bypass & Exit1-IR */ \ + } else { \ + PIN_TMS_SET(); \ + JTAG_CYCLE_TDI(ir); /* Set last IR bit & Exit1-IR */ \ + } \ + \ + JTAG_CYCLE_TCK(); /* Update-IR */ \ + PIN_TMS_CLR(); \ + JTAG_CYCLE_TCK(); /* Idle */ \ + PIN_TDI_OUT(1U); \ +} + + +// JTAG Transfer I/O +// request: A[3:2] RnW APnDP +// data: DATA[31:0] +// return: ACK[2:0] +#define JTAG_TransferFunction(speed) /**/ \ +static uint8_t JTAG_Transfer##speed (uint32_t request, uint32_t *data) { \ + uint32_t ack; \ + uint32_t bit; \ + uint32_t val; \ + uint32_t n; \ + \ + PIN_TMS_SET(); \ + JTAG_CYCLE_TCK(); /* Select-DR-Scan */ \ + PIN_TMS_CLR(); \ + JTAG_CYCLE_TCK(); /* Capture-DR */ \ + JTAG_CYCLE_TCK(); /* Shift-DR */ \ + \ + for (n = DAP_Data.jtag_dev.index; n; n--) { \ + JTAG_CYCLE_TCK(); /* Bypass before data */ \ + } \ + \ + JTAG_CYCLE_TDIO(request >> 1, bit); /* Set RnW, Get ACK.0 */ \ + ack = bit << 1; \ + JTAG_CYCLE_TDIO(request >> 2, bit); /* Set A2, Get ACK.1 */ \ + ack |= bit << 0; \ + JTAG_CYCLE_TDIO(request >> 3, bit); /* Set A3, Get ACK.2 */ \ + ack |= bit << 2; \ + \ + if (ack != DAP_TRANSFER_OK) { \ + /* Exit on error */ \ + PIN_TMS_SET(); \ + JTAG_CYCLE_TCK(); /* Exit1-DR */ \ + goto exit; \ + } \ + \ + if (request & DAP_TRANSFER_RnW) { \ + /* Read Transfer */ \ + val = 0U; \ + for (n = 31U; n; n--) { \ + JTAG_CYCLE_TDO(bit); /* Get D0..D30 */ \ + val |= bit << 31; \ + val >>= 1; \ + } \ + n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1U; \ + if (n) { \ + JTAG_CYCLE_TDO(bit); /* Get D31 */ \ + for (--n; n; n--) { \ + JTAG_CYCLE_TCK(); /* Bypass after data */ \ + } \ + PIN_TMS_SET(); \ + JTAG_CYCLE_TCK(); /* Bypass & Exit1-DR */ \ + } else { \ + PIN_TMS_SET(); \ + JTAG_CYCLE_TDO(bit); /* Get D31 & Exit1-DR */ \ + } \ + val |= bit << 31; \ + if (data) { *data = val; } \ + } else { \ + /* Write Transfer */ \ + val = *data; \ + for (n = 31U; n; n--) { \ + JTAG_CYCLE_TDI(val); /* Set D0..D30 */ \ + val >>= 1; \ + } \ + n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1U; \ + if (n) { \ + JTAG_CYCLE_TDI(val); /* Set D31 */ \ + for (--n; n; n--) { \ + JTAG_CYCLE_TCK(); /* Bypass after data */ \ + } \ + PIN_TMS_SET(); \ + JTAG_CYCLE_TCK(); /* Bypass & Exit1-DR */ \ + } else { \ + PIN_TMS_SET(); \ + JTAG_CYCLE_TDI(val); /* Set D31 & Exit1-DR */ \ + } \ + } \ + \ +exit: \ + JTAG_CYCLE_TCK(); /* Update-DR */ \ + PIN_TMS_CLR(); \ + JTAG_CYCLE_TCK(); /* Idle */ \ + PIN_TDI_OUT(1U); \ + \ + /* Capture Timestamp */ \ + if (request & DAP_TRANSFER_TIMESTAMP) { \ + DAP_Data.timestamp = TIMESTAMP_GET(); \ + } \ + \ + /* Idle cycles */ \ + n = DAP_Data.transfer.idle_cycles; \ + while (n--) { \ + JTAG_CYCLE_TCK(); /* Idle */ \ + } \ + \ + return ((uint8_t)ack); \ +} + + +#undef PIN_DELAY +#define PIN_DELAY() PIN_DELAY_FAST() +JTAG_IR_Function(Fast) +JTAG_TransferFunction(Fast) + +#undef PIN_DELAY +#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay) +JTAG_IR_Function(Slow) +JTAG_TransferFunction(Slow) + + +// JTAG Read IDCODE register +// return: value read +uint32_t JTAG_ReadIDCode (void) { + uint32_t bit; + uint32_t val; + uint32_t n; + + PIN_TMS_SET(); + JTAG_CYCLE_TCK(); /* Select-DR-Scan */ + PIN_TMS_CLR(); + JTAG_CYCLE_TCK(); /* Capture-DR */ + JTAG_CYCLE_TCK(); /* Shift-DR */ + + for (n = DAP_Data.jtag_dev.index; n; n--) { + JTAG_CYCLE_TCK(); /* Bypass before data */ + } + + val = 0U; + for (n = 31U; n; n--) { + JTAG_CYCLE_TDO(bit); /* Get D0..D30 */ + val |= bit << 31; + val >>= 1; + } + PIN_TMS_SET(); + JTAG_CYCLE_TDO(bit); /* Get D31 & Exit1-DR */ + val |= bit << 31; + + JTAG_CYCLE_TCK(); /* Update-DR */ + PIN_TMS_CLR(); + JTAG_CYCLE_TCK(); /* Idle */ + + return (val); +} + + +// JTAG Write ABORT register +// data: value to write +// return: none +void JTAG_WriteAbort (uint32_t data) { + uint32_t n; + + PIN_TMS_SET(); + JTAG_CYCLE_TCK(); /* Select-DR-Scan */ + PIN_TMS_CLR(); + JTAG_CYCLE_TCK(); /* Capture-DR */ + JTAG_CYCLE_TCK(); /* Shift-DR */ + + for (n = DAP_Data.jtag_dev.index; n; n--) { + JTAG_CYCLE_TCK(); /* Bypass before data */ + } + + PIN_TDI_OUT(0U); + JTAG_CYCLE_TCK(); /* Set RnW=0 (Write) */ + JTAG_CYCLE_TCK(); /* Set A2=0 */ + JTAG_CYCLE_TCK(); /* Set A3=0 */ + + for (n = 31U; n; n--) { + JTAG_CYCLE_TDI(data); /* Set D0..D30 */ + data >>= 1; + } + n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1U; + if (n) { + JTAG_CYCLE_TDI(data); /* Set D31 */ + for (--n; n; n--) { + JTAG_CYCLE_TCK(); /* Bypass after data */ + } + PIN_TMS_SET(); + JTAG_CYCLE_TCK(); /* Bypass & Exit1-DR */ + } else { + PIN_TMS_SET(); + JTAG_CYCLE_TDI(data); /* Set D31 & Exit1-DR */ + } + + JTAG_CYCLE_TCK(); /* Update-DR */ + PIN_TMS_CLR(); + JTAG_CYCLE_TCK(); /* Idle */ + PIN_TDI_OUT(1U); +} + + +// JTAG Set IR +// ir: IR value +// return: none +void JTAG_IR (uint32_t ir) { + if (DAP_Data.fast_clock) { + JTAG_IR_Fast(ir); + } else { + JTAG_IR_Slow(ir); + } +} + + +// JTAG Transfer I/O +// request: A[3:2] RnW APnDP +// data: DATA[31:0] +// return: ACK[2:0] +__attribute__((section(".highcode"))) uint8_t JTAG_Transfer(uint32_t request, uint32_t *data) { + if (DAP_Data.fast_clock) { + return JTAG_TransferFast(request, data); + } else { + return JTAG_TransferSlow(request, data); + } +} + + +#endif /* (DAP_JTAG != 0) */ diff --git a/Code/DAP_X033/DAP/DAP_Core/SW_DP.c b/Code/DAP_X033/DAP/DAP_Core/SW_DP.c new file mode 100644 index 0000000..7a1bdf2 --- /dev/null +++ b/Code/DAP_X033/DAP/DAP_Core/SW_DP.c @@ -0,0 +1,286 @@ +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 1. December 2017 + * $Revision: V2.0.0 + * + * Project: CMSIS-DAP Source + * Title: SW_DP.c CMSIS-DAP SW DP I/O + * + *---------------------------------------------------------------------------*/ + +#include "DAP_config.h" +#include "DAP.h" + + +// SW Macros + +#define PIN_SWCLK_SET PIN_SWCLK_TCK_SET +#define PIN_SWCLK_CLR PIN_SWCLK_TCK_CLR + +#define SW_CLOCK_CYCLE() \ + PIN_SWCLK_CLR(); \ + PIN_DELAY(); \ + PIN_SWCLK_SET(); \ + PIN_DELAY() + +#define SW_WRITE_BIT(bit) \ + PIN_SWDIO_OUT(bit); \ + PIN_SWCLK_CLR(); \ + PIN_DELAY(); \ + PIN_SWCLK_SET(); \ + PIN_DELAY() + +#define SW_READ_BIT(bit) \ + PIN_SWCLK_CLR(); \ + PIN_DELAY(); \ + bit = PIN_SWDIO_IN(); \ + PIN_SWCLK_SET(); \ + PIN_DELAY() + +#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay) + + +// Generate SWJ Sequence +// count: sequence bit count +// data: pointer to sequence bit data +// return: none +#if ((DAP_SWD != 0) || (DAP_JTAG != 0)) +void SWJ_Sequence (uint32_t count, const uint8_t *data) { + uint32_t val; + uint32_t n; + + val = 0U; + n = 0U; + while (count--) { + if (n == 0U) { + val = *data++; + n = 8U; + } + if (val & 1U) { + PIN_SWDIO_TMS_SET(); + } else { + PIN_SWDIO_TMS_CLR(); + } + SW_CLOCK_CYCLE(); + val >>= 1; + n--; + } +} +#endif + + +// Generate SWD Sequence +// info: sequence information +// swdo: pointer to SWDIO generated data +// swdi: pointer to SWDIO captured data +// return: none +#if (DAP_SWD != 0) +void SWD_Sequence (uint32_t info, const uint8_t *swdo, uint8_t *swdi) { + uint32_t val; + uint32_t bit; + uint32_t n, k; + + n = info & SWD_SEQUENCE_CLK; + if (n == 0U) { + n = 64U; + } + + if (info & SWD_SEQUENCE_DIN) { + while (n) { + val = 0U; + for (k = 8U; k && n; k--, n--) { + SW_READ_BIT(bit); + val >>= 1; + val |= bit << 7; + } + val >>= k; + *swdi++ = (uint8_t)val; + } + } else { + while (n) { + val = *swdo++; + for (k = 8U; k && n; k--, n--) { + SW_WRITE_BIT(val); + val >>= 1; + } + } + } +} +#endif + + +#if (DAP_SWD != 0) + + +// SWD Transfer I/O +// request: A[3:2] RnW APnDP +// data: DATA[31:0] +// return: ACK[2:0] +#define SWD_TransferFunction(speed) /**/ \ +static uint8_t SWD_Transfer##speed (uint32_t request, uint32_t *data) { \ + uint32_t ack; \ + uint32_t bit; \ + uint32_t val; \ + uint32_t parity; \ + \ + uint32_t n; \ + \ + /* Packet Request */ \ + parity = 0U; \ + SW_WRITE_BIT(1U); /* Start Bit */ \ + bit = request >> 0; \ + SW_WRITE_BIT(bit); /* APnDP Bit */ \ + parity += bit; \ + bit = request >> 1; \ + SW_WRITE_BIT(bit); /* RnW Bit */ \ + parity += bit; \ + bit = request >> 2; \ + SW_WRITE_BIT(bit); /* A2 Bit */ \ + parity += bit; \ + bit = request >> 3; \ + SW_WRITE_BIT(bit); /* A3 Bit */ \ + parity += bit; \ + SW_WRITE_BIT(parity); /* Parity Bit */ \ + SW_WRITE_BIT(0U); /* Stop Bit */ \ + SW_WRITE_BIT(1U); /* Park Bit */ \ + \ + /* Turnaround */ \ + PIN_SWDIO_OUT_DISABLE(); \ + for (n = DAP_Data.swd_conf.turnaround; n; n--) { \ + SW_CLOCK_CYCLE(); \ + } \ + \ + /* Acknowledge response */ \ + SW_READ_BIT(bit); \ + ack = bit << 0; \ + SW_READ_BIT(bit); \ + ack |= bit << 1; \ + SW_READ_BIT(bit); \ + ack |= bit << 2; \ + \ + if (ack == DAP_TRANSFER_OK) { /* OK response */ \ + /* Data transfer */ \ + if (request & DAP_TRANSFER_RnW) { \ + /* Read data */ \ + val = 0U; \ + parity = 0U; \ + for (n = 32U; n; n--) { \ + SW_READ_BIT(bit); /* Read RDATA[0:31] */ \ + parity += bit; \ + val >>= 1; \ + val |= bit << 31; \ + } \ + SW_READ_BIT(bit); /* Read Parity */ \ + if ((parity ^ bit) & 1U) { \ + ack = DAP_TRANSFER_ERROR; \ + } \ + if (data) { *data = val; } \ + /* Turnaround */ \ + for (n = DAP_Data.swd_conf.turnaround; n; n--) { \ + SW_CLOCK_CYCLE(); \ + } \ + PIN_SWDIO_OUT_ENABLE(); \ + } else { \ + /* Turnaround */ \ + for (n = DAP_Data.swd_conf.turnaround; n; n--) { \ + SW_CLOCK_CYCLE(); \ + } \ + PIN_SWDIO_OUT_ENABLE(); \ + /* Write data */ \ + val = *data; \ + parity = 0U; \ + for (n = 32U; n; n--) { \ + SW_WRITE_BIT(val); /* Write WDATA[0:31] */ \ + parity += val; \ + val >>= 1; \ + } \ + SW_WRITE_BIT(parity); /* Write Parity Bit */ \ + } \ + /* Capture Timestamp */ \ + if (request & DAP_TRANSFER_TIMESTAMP) { \ + DAP_Data.timestamp = TIMESTAMP_GET(); \ + } \ + /* Idle cycles */ \ + n = DAP_Data.transfer.idle_cycles; \ + if (n) { \ + PIN_SWDIO_OUT(0U); \ + for (; n; n--) { \ + SW_CLOCK_CYCLE(); \ + } \ + } \ + PIN_SWDIO_OUT(1U); \ + return ((uint8_t)ack); \ + } \ + \ + if ((ack == DAP_TRANSFER_WAIT) || (ack == DAP_TRANSFER_FAULT)) { \ + /* WAIT or FAULT response */ \ + if (DAP_Data.swd_conf.data_phase && ((request & DAP_TRANSFER_RnW) != 0U)) { \ + for (n = 32U+1U; n; n--) { \ + SW_CLOCK_CYCLE(); /* Dummy Read RDATA[0:31] + Parity */ \ + } \ + } \ + /* Turnaround */ \ + for (n = DAP_Data.swd_conf.turnaround; n; n--) { \ + SW_CLOCK_CYCLE(); \ + } \ + PIN_SWDIO_OUT_ENABLE(); \ + if (DAP_Data.swd_conf.data_phase && ((request & DAP_TRANSFER_RnW) == 0U)) { \ + PIN_SWDIO_OUT(0U); \ + for (n = 32U+1U; n; n--) { \ + SW_CLOCK_CYCLE(); /* Dummy Write WDATA[0:31] + Parity */ \ + } \ + } \ + PIN_SWDIO_OUT(1U); \ + return ((uint8_t)ack); \ + } \ + \ + /* Protocol error */ \ + for (n = DAP_Data.swd_conf.turnaround + 32U + 1U; n; n--) { \ + SW_CLOCK_CYCLE(); /* Back off data phase */ \ + } \ + PIN_SWDIO_OUT_ENABLE(); \ + PIN_SWDIO_OUT(1U); \ + return ((uint8_t)ack); \ +} + + +#undef PIN_DELAY +#define PIN_DELAY() PIN_DELAY_FAST() +SWD_TransferFunction(Fast) + +#undef PIN_DELAY +#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay) +SWD_TransferFunction(Slow) + + +// SWD Transfer I/O +// request: A[3:2] RnW APnDP +// data: DATA[31:0] +// return: ACK[2:0] +__attribute__((section(".highcode"))) uint8_t SWD_Transfer(uint32_t request, uint32_t *data) { + if (DAP_Data.fast_clock) { + return SWD_TransferFast(request, data); + } else { + return SWD_TransferSlow(request, data); + } +} + + +#endif /* (DAP_SWD != 0) */ diff --git a/Code/DAP_X033/DAP/buffer.c b/Code/DAP_X033/DAP/buffer.c new file mode 100644 index 0000000..bb2ca32 --- /dev/null +++ b/Code/DAP_X033/DAP/buffer.c @@ -0,0 +1,82 @@ +#include "buffer.h" + +void buffer_init(buffer_t *buffer, unsigned int len) +{ + buffer->data = (unsigned char *)BUFFER_MALLOC(len); + buffer->buffer_size = len; + buffer->buffer_in_cnt = 0; + buffer->buffer_out_cnt = 0; + buffer->buffer_in_index = 0; + buffer->buffer_out_index = 0; +} + +void buffer_reset(buffer_t *buffer) +{ + buffer->buffer_in_cnt = 0; + buffer->buffer_out_cnt = 0; + buffer->buffer_in_index = 0; + buffer->buffer_out_index = 0; +} + +int buffer_in(buffer_t *buffer, unsigned char *data, unsigned int len) +{ + if (buffer->buffer_in_cnt + len - buffer->buffer_out_cnt > buffer->buffer_size) + { + return -1; + } + + unsigned int i; + for (i = 0; i < len; i++) + { + buffer->data[(buffer->buffer_in_index + i) % buffer->buffer_size] = data[i]; + } + buffer->buffer_in_index = (buffer->buffer_in_index + len) % buffer->buffer_size; + buffer->buffer_in_cnt += len; + return 0; +} + +int buffer_out(buffer_t *buffer, unsigned char *data, unsigned int *len, unsigned int max_len) +{ + if (buffer->buffer_out_cnt >= buffer->buffer_in_cnt) + { + return -1; + } + + *len = buffer->buffer_in_cnt - buffer->buffer_out_cnt; + if (*len > max_len) + { + *len = max_len; + } + + unsigned int i; + for (i = 0; i < *len; i++) + { + if (data) + data[i] = buffer->data[(buffer->buffer_out_index + i) % buffer->buffer_size]; + } + buffer->buffer_out_index = (buffer->buffer_out_index + *len) % buffer->buffer_size; + buffer->buffer_out_cnt += *len; + return 0; +} + +int buffer_out_without_decrease(buffer_t *buffer, unsigned char *data, unsigned int *len, unsigned int max_len) +{ + if (buffer->buffer_out_cnt >= buffer->buffer_in_cnt) + { + return -1; + } + + *len = buffer->buffer_in_cnt - buffer->buffer_out_cnt; + if (*len > max_len) + { + *len = max_len; + } + + unsigned int i; + for (i = 0; i < *len; i++) + { + if (data) + data[i] = buffer->data[(buffer->buffer_out_index + i) % buffer->buffer_size]; + } + return 0; +} diff --git a/Code/DAP_X033/DAP/buffer.h b/Code/DAP_X033/DAP/buffer.h new file mode 100644 index 0000000..dced90a --- /dev/null +++ b/Code/DAP_X033/DAP/buffer.h @@ -0,0 +1,20 @@ +#ifndef _BUFFER_H_ +#define _BUFFER_H_ + +#include "stdlib.h" +#define BUFFER_MALLOC malloc + +typedef struct { + unsigned char *data; + unsigned int buffer_size; + unsigned int buffer_in_cnt, buffer_out_cnt; + unsigned int buffer_in_index, buffer_out_index; +} buffer_t; + +void buffer_init(buffer_t *buffer, unsigned int len); +void buffer_reset(buffer_t *buffer); +int buffer_in(buffer_t *buffer, unsigned char *data, unsigned int len); +int buffer_out(buffer_t *buffer, unsigned char *data, unsigned int *len, unsigned int max_len); +int buffer_out_without_decrease(buffer_t *buffer, unsigned char *data, unsigned int *len, unsigned int max_len); + +#endif \ No newline at end of file diff --git a/Code/DAP_X033/DAP/cdc_main.c b/Code/DAP_X033/DAP/cdc_main.c new file mode 100644 index 0000000..4470edb --- /dev/null +++ b/Code/DAP_X033/DAP/cdc_main.c @@ -0,0 +1,64 @@ +#include "cdc_main.h" +#include "buffer.h" +#include "usb_desc.h" +#include "usart.h" + +volatile uint8_t CDC_Is_Active = 0; + +buffer_t usb2uart_buffer; +buffer_t uart2usb_buffer; + +uint8_t uart2usb_buf[CDC_EP_SIZE]; +unsigned int uart2usb_txlen = 0; +uint8_t usb2uart_buf[CDC_EP_SIZE]; +unsigned int usb2uart_txlen = 0; + +void CDC_RX_CallBack(uint8_t *buf, uint32_t len) +{ + buffer_in(&usb2uart_buffer, buf, len); +} + +void CDC_TX_CallBack(void) +{ + buffer_out(&uart2usb_buffer, NULL, &uart2usb_txlen, uart2usb_txlen); +} + +void UART_RX_CallBack(uint8_t *buf, uint32_t len) +{ + buffer_in(&uart2usb_buffer, buf, len); +} + +void UART_TX_CallBack(void) +{ + buffer_out(&usb2uart_buffer, NULL, &usb2uart_txlen, usb2uart_txlen); + CDC_RX_Start(); +} + +void CDC_Init(void) +{ + buffer_init(&usb2uart_buffer, CDC_BUFFER_SIZE); + buffer_init(&uart2usb_buffer, CDC_BUFFER_SIZE); +} + +void CDC_Task(void) +{ + if (!CDC_IN_IsBusy()) + { + if (buffer_out_without_decrease(&uart2usb_buffer, uart2usb_buf, &uart2usb_txlen, sizeof(uart2usb_buf)) == 0) + { + CDC_IN(uart2usb_buf, uart2usb_txlen); + + CDC_Is_Active = 1; + } + } + + if (!USART4_Send_IsBusy()) + { + if (buffer_out_without_decrease(&usb2uart_buffer, usb2uart_buf, &usb2uart_txlen, sizeof(usb2uart_buf)) == 0) + { + USART4_DMA_Send(usb2uart_buf, usb2uart_txlen); + + CDC_Is_Active = 1; + } + } +} diff --git a/Code/DAP_X033/DAP/cdc_main.h b/Code/DAP_X033/DAP/cdc_main.h new file mode 100644 index 0000000..522bb3f --- /dev/null +++ b/Code/DAP_X033/DAP/cdc_main.h @@ -0,0 +1,18 @@ +#ifndef _CDC_MAIN_H +#define _CDC_MAIN_H + +#include "main.h" + +#define CDC_BUFFER_SIZE 1024 +#define CDC_EP_SIZE 64 + +extern volatile uint8_t CDC_Is_Active; + +void CDC_RX_CallBack(uint8_t *buf, uint32_t len); +void CDC_TX_CallBack(void); +void UART_RX_CallBack(uint8_t *buf, uint32_t len); +void UART_TX_CallBack(void); +void CDC_Init(void); +void CDC_Task(void); + +#endif \ No newline at end of file diff --git a/Code/DAP_X033/DAP/dap_main.c b/Code/DAP_X033/DAP/dap_main.c new file mode 100644 index 0000000..ede2e43 --- /dev/null +++ b/Code/DAP_X033/DAP/dap_main.c @@ -0,0 +1,139 @@ +#include "dap_main.h" +#include "string.h" + +#include "usb_desc.h" + +#include "DAP_config.h" +#include "DAP.h" + +volatile uint8_t DAP_USB_IsBulk = 0; +volatile uint8_t DAP_Is_Active = 0; +volatile uint8_t DIR_IsEN = 0; + +static volatile uint32_t DAP_RequestIndexI = 0; // Request Index In +static volatile uint32_t DAP_RequestIndexO = 0; // Request Index Out +static volatile uint32_t DAP_RequestCountI = 0; // Request Count In +static volatile uint32_t DAP_RequestCountO = 0; // Request Count Out + +static volatile uint32_t DAP_ResponseIndexI = 0; // Response Index In +static volatile uint32_t DAP_ResponseIndexO = 0; // Response Index Out +static volatile uint32_t DAP_ResponseCountI = 0; // Response Count In +static volatile uint32_t DAP_ResponseCountO = 0; // Response Count Out + +static uint8_t DAP_Request[DAP_PACKET_COUNT][DAP_PACKET_SIZE + 2]; // Request Buffer,last 2 is length +static uint8_t DAP_Response[DAP_PACKET_COUNT][DAP_PACKET_SIZE + 2]; // Response Buffer,last 2 is length + +void DAP_RX_CallBack(uint8_t *buf, uint32_t len) +{ + if (DAP_RequestCountI - DAP_RequestCountO == DAP_PACKET_COUNT) + { + return; + } + + memcpy(DAP_Request[DAP_RequestIndexI], buf, len); + *(uint16_t *)(DAP_Request[DAP_RequestIndexI] + DAP_PACKET_SIZE - 1) = len; + + if (DAP_Request[DAP_RequestIndexI][0] == ID_DAP_TransferAbort) + { + DAP_TransferAbort = 1U; + return; + } + + DAP_RequestIndexI++; + if (DAP_RequestIndexI == DAP_PACKET_COUNT) + { + DAP_RequestIndexI = 0U; + } + DAP_RequestCountI++; +} + +void DAP_TX_CallBack(void) +{ + DAP_ResponseIndexO++; + if (DAP_ResponseIndexO == DAP_PACKET_COUNT) + { + DAP_ResponseIndexO = 0; + } + DAP_ResponseCountO++; +} + +void DAP_Init(void) +{ + DAP_Setup(); + +// RCC->APB2PCENR |= RCC_APB2Periph_GPIOA; +// GPIOA->CFGLR &= ~(0x0F << (4 * 5)); // DIR,GPIOA5 +// GPIOA->CFGLR |= 0x08 << (4 * 5); +// GPIOA->BCR = 1 << 5; +// +// for (volatile uint32_t i = 0; i < 100; i++) +// { +// __NOP(); +// } +// +// uint8_t temp = (GPIOA->INDR >> 5) & 0x01; +// if (temp == 0) +// { +// DIR_IsEN = 1; +// } +// +// if (DIR_IsEN == 0) +// { +// GPIOA->CFGLR &= ~(0x0F << (4 * 5)); // DIR,GPIOA5 +// } +// else +// { +// GPIOA->CFGLR &= ~(0x0F << (4 * 5)); // DIR,GPIOA5 +// GPIOA->CFGLR |= 0x03 << (4 * 5); +// GPIOA->BCR = 1 << 5; +// } +} + +void DAP_Task(void) +{ + if (DAP_RequestCountI != DAP_RequestCountO) + { + // Handle Queue Commands + if (DAP_Request[DAP_RequestIndexO][0] == ID_DAP_QueueCommands) + DAP_Request[DAP_RequestIndexO][0] = ID_DAP_ExecuteCommands; + + uint32_t num = 0; + num = DAP_ExecuteCommand(DAP_Request[DAP_RequestIndexO], DAP_Response[DAP_ResponseIndexI]); + *(uint16_t *)(DAP_Response[DAP_ResponseIndexI] + DAP_PACKET_SIZE - 1) = num & 0x0000FFFF; + + DAP_RequestIndexO++; + if (DAP_RequestIndexO == DAP_PACKET_COUNT) + { + DAP_RequestIndexO = 0U; + } + DAP_RequestCountO++; + + DAP_ResponseIndexI++; + if (DAP_ResponseIndexI == DAP_PACKET_COUNT) + { + DAP_ResponseIndexI = 0U; + } + DAP_ResponseCountI++; + + DAP_Is_Active = 1; + } + + if (DAP_USB_IsBulk) + { + if (DAP_Bulk_IN_IsBusy()) + return; + if (DAP_ResponseCountI != DAP_ResponseCountO) + { + DAP_Bulk_IN(DAP_Response[DAP_ResponseIndexO], *(uint16_t *)(DAP_Response[DAP_ResponseIndexO] + DAP_PACKET_SIZE - 1)); + } + } + else + { + if (DAP_HID_IN_IsBusy()) + return; + if (DAP_ResponseCountI != DAP_ResponseCountO) + { + DAP_HID_IN(DAP_Response[DAP_ResponseIndexO], *(uint16_t *)(DAP_Response[DAP_ResponseIndexO] + DAP_PACKET_SIZE - 1)); + } + } +} diff --git a/Code/DAP_X033/DAP/dap_main.h b/Code/DAP_X033/DAP/dap_main.h new file mode 100644 index 0000000..820f363 --- /dev/null +++ b/Code/DAP_X033/DAP/dap_main.h @@ -0,0 +1,15 @@ +#ifndef _DAP_MAIN_H_ +#define _DAP_MAIN_H_ + +#include "main.h" + +extern volatile uint8_t DAP_USB_IsBulk; +extern volatile uint8_t DAP_Is_Active; +extern volatile uint8_t DIR_IsEN; + +void DAP_RX_CallBack(uint8_t *buf, uint32_t len); +void DAP_TX_CallBack(void); +void DAP_Init(void); +void DAP_Task(void); + +#endif diff --git a/Code/DAP_X033/DAP/led.c b/Code/DAP_X033/DAP/led.c new file mode 100644 index 0000000..851c0fe --- /dev/null +++ b/Code/DAP_X033/DAP/led.c @@ -0,0 +1,106 @@ +#include "led.h" +#include "dap_main.h" +#include "cdc_main.h" + +static void TIM3_Init(u16 arr, u16 psc) +{ + TIM_TimeBaseInitTypeDef TIM_TimeBaseInitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + + RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE); + + TIM_TimeBaseInitStructure.TIM_Period = arr; + TIM_TimeBaseInitStructure.TIM_Prescaler = psc; + TIM_TimeBaseInitStructure.TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStructure.TIM_ClockDivision = TIM_CKD_DIV1; + + TIM_TimeBaseInit(TIM3, &TIM_TimeBaseInitStructure); + + TIM_ITConfig(TIM3, TIM_IT_Update, ENABLE); + + NVIC_InitStructure.NVIC_IRQChannel = TIM3_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 3; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + TIM_Cmd(TIM3, ENABLE); +} + +void LED_Init(void) +{ + RCC->APB2PCENR |= RCC_APB2Periph_GPIOA; + RCC->APB2PCENR |= RCC_APB2Periph_GPIOC; + + GPIOA->CFGHR &= ~(0x0F << (4 * 1)); // LED1,GPIOA9 + GPIOA->CFGHR |= 0x03 << (4 * 1); + GPIOA->BSHR = 1 << 9; + + GPIOC->CFGLR &= ~(0x0F << (4 * 3)); // LED2,GPIOC3 + GPIOC->CFGLR |= 0x03 << (4 * 3); + GPIOC->BSHR = 1 << 3; + + TIM3_Init(1000 - 1, 48 - 1); +} + +static void LED_Task(void) +{ + static uint32_t LED_Task_Cnt = 0; + static uint32_t DAP_In_Active_Cnt = 0; + static uint32_t CDC_In_Active_Cnt = 0; + + if (DAP_Is_Active == 1) + DAP_In_Active_Cnt = 0; + else if (DAP_In_Active_Cnt < 500) + DAP_In_Active_Cnt++; + DAP_Is_Active = 0; + + if (DAP_In_Active_Cnt >= 500) + { + GPIOA->BCR = 1 << 9; // LED1 + } + else + { + if (LED_Task_Cnt % 100 == 0) + { + if (GPIOA->OUTDR & (1 << 9)) + GPIOA->BCR = 1 << 9; + else + GPIOA->BSHR = 1 << 9; + } + } + + if (CDC_Is_Active == 1) + CDC_In_Active_Cnt = 0; + else if (CDC_In_Active_Cnt < 500) + CDC_In_Active_Cnt++; + CDC_Is_Active = 0; + + if (CDC_In_Active_Cnt >= 500) + { + GPIOC->BCR = 1 << 3; // LED2 + } + else + { + if (LED_Task_Cnt % 100 == 0) + { + if (GPIOC->OUTDR & (1 << 3)) + GPIOC->BCR = 1 << 3; + else + GPIOC->BSHR = 1 << 3; + } + } + + LED_Task_Cnt++; +} + +void TIM3_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void TIM3_IRQHandler(void) +{ + if (TIM_GetITStatus(TIM3, TIM_IT_Update) == SET) + { + TIM_ClearITPendingBit(TIM3, TIM_IT_Update); + + LED_Task(); + } +} diff --git a/Code/DAP_X033/DAP/led.h b/Code/DAP_X033/DAP/led.h new file mode 100644 index 0000000..f4c963f --- /dev/null +++ b/Code/DAP_X033/DAP/led.h @@ -0,0 +1,8 @@ +#ifndef _LED_H +#define _LED_H + +#include "main.h" + +void LED_Init(void); + +#endif diff --git a/Code/DAP_X033/DAP/usart.c b/Code/DAP_X033/DAP/usart.c new file mode 100644 index 0000000..eb5e01e --- /dev/null +++ b/Code/DAP_X033/DAP/usart.c @@ -0,0 +1,214 @@ +#include "usart.h" +#include "cdc_main.h" + +#define U4_DATA_BUF_LEN CDC_EP_SIZE + +volatile uint8_t USART4_TX_Flag = 0; // 0:IDLE,1:TX +uint8_t U4_Rxbuf[U4_DATA_BUF_LEN]; + +void USART4_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure = {0}; + USART_InitTypeDef USART_InitStructure = {0}; + NVIC_InitTypeDef NVIC_InitStructure = {0}; + + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART4, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + USART_InitStructure.USART_BaudRate = 115200; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Tx | USART_Mode_Rx; + + USART_Init(USART4, &USART_InitStructure); + + USART_ITConfig(USART4, USART_IT_IDLE, ENABLE); + + NVIC_InitStructure.NVIC_IRQChannel = USART4_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + USART_Cmd(USART4, ENABLE); +} + +void USART4_Config_Linecoding(uint8_t LineCoding[7]) +{ + USART_InitTypeDef USART_InitStructure = {0}; + + uint32_t dataRat; + uint8_t stopBit, parityType, dataBit; + + dataRat = (LineCoding[3] << 24) | (LineCoding[2] << 16) | (LineCoding[1] << 8) | LineCoding[0]; + stopBit = LineCoding[4]; + parityType = LineCoding[5]; + dataBit = LineCoding[6]; + + if(dataRat == 0) return; + + USART_InitStructure.USART_BaudRate = dataRat; + + if (stopBit == 0) + USART_InitStructure.USART_StopBits = USART_StopBits_1; + else if (stopBit == 1) + USART_InitStructure.USART_StopBits = USART_StopBits_1_5; + else if (stopBit == 2) + USART_InitStructure.USART_StopBits = USART_StopBits_2; + else + USART_InitStructure.USART_StopBits = USART_StopBits_1; + + if (parityType == 0) + USART_InitStructure.USART_Parity = USART_Parity_No; + else if (parityType == 1) + USART_InitStructure.USART_Parity = USART_Parity_Odd; + else if (parityType == 2) + USART_InitStructure.USART_Parity = USART_Parity_Even; + else + USART_InitStructure.USART_Parity = USART_Parity_No; + + if(dataBit == 8) + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + else if(dataBit == 9) + USART_InitStructure.USART_WordLength = USART_WordLength_9b; + else + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Tx | USART_Mode_Rx; + + USART_Init(USART4, &USART_InitStructure); + USART4_DMA_Recv(); +} + +void USART4_DMA_Init(void) +{ + DMA_InitTypeDef DMA_InitStructure = {0}; + NVIC_InitTypeDef NVIC_InitStructure = {0}; + + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE); + + DMA_DeInit(DMA1_Channel1); + DMA_InitStructure.DMA_PeripheralBaseAddr = (u32)(&USART4->DATAR); + DMA_InitStructure.DMA_MemoryBaseAddr = 0; + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST; + DMA_InitStructure.DMA_BufferSize = 0; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; + DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; + DMA_InitStructure.DMA_M2M = DMA_M2M_Disable; + DMA_Init(DMA1_Channel1, &DMA_InitStructure); + + NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel1_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + DMA_ClearFlag(DMA1_FLAG_TC1); + DMA_ITConfig(DMA1_Channel1, DMA_IT_TC, ENABLE); + + DMA_DeInit(DMA1_Channel8); + DMA_InitStructure.DMA_PeripheralBaseAddr = (u32)(&USART4->DATAR); + DMA_InitStructure.DMA_MemoryBaseAddr = (u32)U4_Rxbuf; + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC; + DMA_InitStructure.DMA_BufferSize = U4_DATA_BUF_LEN; + DMA_Init(DMA1_Channel8, &DMA_InitStructure); + + NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel8_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + DMA_ClearFlag(DMA1_FLAG_TC8); + DMA_ITConfig(DMA1_Channel8, DMA_IT_TC, ENABLE); +} + +void USART4_DMA_Recv(void) +{ + DMA_Cmd(DMA1_Channel8, DISABLE); + + DMA1_Channel8->MADDR = (u32)U4_Rxbuf; + DMA1_Channel8->CNTR = U4_DATA_BUF_LEN; + + DMA_Cmd(DMA1_Channel8, ENABLE); + USART_DMACmd(USART4, USART_DMAReq_Rx, ENABLE); +} + +void USART4_DMA_Send(uint8_t *data, uint32_t datalen) +{ + while (USART4_TX_Flag == 1) + ; + USART4_TX_Flag = 1; + + DMA_Cmd(DMA1_Channel1, DISABLE); + + DMA1_Channel1->MADDR = (uint32_t)data; + DMA1_Channel1->CNTR = datalen; + + DMA_Cmd(DMA1_Channel1, ENABLE); + USART_DMACmd(USART4, USART_DMAReq_Tx, ENABLE); +} + +uint8_t USART4_Send_IsBusy(void) +{ + return USART4_TX_Flag; +} + +void USART4_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void USART4_IRQHandler(void) +{ + if (USART_GetITStatus(USART4, USART_IT_IDLE) == SET) + { + UART_RX_CallBack(U4_Rxbuf, U4_DATA_BUF_LEN - DMA1_Channel8->CNTR); + + USART4_DMA_Recv(); + + // Clear IDLE IT + volatile uint8_t temp = 0; + temp = USART4->STATR; + temp = USART4->DATAR; + if (temp != 0) + temp = 0; + } +} + +void DMA1_Channel1_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void DMA1_Channel1_IRQHandler(void) +{ + if (DMA_GetITStatus(DMA1_IT_TC1) == SET) + { + UART_TX_CallBack(); + + USART4_TX_Flag = 0; + + DMA_ClearITPendingBit(DMA1_IT_TC1); + } +} + +void DMA1_Channel8_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void DMA1_Channel8_IRQHandler(void) +{ + if (DMA_GetITStatus(DMA1_IT_TC8) == SET) + { + UART_RX_CallBack(U4_Rxbuf, U4_DATA_BUF_LEN - DMA1_Channel8->CNTR); + + USART4_DMA_Recv(); + + DMA_ClearITPendingBit(DMA1_IT_TC8); + } +} diff --git a/Code/DAP_X033/DAP/usart.h b/Code/DAP_X033/DAP/usart.h new file mode 100644 index 0000000..b7e1ed3 --- /dev/null +++ b/Code/DAP_X033/DAP/usart.h @@ -0,0 +1,17 @@ +#ifndef _USART_H +#define _USART_H + +#include "main.h" + + // Usart2_DMA_Init(); + // Usart2_Init(); + // USART2_DMA_Recv_Data(U2_Rxbuf,U2_DATA_BUF_LEN); + +void USART4_Init(void); +void USART4_DMA_Init(void); +void USART4_DMA_Recv(void); +void USART4_DMA_Send(uint8_t *data, uint32_t datalen); +uint8_t USART4_Send_IsBusy(void); +void USART4_Config_Linecoding(uint8_t LineCoding[7]); + +#endif diff --git a/Code/DAP_X033/DAP/usb_desc.c b/Code/DAP_X033/DAP/usb_desc.c new file mode 100644 index 0000000..2647c8b --- /dev/null +++ b/Code/DAP_X033/DAP/usb_desc.c @@ -0,0 +1,501 @@ +#include "usb_desc.h" +#include "usbd_core.h" +#include "usbd_cdc.h" +#include "usbd_hid.h" + +#include "dap_main.h" +#include "cdc_main.h" +#include "usart.h" + +#define USB_IOEN 0x00000080 +#define USB_PHY_V33 0x00000040 +#define UDP_PUE_MASK 0x0000000C +#define UDP_PUE_DISABLE 0x00000000 +#define UDP_PUE_35UA 0x00000004 +#define UDP_PUE_10K 0x00000008 +#define UDP_PUE_1K5 0x0000000C + +#define UDM_PUE_MASK 0x00000003 +#define UDM_PUE_DISABLE 0x00000000 +#define UDM_PUE_35UA 0x00000001 +#define UDM_PUE_10K 0x00000002 +#define UDM_PUE_1K5 0x00000003 + +void usb_dc_low_level_init(void) +{ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_USBFS, ENABLE); + + GPIO_InitTypeDef GPIO_InitStructure = {0}; + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_16; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_17; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + if (PWR_VDD_SupplyVoltage() == PWR_VDD_5V) // to be tested + AFIO->CTLR = (AFIO->CTLR & ~(UDP_PUE_MASK | UDM_PUE_MASK | USB_PHY_V33)) | UDP_PUE_10K | USB_IOEN; + else + AFIO->CTLR = (AFIO->CTLR & ~(UDP_PUE_MASK | UDM_PUE_MASK)) | USB_PHY_V33 | UDP_PUE_1K5 | USB_IOEN; + + NVIC_InitTypeDef NVIC_InitStructure = {0}; + NVIC_InitStructure.NVIC_IRQChannel = USBFS_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); +} + +static uint8_t DAP_Bulk_RX_Buf[DAP_BULK_SIZE] __attribute__((aligned(4))); +static uint8_t DAP_Bulk_TX_Buf[DAP_BULK_SIZE] __attribute__((aligned(4))); +static uint8_t DAP_HID_RX_Buf[DAP_HID_SIZE] __attribute__((aligned(4))); +static uint8_t DAP_HID_TX_Buf[DAP_HID_SIZE] __attribute__((aligned(4))); +static uint8_t CDC_RX_Buf[CDC_SIZE] __attribute__((aligned(4))); +static uint8_t CDC_TX_Buf[CDC_SIZE] __attribute__((aligned(4))); + +static volatile uint8_t DAP_Bulk_IN_Busy = 0, DAP_HID_IN_Busy = 0, CDC_IN_Busy = 0; + +#define DAP_BULK_INTERFACE_SIZE (9 + 7 + 7) +#define DAP_HID_INTERFACE_SIZE (9 + 9 + 7 + 7) +#define USB_CONFIG_SIZE (9 + DAP_BULK_INTERFACE_SIZE + DAP_HID_INTERFACE_SIZE + CDC_ACM_DESCRIPTOR_LEN) + +#define HID_DESCRIPTOR_SIZE 36 + +static uint8_t dap_descriptor[] = { + USB_DEVICE_DESCRIPTOR_INIT(USB_2_1, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0100, 0x01), + + // bNumInterfaces: 1(dap hid)+1(dap bulk)+2(cdc)=4 + USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 4, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + + // bInterfaceClass:0xFF,Vendor Specific + // bInterfaceSubClass:0x00 + // bInterfaceProtocol:0x00 + // iInterface:0x04,string4 + USB_INTERFACE_DESCRIPTOR_INIT(0x00, 0x00, 0x02, 0xFF, 0x00, 0x00, 0x04), + + USB_ENDPOINT_DESCRIPTOR_INIT(DAP_BULK_OUT_EP, USB_ENDPOINT_TYPE_BULK, DAP_BULK_SIZE, 0x00), + USB_ENDPOINT_DESCRIPTOR_INIT(DAP_BULK_IN_EP, USB_ENDPOINT_TYPE_BULK, DAP_BULK_SIZE, 0x00), + + // bInterfaceClass:0x03,HID + // bInterfaceSubClass:0x00 + // bInterfaceProtocol:0x00 + // iInterface:0x05,string5 + USB_INTERFACE_DESCRIPTOR_INIT(0x01, 0x00, 0x02, 0x03, 0x00, 0x00, 0x05), + /******************** Descriptor of Custom HID ********************/ + 0x09, /* bLength: HID Descriptor size */ + HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ + 0x10, /* bcdHID: HID Class Spec release number */ + 0x01, + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + HID_DESCRIPTOR_SIZE, /* wItemLength: Total length of Report descriptor */ + 0x00, + + USB_ENDPOINT_DESCRIPTOR_INIT(DAP_HID_OUT_EP, USB_ENDPOINT_TYPE_INTERRUPT, DAP_HID_SIZE, 0x01), + USB_ENDPOINT_DESCRIPTOR_INIT(DAP_HID_IN_EP, USB_ENDPOINT_TYPE_INTERRUPT, DAP_HID_SIZE, 0x01), + + // str_idx:0x06,string6 + CDC_ACM_DESCRIPTOR_INIT(0x02, CDC_INT_EP, CDC_OUT_EP, CDC_IN_EP, CDC_SIZE, 0x06), + + /* String 0 (LANGID) */ + USB_LANGID_INIT(USBD_LANGID_STRING), + /* String 1 (Manufacturer) */ + 12, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'H', 0x00, /* wcChar0 */ + 'o', 0x00, /* wcChar1 */ + 'r', 0x00, /* wcChar2 */ + 'c', 0x00, /* wcChar3 */ + 'o', 0x00, /* wcChar4 */ + /* String 2 (Product) */ + 32, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'H', 0x00, /* wcChar0 */ + 'o', 0x00, /* wcChar1 */ + 'r', 0x00, /* wcChar2 */ + 'c', 0x00, /* wcChar3 */ + 'o', 0x00, /* wcChar4 */ + ' ', 0x00, /* wcChar5 */ + 'C', 0x00, /* wcChar6 */ + 'M', 0x00, /* wcChar7 */ + 'S', 0x00, /* wcChar8 */ + 'I', 0x00, /* wcChar9 */ + 'S', 0x00, /* wcChar10 */ + '-', 0x00, /* wcChar11 */ + 'D', 0x00, /* wcChar12 */ + 'A', 0x00, /* wcChar13 */ + 'P', 0x00, /* wcChar14 */ + /* String 3 (Serial Number) */ + 0x1A, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + '1', 0x00, /* wcChar0 */ + '3', 0x00, /* wcChar1 */ + '1', 0x00, /* wcChar2 */ + '4', 0x00, /* wcChar3 */ + '0', 0x00, /* wcChar4 */ + '5', 0x00, /* wcChar5 */ + '2', 0x00, /* wcChar6 */ + '1', 0x00, /* wcChar7 */ + '3', 0x00, /* wcChar8 */ + '3', 0x00, /* wcChar9 */ + '3', 0x00, /* wcChar10 */ + '3', 0x00, /* wcChar11 */ + /* String 4 (Interface) */ + 38, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'H', 0x00, /* wcChar0 */ + 'o', 0x00, /* wcChar1 */ + 'r', 0x00, /* wcChar2 */ + 'c', 0x00, /* wcChar3 */ + 'o', 0x00, /* wcChar4 */ + ' ', 0x00, /* wcChar5 */ + 'C', 0x00, /* wcChar6 */ + 'M', 0x00, /* wcChar7 */ + 'S', 0x00, /* wcChar8 */ + 'I', 0x00, /* wcChar9 */ + 'S', 0x00, /* wcChar10 */ + '-', 0x00, /* wcChar11 */ + 'D', 0x00, /* wcChar12 */ + 'A', 0x00, /* wcChar13 */ + 'P', 0x00, /* wcChar14 */ + ' ', 0x00, /* wcChar15 */ + 'v', 0x00, /* wcChar16 */ + '2', 0x00, /* wcChar17 */ + // /* String 5 (Interface) */ + 38, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'H', 0x00, /* wcChar0 */ + 'o', 0x00, /* wcChar1 */ + 'r', 0x00, /* wcChar2 */ + 'c', 0x00, /* wcChar3 */ + 'o', 0x00, /* wcChar4 */ + ' ', 0x00, /* wcChar5 */ + 'C', 0x00, /* wcChar6 */ + 'M', 0x00, /* wcChar7 */ + 'S', 0x00, /* wcChar8 */ + 'I', 0x00, /* wcChar9 */ + 'S', 0x00, /* wcChar10 */ + '-', 0x00, /* wcChar11 */ + 'D', 0x00, /* wcChar12 */ + 'A', 0x00, /* wcChar13 */ + 'P', 0x00, /* wcChar14 */ + ' ', 0x00, /* wcChar15 */ + 'v', 0x00, /* wcChar16 */ + '1', 0x00, /* wcChar17 */ + // /* String 6 (Interface) */ + 20, // bLength + USB_DESCRIPTOR_TYPE_STRING, // bDescriptorType + 'H', 0x00, /* wcChar0 */ + 'o', 0x00, /* wcChar1 */ + 'r', 0x00, /* wcChar2 */ + 'c', 0x00, /* wcChar3 */ + 'o', 0x00, /* wcChar4 */ + ' ', 0x00, /* wcChar5 */ + 'C', 0, /* wcChar6 */ + 'D', 0, /* wcChar7 */ + 'C', 0, /* wcChar8 */ +#ifdef CONFIG_USB_HS + /////////////////////////////////////// + /// device qualifier descriptor + /////////////////////////////////////// + 0x0A, + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0xFF, + 0xFF, + 0xFF, + 0x40, + 0x01, + 0x00, +#endif + 0x00}; + +#define USBD_WINUSB_NUM 1 +#define FUNCTION_SUBSET_LEN 160 +#define DEVICE_INTERFACE_GUIDS_FEATURE_LEN 132 +#define USBD_WINUSB_DESC_SET_LEN (WINUSB_DESCRIPTOR_SET_HEADER_SIZE + USBD_WINUSB_NUM * FUNCTION_SUBSET_LEN) + +static const uint8_t dap_winusb_descriptor[] = { + WBVAL(WINUSB_DESCRIPTOR_SET_HEADER_SIZE), /* wLength */ + WBVAL(WINUSB_SET_HEADER_DESCRIPTOR_TYPE), /* wDescriptorType */ + 0x00, 0x00, 0x03, 0x06, /* >= Win 8.1 */ /* dwWindowsVersion*/ + WBVAL(USBD_WINUSB_DESC_SET_LEN), /* wDescriptorSetTotalLength */ + + WBVAL(WINUSB_FUNCTION_SUBSET_HEADER_SIZE), /* wLength */ + WBVAL(WINUSB_SUBSET_HEADER_FUNCTION_TYPE), /* wDescriptorType */ + 0, /* bFirstInterface USBD_BULK_IF_NUM*/ + 0, /* bReserved */ + WBVAL(FUNCTION_SUBSET_LEN), /* wSubsetLength */ + + WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_SIZE), /* wLength */ + WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_TYPE), /* wDescriptorType */ + 'W', 'I', 'N', 'U', 'S', 'B', 0, 0, /* CompatibleId*/ + 0, 0, 0, 0, 0, 0, 0, 0, /* SubCompatibleId*/ + WBVAL(DEVICE_INTERFACE_GUIDS_FEATURE_LEN), /* wLength */ + WBVAL(WINUSB_FEATURE_REG_PROPERTY_TYPE), /* wDescriptorType */ + WBVAL(WINUSB_PROP_DATA_TYPE_REG_MULTI_SZ), /* wPropertyDataType */ + WBVAL(42), /* wPropertyNameLength */ + 'D', 0, 'e', 0, 'v', 0, 'i', 0, 'c', 0, 'e', 0, + 'I', 0, 'n', 0, 't', 0, 'e', 0, 'r', 0, 'f', 0, 'a', 0, 'c', 0, 'e', 0, + 'G', 0, 'U', 0, 'I', 0, 'D', 0, 's', 0, 0, 0, + WBVAL(80), /* wPropertyDataLength */ + '{', 0, + 'C', 0, 'D', 0, 'B', 0, '3', 0, 'B', 0, '5', 0, 'A', 0, 'D', 0, '-', 0, + '2', 0, '9', 0, '3', 0, 'B', 0, '-', 0, + '4', 0, '6', 0, '6', 0, '3', 0, '-', 0, + 'A', 0, 'A', 0, '3', 0, '6', 0, '-', + 0, '1', 0, 'A', 0, 'A', 0, 'E', 0, '4', 0, '6', 0, '4', 0, '6', 0, '3', 0, '7', 0, '7', 0, '6', 0, + '}', 0, 0, 0, 0, 0}; + +#define USBD_WINUSB_VENDOR_CODE 0x01 // + +#define USBD_WINUSB_DESC_LEN 28 +#define USBD_BOS_WTOTALLENGTH (0x05 + USBD_WINUSB_DESC_LEN * USBD_WINUSB_NUM) + +static const uint8_t dap_bos_descriptor[] = { + 0x05, /* bLength */ + 0x0f, /* bDescriptorType */ + WBVAL(USBD_BOS_WTOTALLENGTH), /* wTotalLength */ + USBD_WINUSB_NUM, /* bNumDeviceCaps */ + + USBD_WINUSB_DESC_LEN, /* bLength */ + 0x10, /* bDescriptorType */ + USB_DEVICE_CAPABILITY_PLATFORM, /* bDevCapabilityType */ + 0x00, /* bReserved */ + 0xDF, 0x60, 0xDD, 0xD8, /* PlatformCapabilityUUID */ + 0x89, 0x45, 0xC7, 0x4C, + 0x9C, 0xD2, 0x65, 0x9D, + 0x9E, 0x64, 0x8A, 0x9F, + 0x00, 0x00, 0x03, 0x06, /* >= Win 8.1 */ /* dwWindowsVersion*/ + WBVAL(USBD_WINUSB_DESC_SET_LEN), /* wDescriptorSetTotalLength */ + USBD_WINUSB_VENDOR_CODE, /* bVendorCode */ + 0, /* bAltEnumCode */ +}; + +static struct usb_bos_descriptor bos_desc = { + .string = (uint8_t *)&dap_bos_descriptor[0], + .string_len = USBD_BOS_WTOTALLENGTH}; + +static struct usb_msosv2_descriptor msosv2_desc = { + .vendor_code = USBD_WINUSB_VENDOR_CODE, + .compat_id = (uint8_t *)&dap_winusb_descriptor[0], + .compat_id_len = USBD_WINUSB_DESC_SET_LEN, +}; + +static const uint8_t dap_hid_descriptor[] = { + 0x06, 0x00, 0xff, + 0x09, 0x01, 0xa1, 0x01, 0x15, 0x00, 0x26, 0xff, 0x00, 0x75, 0x08, 0x96, WBVAL(DAP_HID_SIZE), + 0x09, 0x01, 0x81, 0x02, 0x96, WBVAL(DAP_HID_SIZE), + 0x09, 0x01, 0x91, 0x02, 0x96, WBVAL(DAP_HID_SIZE), + 0x09, 0x01, 0xb1, 0x02, + 0xC0}; + +static void usbd_event_handler(uint8_t busid, uint8_t event) +{ + switch (event) + { + case USBD_EVENT_RESET: + break; + case USBD_EVENT_CONNECTED: + break; + case USBD_EVENT_DISCONNECTED: + break; + case USBD_EVENT_RESUME: + break; + case USBD_EVENT_SUSPEND: + break; + case USBD_EVENT_CONFIGURED: + /* setup first out ep read transfer */ + usbd_ep_start_read(0, DAP_BULK_OUT_EP, DAP_Bulk_RX_Buf, DAP_BULK_SIZE); + usbd_ep_start_read(0, DAP_HID_OUT_EP, DAP_HID_RX_Buf, DAP_HID_SIZE); + usbd_ep_start_read(0, CDC_OUT_EP, CDC_RX_Buf, CDC_SIZE); + break; + case USBD_EVENT_SET_REMOTE_WAKEUP: + break; + case USBD_EVENT_CLR_REMOTE_WAKEUP: + break; + + default: + break; + } +} + +static void DAP_Bulk_IN_CallBack(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + DAP_Bulk_IN_Busy = false; + if (DAP_USB_IsBulk) + DAP_TX_CallBack(); +} + +static void DAP_Bulk_OUT_CallBack(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + DAP_USB_IsBulk = true; + DAP_RX_CallBack(DAP_Bulk_RX_Buf, nbytes); + usbd_ep_start_read(0, DAP_BULK_OUT_EP, DAP_Bulk_RX_Buf, DAP_BULK_SIZE); +} + +void DAP_Bulk_IN(uint8_t *buf, uint32_t len) +{ + if (DAP_Bulk_IN_Busy) + return; + DAP_Bulk_IN_Busy = true; + memcpy(DAP_Bulk_TX_Buf, buf, len); + usbd_ep_start_write(0, DAP_BULK_IN_EP, DAP_Bulk_TX_Buf, len); +} + +uint8_t DAP_Bulk_IN_IsBusy(void) +{ + return DAP_Bulk_IN_Busy; +} + +static void DAP_HID_IN_CallBack(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + DAP_HID_IN_Busy = false; + if (!DAP_USB_IsBulk) + DAP_TX_CallBack(); +} + +static void DAP_HID_OUT_CallBack(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + DAP_USB_IsBulk = false; + DAP_RX_CallBack(DAP_HID_RX_Buf, nbytes); + usbd_ep_start_read(0, DAP_HID_OUT_EP, DAP_HID_RX_Buf, DAP_HID_SIZE); +} + +void DAP_HID_IN(uint8_t *buf, uint32_t len) +{ + if (DAP_HID_IN_Busy) + return; + DAP_HID_IN_Busy = true; + memcpy(DAP_HID_TX_Buf, buf, len); + usbd_ep_start_write(0, DAP_HID_IN_EP, DAP_HID_TX_Buf, DAP_HID_SIZE); +} + +uint8_t DAP_HID_IN_IsBusy(void) +{ + return DAP_HID_IN_Busy; +} + +static void CDC_IN_CallBack(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + CDC_IN_Busy = false; + CDC_TX_CallBack(); +} + +static void CDC_OUT_CallBack(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + CDC_RX_CallBack(CDC_RX_Buf, nbytes); +} + +void CDC_RX_Start(void) +{ + usbd_ep_start_read(0, CDC_OUT_EP, CDC_RX_Buf, CDC_SIZE); +} + +void CDC_IN(uint8_t *buf, uint32_t len) +{ + if (CDC_IN_Busy) + return; + CDC_IN_Busy = true; + memcpy(CDC_TX_Buf, buf, len); + usbd_ep_start_write(0, CDC_IN_EP, CDC_TX_Buf, len); +} + +uint8_t CDC_IN_IsBusy(void) +{ + return CDC_IN_Busy; +} + +static struct usbd_interface DAP_Bulk_Interface; +static struct usbd_endpoint DAP_Bulk_OUT_Endpoint = { + .ep_addr = DAP_BULK_OUT_EP, + .ep_cb = DAP_Bulk_OUT_CallBack, +}; +static struct usbd_endpoint DAP_Bulk_IN_Endpoint = { + .ep_addr = DAP_BULK_IN_EP, + .ep_cb = DAP_Bulk_IN_CallBack, +}; + +static struct usbd_interface DAP_HID_Interface; +static struct usbd_endpoint DAP_HID_OUT_Endpoint = { + .ep_addr = DAP_HID_OUT_EP, + .ep_cb = DAP_HID_OUT_CallBack, +}; +static struct usbd_endpoint DAP_HID_IN_Endpoint = { + .ep_addr = DAP_HID_IN_EP, + .ep_cb = DAP_HID_IN_CallBack, +}; + +static struct usbd_interface CDC_Interface1; +static struct usbd_interface CDC_Interface2; +static struct usbd_endpoint CDC_OUT_Endpoint = { + .ep_addr = CDC_OUT_EP, + .ep_cb = CDC_OUT_CallBack, +}; +static struct usbd_endpoint CDC_IN_Endpoint = { + .ep_addr = CDC_IN_EP, + .ep_cb = CDC_IN_CallBack, +}; + +uint8_t line_coding_now[7]; +void usbd_cdc_acm_set_line_coding(uint8_t busid, uint8_t intf, struct cdc_line_coding *line_coding) +{ + memcpy(line_coding_now, (uint8_t *)line_coding, 7); + USART4_Config_Linecoding(line_coding_now); +} + +void usbd_cdc_acm_get_line_coding(uint8_t busid, uint8_t intf, struct cdc_line_coding *line_coding) +{ + memcpy(line_coding, line_coding_now, 7); +} + +void usbd_cdc_acm_set_dtr(uint8_t busid, uint8_t intf, bool dtr) +{ +} + +void usbd_cdc_acm_set_rts(uint8_t busid, uint8_t intf, bool rts) +{ +} + +void usbd_cdc_acm_send_break(uint8_t busid, uint8_t intf) +{ +} + +#define ESIG_ADDR ((uint32_t)0x1FFFF7E8) +void DAP_USB_Init(void) +{ + uint8_t unique_id[0x1A - 2]; + uint8_t uid_buf[12]; + memcpy(uid_buf, (uint8_t *)ESIG_ADDR, 12); + for (uint8_t i = 0; i < 12; i++) + { + unique_id[2 * i] = uid_buf[i] % 9 + '0'; + unique_id[2 * i + 1] = 0; + } + memcpy(dap_descriptor + 198, unique_id, 0x1A - 2); + + usbd_desc_register(0, dap_descriptor); + usbd_bos_desc_register(0, &bos_desc); + usbd_msosv2_desc_register(0, &msosv2_desc); + + usbd_add_interface(0, &DAP_Bulk_Interface); + usbd_add_endpoint(0, &DAP_Bulk_OUT_Endpoint); + usbd_add_endpoint(0, &DAP_Bulk_IN_Endpoint); + + usbd_add_interface(0, usbd_hid_init_intf(0, &DAP_HID_Interface, dap_hid_descriptor, HID_DESCRIPTOR_SIZE)); + usbd_add_endpoint(0, &DAP_HID_OUT_Endpoint); + usbd_add_endpoint(0, &DAP_HID_IN_Endpoint); + + usbd_add_interface(0, usbd_cdc_acm_init_intf(0, &CDC_Interface1)); + usbd_add_interface(0, usbd_cdc_acm_init_intf(0, &CDC_Interface2)); + usbd_add_endpoint(0, &CDC_OUT_Endpoint); + usbd_add_endpoint(0, &CDC_IN_Endpoint); + + usbd_initialize(0, USBFS_BASE, &usbd_event_handler); +} diff --git a/Code/DAP_X033/DAP/usb_desc.h b/Code/DAP_X033/DAP/usb_desc.h new file mode 100644 index 0000000..4b76128 --- /dev/null +++ b/Code/DAP_X033/DAP/usb_desc.h @@ -0,0 +1,34 @@ +#ifndef _USB_DESC_H +#define _USB_DESC_H + +#include "main.h" + +#define DAP_BULK_IN_EP 0x81 +#define DAP_BULK_OUT_EP 0x01 +#define DAP_BULK_SIZE 64 + +#define DAP_HID_IN_EP 0x82 +#define DAP_HID_OUT_EP 0x02 +#define DAP_HID_SIZE 64 + +#define CDC_IN_EP 0x83 +#define CDC_OUT_EP 0x03 +#define CDC_INT_EP 0x84 +#define CDC_SIZE 64 + +#define USBD_VID 0xFAED +#define USBD_PID 0x4873 + +#define USBD_MAX_POWER 500 +#define USBD_LANGID_STRING 1033 + +void DAP_USB_Init(void); +void DAP_Bulk_IN(uint8_t *buf, uint32_t len); +uint8_t DAP_Bulk_IN_IsBusy(void); +void DAP_HID_IN(uint8_t *buf, uint32_t len); +uint8_t DAP_HID_IN_IsBusy(void); +void CDC_IN(uint8_t *buf, uint32_t len); +uint8_t CDC_IN_IsBusy(void); +void CDC_RX_Start(void); + +#endif diff --git a/Code/DAP_X033/DAP_X033.launch b/Code/DAP_X033/DAP_X033.launch new file mode 100644 index 0000000..92922fe --- /dev/null +++ b/Code/DAP_X033/DAP_X033.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Code/DAP_X033/DAP_X033.wvproj b/Code/DAP_X033/DAP_X033.wvproj new file mode 100644 index 0000000..919bb86 Binary files /dev/null and b/Code/DAP_X033/DAP_X033.wvproj differ diff --git a/Code/DAP_X033/Ld/Link.ld b/Code/DAP_X033/Ld/Link.ld new file mode 100644 index 0000000..a047fa1 --- /dev/null +++ b/Code/DAP_X033/Ld/Link.ld @@ -0,0 +1 @@ +ENTRY( _start ) __stack_size = 2048; PROVIDE( _stack_size = __stack_size ); MEMORY { FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 62K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K } SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); } >FLASH AT>FLASH .highcodelalign : { . = ALIGN(4); PROVIDE(_highcode_lma = .); } >FLASH AT>FLASH .highcode : { . = ALIGN(4); PROVIDE(_highcode_vma_start = .); *(.vector); KEEP(*(SORT_NONE(.vector_handler))) *(.highcode); *(.highcode.*); . = ALIGN(4); PROVIDE(_highcode_vma_end = .); } >RAM AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) *(.sdata2.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM } \ No newline at end of file diff --git a/Code/DAP_X033/Peripheral/inc/PIOC_SFR.h b/Code/DAP_X033/Peripheral/inc/PIOC_SFR.h new file mode 100644 index 0000000..fcb81ea --- /dev/null +++ b/Code/DAP_X033/Peripheral/inc/PIOC_SFR.h @@ -0,0 +1,266 @@ +/* Define for PIOC */ +/* Website: http://wch.cn */ +/* Email: tech@wch.cn */ +/* Author: W.ch 2022.08 */ +/* V1.0 SpecialFunctionRegister */ + +// __PIOC_SFR_H__ + +#ifndef __PIOC_SFR_H__ +#define __PIOC_SFR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +// Register Bit Attribute / Bit Access Type +// RO: Read Only (internal change) +// RW: Read / Write +// Attribute: master/PIOC + +/* Register name rule: + R32_* for 32 bits register (UINT32,ULONG) + R16_* for 16 bits register (UINT16,USHORT) + R8_* for 8 bits register (UINT8,UCHAR) + RB_* for bit or bit mask of 8 bit register */ + +/* ********************************************************************************************************************* */ + +#define PIOC_SRAM_BASE (SRAM_BASE+0x4000) // PIOC code RAM base address + +#define PIOC_SFR_BASE PIOC_BASE // PIOC SFR base address + +#define R32_PIOC_SFR (*((volatile unsigned long *)(PIOC_SFR_BASE+0x04))) // RO/RW, PIOC SFR + +#define R8_INDIR_ADDR (*((volatile unsigned char *)(PIOC_SFR_BASE+0x04))) // RO/RW, PIOC indirect address + +#define R8_TMR0_COUNT (*((volatile unsigned char *)(PIOC_SFR_BASE+0x05))) // RO/RW, PIOC timer count + +#define R8_TMR0_CTRL (*((volatile unsigned char *)(PIOC_SFR_BASE+0x06))) // RO/RW, PIOC timer control and GP bit +#define RB_EN_LEVEL1 0x80 // RO/RW, enable IO1 level change to wakeup & action interrupt flag +#define RB_EN_LEVEL0 0x40 // RO/RW, enable IO0 level change to wakeup & action interrupt flag +#define RB_GP_BIT_Y 0x20 // RO/RW, general-purpose bit 1, reset by power on, no effect if system reset or RB_MST_RESET reset +#define RB_GP_BIT_X 0x10 // RO/RW, general-purpose bit 0, reset by power on, no effect if system reset or RB_MST_RESET reset +#define RB_TMR0_MODE 0x08 // RO/RW, timer mode: 0-timer, 1-PWM +#define RB_TMR0_FREQ2 0x04 // RO/RW, timer clock frequency selection 2 +#define RB_TMR0_FREQ1 0x02 // RO/RW, timer clock frequency selection 1 +#define RB_TMR0_FREQ0 0x01 // RO/RW, timer clock frequency selection 0 + +#define R8_TMR0_INIT (*((volatile unsigned char *)(PIOC_SFR_BASE+0x07))) // RO/RW, PIOC timer initial value + + +#define R32_PORT_CFG (*((volatile unsigned long *)(PIOC_SFR_BASE+0x08))) // RO/RW, port status and config + +#define R8_BIT_CYCLE (*((volatile unsigned char *)(PIOC_SFR_BASE+0x08))) // RO/RW, encode bit cycle +#define RB_BIT_TX_O0 0x80 // RO/RW, bit data for IO0 port encode output +#define RB_BIT_CYCLE 0x7F // RO/RW, IO0 port bit data cycle -1 + +#define R8_INDIR_ADDR2 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x09))) // RO/RW, PIOC indirect address 2 + +#define R8_PORT_DIR (*((volatile unsigned char *)(PIOC_SFR_BASE+0x0A))) // RO/RW, IO port direction and mode +//#define RB_PORT_MOD3 0x80 // RO/RW, IO port mode 3 +//#define RB_PORT_MOD2 0x40 // RO/RW, IO port mode 2 +//#define RB_PORT_MOD1 0x20 // RO/RW, IO port mode 1 +//#define RB_PORT_MOD0 0x10 // RO/RW, IO port mode 0 +//#define RB_PORT_PU1 0x08 // RO/RW, IO1 port pullup enable +//#define RB_PORT_PU0 0x04 // RO/RW, IO0 port pullup enable +#define RB_PORT_DIR1 0x02 // RO/RW, IO1 port direction +#define RB_PORT_DIR0 0x01 // RO/RW, IO0 port direction + +#define R8_PORT_IO (*((volatile unsigned char *)(PIOC_SFR_BASE+0x0B))) // RO/RW, IO port input and output +#define RB_PORT_IN_XOR 0x80 // RO/RO, IO0 XOR IO1 port input +#define RB_BIT_RX_I0 0x40 // RO/RO, decoced bit data for IO0 port received +#define RB_PORT_IN1 0x20 // RO/RO, IO1 port input +#define RB_PORT_IN0 0x10 // RO/RO, IO0 port input +#define RB_PORT_XOR1 0x08 // RO/RO, IO1 port output XOR input +#define RB_PORT_XOR0 0x04 // RO/RO, IO0 port output XOR input +#define RB_PORT_OUT1 0x02 // RO/RW, IO1 port output +#define RB_PORT_OUT0 0x01 // RO/RW, IO0 port output + + +#define R32_DATA_CTRL (*((volatile unsigned long *)(PIOC_SFR_BASE+0x1C))) // RW/RW, data control + +#define R8_SYS_CFG (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1C))) // RW/RW, port config +#define RB_INT_REQ 0x80 // RO/RW, PIOC interrupt request action, set 1/0 by PIOC, clear 0 by master write R8_CTRL_RD (no effect) +#define RB_DATA_SW_MR 0x40 // RO/RO, R8_CTRL_RD wait for read status, set 1 by PIOC write R8_CTRL_RD, clear 0 by master read R8_CTRL_RD +#define RB_DATA_MW_SR 0x20 // RO/RO, R8_CTRL_WR wait for read status, set 1 by master write R8_CTRL_WR, clear 0 by PIOC read R8_CTRL_WR +#define RB_MST_CFG_B4 0x10 // RW/RO, config inform bit, default 0 +#define RB_MST_IO_EN1 0x08 // RW/RO, IO1 switch enable, default 0 +#define RB_MST_IO_EN0 0x04 // RW/RO, IO0 switch enable, default 0 +#define RB_MST_RESET 0x02 // RW/RO, force PIOC reset, high action, default 0 +#define RB_MST_CLK_GATE 0x01 // RW/RO, PIOC global clock enable, high action, default 0 + +#define R8_CTRL_RD (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1D))) // RO/RW, data for master read only and PIOC write only + +#define R8_CTRL_WR (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1E))) // RW/RO, data for master write only and PIOC read only + +#define R8_DATA_EXCH (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1F))) // RW/RW, data exchange + + +#define R32_DATA_REG0_3 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x20))) // RW/RW, data buffer 0~3 +#define R8_DATA_REG0 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x20))) // RW/RW, data buffer 0 +#define R8_DATA_REG1 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x21))) // RW/RW, data buffer 1 +#define R8_DATA_REG2 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x22))) // RW/RW, data buffer 2 +#define R8_DATA_REG3 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x23))) // RW/RW, data buffer 3 + +#define R32_DATA_REG4_7 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x24))) // RW/RW, data buffer 4~7 +#define R8_DATA_REG4 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x24))) // RW/RW, data buffer 4 +#define R8_DATA_REG5 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x25))) // RW/RW, data buffer 5 +#define R8_DATA_REG6 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x26))) // RW/RW, data buffer 6 +#define R8_DATA_REG7 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x27))) // RW/RW, data buffer 7 + +#define R32_DATA_REG8_11 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x28))) // RW/RW, data buffer 8~11 +#define R8_DATA_REG8 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x28))) // RW/RW, data buffer 8 +#define R8_DATA_REG9 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x29))) // RW/RW, data buffer 9 +#define R8_DATA_REG10 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2A))) // RW/RW, data buffer 10 +#define R8_DATA_REG11 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2B))) // RW/RW, data buffer 11 + +#define R32_DATA_REG12_15 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x2C))) // RW/RW, data buffer 12~15 +#define R8_DATA_REG12 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2C))) // RW/RW, data buffer 12 +#define R8_DATA_REG13 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2D))) // RW/RW, data buffer 13 +#define R8_DATA_REG14 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2E))) // RW/RW, data buffer 14 +#define R8_DATA_REG15 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2F))) // RW/RW, data buffer 15 + +#define R32_DATA_REG16_19 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x30))) // RW/RW, data buffer 16~19 +#define R8_DATA_REG16 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x30))) // RW/RW, data buffer 16 +#define R8_DATA_REG17 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x31))) // RW/RW, data buffer 17 +#define R8_DATA_REG18 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x32))) // RW/RW, data buffer 18 +#define R8_DATA_REG19 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x33))) // RW/RW, data buffer 19 + +#define R32_DATA_REG20_23 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x34))) // RW/RW, data buffer 20~23 +#define R8_DATA_REG20 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x34))) // RW/RW, data buffer 20 +#define R8_DATA_REG21 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x35))) // RW/RW, data buffer 21 +#define R8_DATA_REG22 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x36))) // RW/RW, data buffer 22 +#define R8_DATA_REG23 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x37))) // RW/RW, data buffer 23 + +#define R32_DATA_REG24_27 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x38))) // RW/RW, data buffer 24~27 +#define R8_DATA_REG24 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x38))) // RW/RW, data buffer 24 +#define R8_DATA_REG25 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x39))) // RW/RW, data buffer 25 +#define R8_DATA_REG26 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3A))) // RW/RW, data buffer 26 +#define R8_DATA_REG27 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3B))) // RW/RW, data buffer 27 + +#define R32_DATA_REG28_31 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x3C))) // RW/RW, data buffer 28~31 +#define R8_DATA_REG28 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3C))) // RW/RW, data buffer 28 +#define R8_DATA_REG29 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3D))) // RW/RW, data buffer 29 +#define R8_DATA_REG30 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3E))) // RW/RW, data buffer 30 +#define R8_DATA_REG31 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3F))) // RW/RW, data buffer 31 + +/* ******************************************************************************************************* */ + +/* PIOC Registers */ +typedef struct +{ + uint32_t RESERVED00; + union { + __IO uint32_t D32_PIOC_SFR ; // RO/RW, PIOC SFR + struct { + __IO uint8_t D8_INDIR_ADDR; // RO/RW, PIOC indirect address + __IO uint8_t D8_TMR0_COUNT; // RO/RW, PIOC timer count + __IO uint8_t D8_TMR0_CTRL; // RO/RW, PIOC timer control and GP bit + __IO uint8_t D8_TMR0_INIT; // RO/RW, PIOC timer initial value + } ; + } ; + union { + __IO uint32_t D32_PORT_CFG ; // RO/RW, port status and config + struct { + __IO uint8_t D8_BIT_CYCLE; // RO/RW, encode bit cycle + __IO uint8_t D8_INDIR_ADDR2; // RO/RW, PIOC indirect address 2 + __IO uint8_t D8_PORT_DIR; // RO/RW, IO port direction and mode + __IO uint8_t D8_PORT_IO; // RO/RW, IO port input and output + } ; + } ; + uint32_t RESERVED0C; + uint32_t RESERVED10; + uint32_t RESERVED14; + uint32_t RESERVED18; + union { + __IO uint32_t D32_DATA_CTRL ; // RW/RW, data control + struct { + __IO uint8_t D8_SYS_CFG; // RW/RW, port config + __IO uint8_t D8_CTRL_RD; // RO/RW, data for master read only and PIOC write only + __IO uint8_t D8_CTRL_WR; // RW/RO, data for master write only and PIOC read only + __IO uint8_t D8_DATA_EXCH; // RW/RW, data exchange + } ; + } ; + union { + __IO uint32_t D32_DATA_REG0_3 ; // RW/RW, data buffer 0~3 + struct { + __IO uint8_t D8_DATA_REG0; // RW/RW, data buffer 0 + __IO uint8_t D8_DATA_REG1; // RW/RW, data buffer 1 + __IO uint8_t D8_DATA_REG2; // RW/RW, data buffer 2 + __IO uint8_t D8_DATA_REG3; // RW/RW, data buffer 3 + } ; + __IO uint16_t D16_DATA_REG0_1 ; // RW/RW, data buffer 0~1 + } ; + union { + __IO uint32_t D32_DATA_REG4_7 ; // RW/RW, data buffer 4~7 + struct { + __IO uint8_t D8_DATA_REG4; // RW/RW, data buffer 4 + __IO uint8_t D8_DATA_REG5; // RW/RW, data buffer 5 + __IO uint8_t D8_DATA_REG6; // RW/RW, data buffer 6 + __IO uint8_t D8_DATA_REG7; // RW/RW, data buffer 7 + } ; + } ; + union { + __IO uint32_t D32_DATA_REG8_11 ; // RW/RW, data buffer 8~11 + struct { + __IO uint8_t D8_DATA_REG8; // RW/RW, data buffer 8 + __IO uint8_t D8_DATA_REG9; // RW/RW, data buffer 9 + __IO uint8_t D8_DATA_REG10; // RW/RW, data buffer 10 + __IO uint8_t D8_DATA_REG11; // RW/RW, data buffer 11 + } ; + } ; + union { + __IO uint32_t D32_DATA_REG12_15 ; // RW/RW, data buffer 12~15 + struct { + __IO uint8_t D8_DATA_REG12; // RW/RW, data buffer 12 + __IO uint8_t D8_DATA_REG13; // RW/RW, data buffer 13 + __IO uint8_t D8_DATA_REG14; // RW/RW, data buffer 14 + __IO uint8_t D8_DATA_REG15; // RW/RW, data buffer 15 + } ; + } ; + union { + __IO uint32_t D32_DATA_REG16_19 ; // RW/RW, data buffer 16~19 + struct { + __IO uint8_t D8_DATA_REG16; // RW/RW, data buffer 16 + __IO uint8_t D8_DATA_REG17; // RW/RW, data buffer 17 + __IO uint8_t D8_DATA_REG18; // RW/RW, data buffer 18 + __IO uint8_t D8_DATA_REG19; // RW/RW, data buffer 19 + } ; + } ; + union { + __IO uint32_t D32_DATA_REG20_23 ; // RW/RW, data buffer 20~23 + struct { + __IO uint8_t D8_DATA_REG20; // RW/RW, data buffer 20 + __IO uint8_t D8_DATA_REG21; // RW/RW, data buffer 21 + __IO uint8_t D8_DATA_REG22; // RW/RW, data buffer 22 + __IO uint8_t D8_DATA_REG23; // RW/RW, data buffer 23 + } ; + } ; + union { + __IO uint32_t D32_DATA_REG24_27 ; // RW/RW, data buffer 24~27 + struct { + __IO uint8_t D8_DATA_REG24; // RW/RW, data buffer 24 + __IO uint8_t D8_DATA_REG25; // RW/RW, data buffer 25 + __IO uint8_t D8_DATA_REG26; // RW/RW, data buffer 26 + __IO uint8_t D8_DATA_REG27; // RW/RW, data buffer 27 + } ; + } ; + union { + __IO uint32_t D32_DATA_REG28_31 ; // RW/RW, data buffer 28~31 + struct { + __IO uint8_t D8_DATA_REG28; // RW/RW, data buffer 28 + __IO uint8_t D8_DATA_REG29; // RW/RW, data buffer 29 + __IO uint8_t D8_DATA_REG30; // RW/RW, data buffer 30 + __IO uint8_t D8_DATA_REG31; // RW/RW, data buffer 31 + } ; + } ; +} PIOC_TypeDef; + +#define PIOC ((PIOC_TypeDef *)PIOC_BASE) + +#ifdef __cplusplus +} +#endif + +#endif // __PIOC_SFR_H__ diff --git a/Code/DAP_X033/Peripheral/inc/ch32x035.h b/Code/DAP_X033/Peripheral/inc/ch32x035.h new file mode 100644 index 0000000..aacca23 --- /dev/null +++ b/Code/DAP_X033/Peripheral/inc/ch32x035.h @@ -0,0 +1,2963 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : CH32X035 Device Peripheral Access Layer Header File. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_H +#define __CH32X035_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define __MPU_PRESENT 0 /* Other CH32 devices does not provide an MPU */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + +#define HSI_VALUE ((uint32_t)48000000) /* Value of the Internal oscillator in Hz */ + +/* Standard Peripheral Library version number */ +#define __STDPERIPH_VERSION_MAIN (0x01) /* [15:8] main version */ +#define __STDPERIPH_VERSION_SUB (0x04) /* [7:0] sub version */ +#define __STDPERIPH_VERSION ((__STDPERIPH_VERSION_MAIN << 8)\ + |(__STDPERIPH_VERSION_SUB << 0)) + + +/* Interrupt Number Definition, according to the selected device */ +typedef enum IRQn +{ + /****** RISC-V Processor Exceptions Numbers *******************************************************/ + NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */ + EXC_IRQn = 3, /* 3 Exception Interrupt */ + Ecall_M_Mode_IRQn = 5, /* 5 Ecall M Mode Interrupt */ + Ecall_U_Mode_IRQn = 8, /* 8 Ecall U Mode Interrupt */ + Break_Point_IRQn = 9, /* 9 Break Point Interrupt */ + SysTicK_IRQn = 12, /* 12 System timer Interrupt */ + Software_IRQn = 14, /* 14 software Interrupt */ + + /****** RISC-V specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 16, /* Window WatchDog Interrupt */ + PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ + FLASH_IRQn = 18, /* FLASH global Interrupt */ + EXTI7_0_IRQn = 20, /* External Line[7:0] Interrupts */ + AWU_IRQn = 21, /* AWU global Interrupt */ + DMA1_Channel1_IRQn = 22, /* DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 23, /* DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 24, /* DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 25, /* DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 26, /* DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 27, /* DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 28, /* DMA1 Channel 7 global Interrupt */ + ADC1_IRQn = 29, /* ADC1 global Interrupt */ + I2C1_EV_IRQn = 30, /* I2C1 Event Interrupt */ + I2C1_ER_IRQn = 31, /* I2C1 Error Interrupt */ + USART1_IRQn = 32, /* USART1 global Interrupt */ + SPI1_IRQn = 33, /* SPI1 global Interrupt */ + TIM1_BRK_IRQn = 34, /* TIM1 Break Interrupt */ + TIM1_UP_IRQn = 35, /* TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 36, /* TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 37, /* TIM1 Capture Compare Interrupt */ + TIM2_UP_IRQn = 38, /* TIM2 Update Interrupt */ + USART2_IRQn = 39, /* USART2 global Interrupt */ + EXTI15_8_IRQn = 40, /* External Line[15:8] Interrupts */ + EXTI25_16_IRQn = 41, /* External Line[25:16] Interrupts */ + USART3_IRQn = 42, /* USART3 global Interrupt */ + USART4_IRQn = 43, /* USART4 global Interrupt */ + DMA1_Channel8_IRQn = 44, /* DMA1 Channel 8 global Interrupt */ + USBFS_IRQn = 45, /* USBFS Host/Device global Interrupt */ + USBFSWakeUp_IRQn = 46, /* USBFS Host/Device WakeUp Interrupt */ + PIOC_IRQn = 47, /* PIOC global Interrupt */ + OPA_IRQn = 48, /* OPA global Interrupt */ + USBPD_IRQn = 49, /* USBPD global Interrupt */ + USBPDWakeUp_IRQn = 50, /* USBPD WakeUp Interrupt */ + TIM2_CC_IRQn = 51, /* TIM2 Capture Compare Interrupt */ + TIM2_TRG_COM_IRQn = 52, /* TIM2 Trigger and Commutation Interrupt */ + TIM2_BRK_IRQn = 53, /* TIM2 Break Interrupt */ + TIM3_IRQn = 54, /* TIM3 global Interrupt */ +} IRQn_Type; + +#define HardFault_IRQn EXC_IRQn + +#include +#include "core_riscv.h" +#include "system_ch32x035.h" + +/* Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSI_Value HSI_VALUE + +/* Analog to Digital Converter */ +typedef struct +{ + __IO uint32_t STATR; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t SAMPTR1; + __IO uint32_t SAMPTR2; + __IO uint32_t IOFR1; + __IO uint32_t IOFR2; + __IO uint32_t IOFR3; + __IO uint32_t IOFR4; + __IO uint32_t WDHTR; + __IO uint32_t WDLTR; + __IO uint32_t RSQR1; + __IO uint32_t RSQR2; + __IO uint32_t RSQR3; + __IO uint32_t ISQR; + __IO uint32_t IDATAR1; + __IO uint32_t IDATAR2; + __IO uint32_t IDATAR3; + __IO uint32_t IDATAR4; + __IO uint32_t RDATAR; + __IO uint32_t CTLR3; + __IO uint32_t WDTR1; + __IO uint32_t WDTR2; + __IO uint32_t WDTR3; +} ADC_TypeDef; + +/* DMA Channel Controller */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t CNTR; + __IO uint32_t PADDR; + __IO uint32_t MADDR; +} DMA_Channel_TypeDef; + +/* DMA Controller */ +typedef struct +{ + __IO uint32_t INTFR; + __IO uint32_t INTFCR; +} DMA_TypeDef; + +/* External Interrupt/Event Controller */ +typedef struct +{ + __IO uint32_t INTENR; + __IO uint32_t EVENR; + __IO uint32_t RTENR; + __IO uint32_t FTENR; + __IO uint32_t SWIEVR; + __IO uint32_t INTFR; +} EXTI_TypeDef; + +/* FLASH Registers */ +typedef struct +{ + __IO uint32_t ACTLR; + __IO uint32_t KEYR; + __IO uint32_t OBKEYR; + __IO uint32_t STATR; + __IO uint32_t CTLR; + __IO uint32_t ADDR; + uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WPR; + __IO uint32_t MODEKEYR; + __IO uint32_t BOOT_MODEKEYR; +} FLASH_TypeDef; + +/* Option Bytes Registers */ +typedef struct +{ + __IO uint16_t RDPR; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRPR0; + __IO uint16_t WRPR1; + __IO uint16_t WRPR2; + __IO uint16_t WRPR3; +} OB_TypeDef; + +/* General Purpose I/O */ +typedef struct +{ + __IO uint32_t CFGLR; + __IO uint32_t CFGHR; + __IO uint32_t INDR; + __IO uint32_t OUTDR; + __IO uint32_t BSHR; + __IO uint32_t BCR; + __IO uint32_t LCKR; + __IO uint32_t CFGXR; + __IO uint32_t BSXR; +} GPIO_TypeDef; + +/* Alternate Function I/O */ +typedef struct +{ + uint32_t RESERVED0; + __IO uint32_t PCFR1; + __IO uint32_t EXTICR[2]; + uint32_t RESERVED1; + uint32_t RESERVED2; + __IO uint32_t CTLR; +} AFIO_TypeDef; + +/* Inter Integrated Circuit Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t OADDR1; + uint16_t RESERVED2; + __IO uint16_t OADDR2; + uint16_t RESERVED3; + __IO uint16_t DATAR; + uint16_t RESERVED4; + __IO uint16_t STAR1; + uint16_t RESERVED5; + __IO uint16_t STAR2; + uint16_t RESERVED6; + __IO uint16_t CKCFGR; + uint16_t RESERVED7; +} I2C_TypeDef; + +/* Independent WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t PSCR; + __IO uint32_t RLDR; + __IO uint32_t STATR; +} IWDG_TypeDef; + +/* Power Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/* Reset and Clock Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR0; + __IO uint32_t RESERVED0; + __IO uint32_t APB2PRSTR; + __IO uint32_t APB1PRSTR; + __IO uint32_t AHBPCENR; + __IO uint32_t APB2PCENR; + __IO uint32_t APB1PCENR; + __IO uint32_t RESERVED1; + __IO uint32_t RSTSCKR; + __IO uint32_t AHBRSTR; +} RCC_TypeDef; + +/* Serial Peripheral Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t STATR; + uint16_t RESERVED2; + __IO uint16_t DATAR; + uint16_t RESERVED3; + __IO uint16_t CRCR; + uint16_t RESERVED4; + __IO uint16_t RCRCR; + uint16_t RESERVED5; + __IO uint16_t TCRCR; + uint16_t RESERVED6; + uint32_t RESERVED7; + uint32_t RESERVED8; + __IO uint16_t HSCR; + uint16_t RESERVED9; +} SPI_TypeDef; + +/* TIM */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t SMCFGR; + uint16_t RESERVED2; + __IO uint16_t DMAINTENR; + uint16_t RESERVED3; + __IO uint16_t INTFR; + uint16_t RESERVED4; + __IO uint16_t SWEVGR; + uint16_t RESERVED5; + __IO uint16_t CHCTLR1; + uint16_t RESERVED6; + __IO uint16_t CHCTLR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + __IO uint16_t CNT; + uint16_t RESERVED9; + __IO uint16_t PSC; + uint16_t RESERVED10; + __IO uint16_t ATRLR; + uint16_t RESERVED11; + __IO uint16_t RPTCR; + uint16_t RESERVED12; + union + { + __IO uint32_t CH1CVR_R32; + struct + { + __IO uint16_t CH1CVR; + uint16_t RESERVED13; + }; + }; + union + { + __IO uint32_t CH2CVR__R32; + struct + { + __IO uint16_t CH2CVR; + uint16_t RESERVED14; + }; + }; + union + { + __IO uint32_t CH3CVR__R32; + struct + { + __IO uint16_t CH3CVR; + uint16_t RESERVED15; + }; + }; + union + { + __IO uint32_t CH4CVR__R32; + struct + { + __IO uint16_t CH4CVR; + uint16_t RESERVED16; + }; + }; + __IO uint16_t BDTR; + uint16_t RESERVED17; + __IO uint16_t DMACFGR; + uint16_t RESERVED18; + __IO uint16_t DMAADR; + uint16_t RESERVED19; + __IO uint16_t SPEC; + uint16_t RESERVED20; +} TIM_TypeDef; + +/* Universal Synchronous Asynchronous Receiver Transmitter */ +typedef struct +{ + __IO uint16_t STATR; + uint16_t RESERVED0; + __IO uint16_t DATAR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CTLR1; + uint16_t RESERVED3; + __IO uint16_t CTLR2; + uint16_t RESERVED4; + __IO uint16_t CTLR3; + uint16_t RESERVED5; + __IO uint16_t GPR; + uint16_t RESERVED6; +} USART_TypeDef; + +/* Window WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR; + __IO uint32_t STATR; +} WWDG_TypeDef; + +/* OPA Registers */ +typedef struct +{ + __IO uint16_t CFGR1; + __IO uint16_t CFGR2; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t OPAKEY; + __IO uint32_t CMPKEY; + __IO uint32_t POLLKEY; +} OPA_TypeDef; + +/* AWU Registers */ +typedef struct +{ + __IO uint32_t CSR; + __IO uint32_t WR; + __IO uint32_t PSC; +} AWU_TypeDef; + +/* PD Registers */ + +typedef struct +{ + union + { + __IO uint32_t USBPD_CONFIG; + struct + { + __IO uint16_t CONFIG; + __IO uint16_t BMC_CLK_CNT; + }; + }; + union + { + __IO uint32_t USBPD_CONTROL; + struct + { + union + { + __IO uint16_t R16_CONTROL; + struct + { + __IO uint8_t CONTROL; + __IO uint8_t TX_SEL; + }; + }; + __IO uint16_t BMC_TX_SZ; + }; + }; + union + { + __IO uint32_t USBPD_STATUS; + struct + { + union + { + __IO uint16_t R16_STATUS; + struct + { + __IO uint8_t DATA_BUF; + __IO uint8_t STATUS; + }; + }; + __IO uint16_t BMC_BYTE_CNT; + }; + }; + union + { + __IO uint32_t USBPD_PORT; + struct + { + __IO uint16_t PORT_CC1; + __IO uint16_t PORT_CC2; + }; + }; + union + { + __IO uint32_t USBPD_DMA; + struct + { + __IO uint16_t DMA; + __IO uint16_t RESERVED; + }; + }; +} USBPD_TypeDef; + +/* USBFS Registers */ +typedef struct +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t UDEV_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + uint8_t RESERVED0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint32_t RX_LEN; + __IO uint8_t UEP4_1_MOD; + __IO uint8_t UEP2_3_MOD; + __IO uint8_t UEP567_MOD; + uint8_t RESERVED1; + __IO uint32_t UEP0_DMA; + __IO uint32_t UEP1_DMA; + __IO uint32_t UEP2_DMA; + __IO uint32_t UEP3_DMA; + union{ + __IO uint32_t UEP0_CTRL; + struct{ + __IO uint16_t UEP0_TX_LEN; + __IO uint16_t UEP0_CTRL_H; + }; + }; + union{ + __IO uint32_t UEP1_CTRL; + struct{ + __IO uint16_t UEP1_TX_LEN; + __IO uint16_t UEP1_CTRL_H; + }; + }; + union{ + __IO uint32_t UEP2_CTRL; + struct{ + __IO uint16_t UEP2_TX_LEN; + __IO uint16_t UEP2_CTRL_H; + }; + }; + union{ + __IO uint32_t UEP3_CTRL; + struct{ + __IO uint16_t UEP3_TX_LEN; + __IO uint16_t UEP3_CTRL_H; + }; + }; + union{ + __IO uint32_t UEP4_CTRL; + struct{ + __IO uint16_t UEP4_TX_LEN; + __IO uint16_t UEP4_CTRL_H; + }; + }; + uint32_t RESERVED2; + uint32_t RESERVED3; + uint32_t RESERVED4; + uint32_t RESERVED5; + uint32_t RESERVED6; + uint32_t RESERVED7; + uint32_t RESERVED8; + uint32_t RESERVED9; + __IO uint32_t UEP5_DMA; + __IO uint32_t UEP6_DMA; + __IO uint32_t UEP7_DMA; + uint32_t RESERVED10; + union{ + __IO uint32_t UEP5_CTRL; + struct{ + __IO uint16_t UEP5_TX_LEN; + __IO uint16_t UEP5_CTRL_H; + }; + }; + union{ + __IO uint32_t UEP6_CTRL; + struct{ + __IO uint16_t UEP6_TX_LEN; + __IO uint16_t UEP6_CTRL_H; + }; + }; + union{ + __IO uint32_t UEP7_CTRL; + struct{ + __IO uint16_t UEP7_TX_LEN; + __IO uint16_t UEP7_CTRL_H; + }; + }; + __IO uint32_t UEPX_MOD; +} USBFSD_TypeDef; + +typedef struct +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t HOST_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + uint8_t RESERVED0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + uint16_t RESERVED1; + uint8_t RESERVED2; + __IO uint8_t HOST_EP_MOD; + uint16_t RESERVED3; + uint32_t RESERVED4; + uint32_t RESERVED5; + __IO uint16_t HOST_RX_DMA; + uint16_t RESERVED6; + __IO uint16_t HOST_TX_DMA; + uint16_t RESERVED7; + uint32_t RESERVED8; + uint16_t RESERVED9; + __IO uint8_t HOST_SETUP; + uint8_t RESERVED10; + __IO uint8_t HOST_EP_PID; + uint8_t RESERVED11; + __IO uint8_t HOST_RX_CTRL; + uint8_t RESERVED12; + __IO uint8_t HOST_TX_LEN; + uint8_t RESERVED13; + __IO uint8_t HOST_TX_CTRL; + uint8_t RESERVED14; +} USBFSH_TypeDef; + +/* Peripheral memory map */ +#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ + +#define APB1PERIPH_BASE (PERIPH_BASE) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define USART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define DMA1_Channel8_BASE (AHBPERIPH_BASE + 0x0094) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) +#define USBFS_BASE (AHBPERIPH_BASE + 0x3400) +#define OPA_BASE (AHBPERIPH_BASE + 0x6000) +#define AWU_BASE (AHBPERIPH_BASE + 0x6400) +#define PIOC_BASE (AHBPERIPH_BASE + 0x6C00) +#define USBPD_BASE (AHBPERIPH_BASE + 0x7000) + +#define OB_BASE ((uint32_t)0x1FFFF800) + +/* Peripheral declaration */ +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define TIM3 ((TIM_TypeDef *)TIM3_BASE) +#define WWDG ((WWDG_TypeDef *)WWDG_BASE) +#define IWDG ((IWDG_TypeDef *)IWDG_BASE) +#define USART2 ((USART_TypeDef *)USART2_BASE) +#define USART3 ((USART_TypeDef *)USART3_BASE) +#define USART4 ((USART_TypeDef *)USART4_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define PWR ((PWR_TypeDef *)PWR_BASE) + +#define AFIO ((AFIO_TypeDef *)AFIO_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define TKey1 ((ADC_TypeDef *)ADC1_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) + +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define DMA1_Channel8 ((DMA_Channel_TypeDef *)DMA1_Channel8_BASE) +#define RCC ((RCC_TypeDef *)RCC_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define USBFSD ((USBFSD_TypeDef *)USBFS_BASE) +#define USBFSH ((USBFSH_TypeDef *)USBFS_BASE) +#define OPA ((OPA_TypeDef *)OPA_BASE) +#define AWU ((AWU_TypeDef *)AWU_BASE) +#define USBPD ((USBPD_TypeDef *)USBPD_BASE) + +#define OB ((OB_TypeDef *)OB_BASE) + + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* Analog to Digital Converter */ +/******************************************************************************/ + +/******************** Bit definition for ADC_STATR register ********************/ +#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */ +#define ADC_EOC ((uint8_t)0x02) /* End of conversion */ +#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */ +#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */ +#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ + +/******************* Bit definition for ADC_CTLR1 register ********************/ +#define ADC_AWDCH ((uint32_t)0x0000000F) /* AWDCH[3:0] bits (Analog watchdog channel select bits) */ +#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ + +#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ +#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ +#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ +#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ +#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ +#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ +#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ +#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ + +#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ +#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ + +#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ +#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ +#define ADC_TKENABLE ((uint32_t)0x01000000) /* TKEN mode enable */ + +/******************* Bit definition for ADC_CTLR2 register ********************/ +#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ +#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ +#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ +#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ + +#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ + +#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ +#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ +#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ + +#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ +#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ +#define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ + +/****************** Bit definition for ADC_SAMPTR1 register *******************/ +#define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMP10_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP10_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP10_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP11 ((uint32_t)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMP11_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP11_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP11_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP12 ((uint32_t)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMP12_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP12_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP12_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP13 ((uint32_t)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMP13_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP13_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP13_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP14 ((uint32_t)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMP14_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP14_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP14_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP15 ((uint32_t)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SMP15_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP15_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP15_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */ + +/****************** Bit definition for ADC_SAMPTR2 register *******************/ +#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ + +#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ +#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ +#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ + +/****************** Bit definition for ADC_IOFR1 register *******************/ +#define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_IOFR2 register *******************/ +#define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_IOFR3 register *******************/ +#define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_IOFR4 register *******************/ +#define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_WDHTR register ********************/ +#define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */ + +/******************* Bit definition for ADC_WDLTR register ********************/ +#define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */ + +/******************* Bit definition for ADC_RSQR1 register *******************/ +#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ +#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ + +/******************* Bit definition for ADC_RSQR2 register *******************/ +#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_RSQR3 register *******************/ +#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_ISQR register *******************/ +#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ +#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ + +/******************* Bit definition for ADC_IDATAR1 register *******************/ +#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR2 register *******************/ +#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR3 register *******************/ +#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR4 register *******************/ +#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************** Bit definition for ADC_RDATAR register ********************/ +#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ + +/******************** Bit definition for ADC_CTLR3 register ********************/ +#define ADC_CTLR3_CLK_DIV ((uint32_t)0x0000000F) /* CLK_DIVL[3:0] bits */ +#define ADC_CTLR3_CLK_DIV_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_CTLR3_CLK_DIV_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_CTLR3_CLK_DIV_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_CTLR3_CLK_DIV_3 ((uint32_t)0x00000008) /* Bit 3 */ + +#define ADC_CTLR3_AWD_SCAN ((uint32_t)0x00000200) /* Analog watchdog Scan enable */ +#define ADC_CTLR3_AWD0_RST_EN ((uint32_t)0x00001000) /* Watchdog0 Reset Enable */ +#define ADC_CTLR3_AWD1_RST_EN ((uint32_t)0x00002000) /* Watchdog1 Reset Enable */ +#define ADC_CTLR3_AWD2_RST_EN ((uint32_t)0x00004000) /* Watchdog2 Reset Enable */ +#define ADC_CTLR3_AWD3_RST_EN ((uint32_t)0x00008000) /* Watchdog3 Reset Enable */ + +/******************** Bit definition for ADC_WDTR1 register ********************/ +#define ADC_WDTR1_LTR1 ((uint32_t)0x00000FFF) /* Analog watchdog1 low threshold */ +#define ADC_WDTR1_HTR1 ((uint32_t)0x00FFF000) /* Analog watchdog1 high threshold */ + +/******************** Bit definition for ADC_WDTR2 register ********************/ +#define ADC_WDTR2_LTR2 ((uint32_t)0x00000FFF) /* Analog watchdog2 low threshold */ +#define ADC_WDTR2_HTR2 ((uint32_t)0x00FFF000) /* Analog watchdog2 high threshold */ + +/******************** Bit definition for ADC_WDTR3 register ********************/ +#define ADC_WDTR3_LTR3 ((uint32_t)0x00000FFF) /* Analog watchdog3 low threshold */ +#define ADC_WDTR3_HTR3 ((uint32_t)0x00FFF000) /* Analog watchdog3 high threshold */ + +/******************************************************************************/ +/* DMA Controller */ +/******************************************************************************/ + +/******************* Bit definition for DMA_INTFR register ********************/ +#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ +#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ +#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ +#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ +#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ +#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ +#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ +#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ +#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ +#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ +#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ +#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ +#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ +#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ +#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ +#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ +#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ +#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ +#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ +#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ +#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ +#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ +#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ +#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ +#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ +#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ +#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ +#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ +#define DMA_GIF8 ((uint32_t)0x10000000) /* Channel 8 Global interrupt flag */ +#define DMA_TCIF8 ((uint32_t)0x20000000) /* Channel 8 Transfer Complete flag */ +#define DMA_HTIF8 ((uint32_t)0x40000000) /* Channel 8 Half Transfer flag */ +#define DMA_TEIF8 ((uint32_t)0x80000000) /* Channel 8 Transfer Error flag */ + +/******************* Bit definition for DMA_INTFCR register *******************/ +#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ +#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ +#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ +#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ +#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ +#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ +#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ +#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ +#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ +#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ +#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ +#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ +#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ +#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ +#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ +#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ +#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ +#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ +#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ +#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ +#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ +#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ +#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ +#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ +#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ +#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ +#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ +#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ +#define DMA_CGIF8 ((uint32_t)0x10000000) /* Channel 8 Global interrupt clear */ +#define DMA_CTCIF8 ((uint32_t)0x20000000) /* Channel 8 Transfer Complete clear */ +#define DMA_CHTIF8 ((uint32_t)0x40000000) /* Channel 8 Half Transfer clear */ +#define DMA_CTEIF8 ((uint32_t)0x80000000) /* Channel 8 Transfer Error clear */ + +/******************* Bit definition for DMA_CFGR1 register *******************/ +#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ +#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ +#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR2 register *******************/ +#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR3 register *******************/ +#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFG4 register *******************/ +#define DMA_CFG4_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG4_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG4_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG4_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/****************** Bit definition for DMA_CFG5 register *******************/ +#define DMA_CFG5_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG5_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG5_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG5_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/******************* Bit definition for DMA_CFG6 register *******************/ +#define DMA_CFG6_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG6_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG6_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG6_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFG7 register *******************/ +#define DMA_CFG7_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG7_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG7_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG7_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/******************* Bit definition for DMA_CFG8 register *******************/ +#define DMA_CFG8_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG8_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG8_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG8_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG8_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG8_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG8_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG8_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG8_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG8_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG8_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG8_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG8_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG8_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG8_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG8_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG8_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG8_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/****************** Bit definition for DMA_CNTR1 register ******************/ +#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR2 register ******************/ +#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR3 register ******************/ +#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR4 register ******************/ +#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR5 register ******************/ +#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR6 register ******************/ +#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR7 register ******************/ +#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR8 register ******************/ +#define DMA_CNTR8_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_PADDR1 register *******************/ +#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR2 register *******************/ +#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR3 register *******************/ +#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR4 register *******************/ +#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR5 register *******************/ +#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR6 register *******************/ +#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR7 register *******************/ +#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR8 register *******************/ +#define DMA_PADDR8_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_MADDR1 register *******************/ +#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR2 register *******************/ +#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR3 register *******************/ +#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR4 register *******************/ +#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR5 register *******************/ +#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR6 register *******************/ +#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR7 register *******************/ +#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR8 register *******************/ +#define DMA_MADDR8_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/******************************************************************************/ +/* External Interrupt/Event Controller */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_INTENR register *******************/ +#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ +#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ +#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ +#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ +#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ +#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ +#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ +#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ +#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ +#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ +#define EXTI_INTENR_MR10 ((uint32_t)0x00000400) /* Interrupt Mask on line 10 */ +#define EXTI_INTENR_MR11 ((uint32_t)0x00000800) /* Interrupt Mask on line 11 */ +#define EXTI_INTENR_MR12 ((uint32_t)0x00001000) /* Interrupt Mask on line 12 */ +#define EXTI_INTENR_MR13 ((uint32_t)0x00002000) /* Interrupt Mask on line 13 */ +#define EXTI_INTENR_MR14 ((uint32_t)0x00004000) /* Interrupt Mask on line 14 */ +#define EXTI_INTENR_MR15 ((uint32_t)0x00008000) /* Interrupt Mask on line 15 */ +#define EXTI_INTENR_MR16 ((uint32_t)0x00010000) /* Interrupt Mask on line 16 */ +#define EXTI_INTENR_MR17 ((uint32_t)0x00020000) /* Interrupt Mask on line 17 */ +#define EXTI_INTENR_MR18 ((uint32_t)0x00040000) /* Interrupt Mask on line 18 */ +#define EXTI_INTENR_MR19 ((uint32_t)0x00080000) /* Interrupt Mask on line 19 */ +#define EXTI_INTENR_MR20 ((uint32_t)0x00100000) /* Interrupt Mask on line 20 */ +#define EXTI_INTENR_MR21 ((uint32_t)0x00200000) /* Interrupt Mask on line 21 */ +#define EXTI_INTENR_MR22 ((uint32_t)0x00400000) /* Interrupt Mask on line 22 */ +#define EXTI_INTENR_MR23 ((uint32_t)0x00800000) /* Interrupt Mask on line 23 */ +#define EXTI_INTENR_MR24 ((uint32_t)0x01000000) /* Interrupt Mask on line 24 */ +#define EXTI_INTENR_MR25 ((uint32_t)0x02000000) /* Interrupt Mask on line 25 */ +#define EXTI_INTENR_MR26 ((uint32_t)0x04000000) /* Interrupt Mask on line 26 */ +#define EXTI_INTENR_MR27 ((uint32_t)0x08000000) /* Interrupt Mask on line 27 */ +#define EXTI_INTENR_MR28 ((uint32_t)0x10000000) /* Interrupt Mask on line 28 */ +#define EXTI_INTENR_MR29 ((uint32_t)0x20000000) /* Interrupt Mask on line 29 */ + +/******************* Bit definition for EXTI_EVENR register *******************/ +#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ +#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ +#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ +#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ +#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ +#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ +#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ +#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ +#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ +#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ +#define EXTI_EVENR_MR10 ((uint32_t)0x00000400) /* Event Mask on line 10 */ +#define EXTI_EVENR_MR11 ((uint32_t)0x00000800) /* Event Mask on line 11 */ +#define EXTI_EVENR_MR12 ((uint32_t)0x00001000) /* Event Mask on line 12 */ +#define EXTI_EVENR_MR13 ((uint32_t)0x00002000) /* Event Mask on line 13 */ +#define EXTI_EVENR_MR14 ((uint32_t)0x00004000) /* Event Mask on line 14 */ +#define EXTI_EVENR_MR15 ((uint32_t)0x00008000) /* Event Mask on line 15 */ +#define EXTI_EVENR_MR16 ((uint32_t)0x00010000) /* Event Mask on line 16 */ +#define EXTI_EVENR_MR17 ((uint32_t)0x00020000) /* Event Mask on line 17 */ +#define EXTI_EVENR_MR18 ((uint32_t)0x00040000) /* Event Mask on line 18 */ +#define EXTI_EVENR_MR19 ((uint32_t)0x00080000) /* Event Mask on line 19 */ +#define EXTI_EVENR_MR20 ((uint32_t)0x00100000) /* Event Mask on line 20 */ +#define EXTI_EVENR_MR21 ((uint32_t)0x00200000) /* Event Mask on line 21 */ +#define EXTI_EVENR_MR22 ((uint32_t)0x00400000) /* Event Mask on line 22 */ +#define EXTI_EVENR_MR23 ((uint32_t)0x00800000) /* Event Mask on line 23 */ +#define EXTI_EVENR_MR24 ((uint32_t)0x01000000) /* Event Mask on line 24 */ +#define EXTI_EVENR_MR25 ((uint32_t)0x02000000) /* Event Mask on line 25 */ +#define EXTI_EVENR_MR26 ((uint32_t)0x04000000) /* Event Mask on line 26 */ +#define EXTI_EVENR_MR27 ((uint32_t)0x08000000) /* Event Mask on line 27 */ +#define EXTI_EVENR_MR28 ((uint32_t)0x10000000) /* Event Mask on line 28 */ +#define EXTI_EVENR_MR29 ((uint32_t)0x20000000) /* Event Mask on line 29 */ + +/****************** Bit definition for EXTI_RTENR register *******************/ +#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ +#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ +#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ +#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ +#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ +#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ +#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ +#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ +#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ +#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ +#define EXTI_RTENR_TR10 ((uint32_t)0x00000400) /* Rising trigger event configuration bit of line 10 */ +#define EXTI_RTENR_TR11 ((uint32_t)0x00000800) /* Rising trigger event configuration bit of line 11 */ +#define EXTI_RTENR_TR12 ((uint32_t)0x00001000) /* Rising trigger event configuration bit of line 12 */ +#define EXTI_RTENR_TR13 ((uint32_t)0x00002000) /* Rising trigger event configuration bit of line 13 */ +#define EXTI_RTENR_TR14 ((uint32_t)0x00004000) /* Rising trigger event configuration bit of line 14 */ +#define EXTI_RTENR_TR15 ((uint32_t)0x00008000) /* Rising trigger event configuration bit of line 15 */ +#define EXTI_RTENR_TR16 ((uint32_t)0x00010000) /* Rising trigger event configuration bit of line 16 */ +#define EXTI_RTENR_TR17 ((uint32_t)0x00020000) /* Rising trigger event configuration bit of line 17 */ +#define EXTI_RTENR_TR18 ((uint32_t)0x00040000) /* Rising trigger event configuration bit of line 18 */ +#define EXTI_RTENR_TR19 ((uint32_t)0x00080000) /* Rising trigger event configuration bit of line 19 */ +#define EXTI_RTENR_TR20 ((uint32_t)0x00100000) /* Rising trigger event configuration bit of line 20 */ +#define EXTI_RTENR_TR21 ((uint32_t)0x00200000) /* Rising trigger event configuration bit of line 21 */ +#define EXTI_RTENR_TR22 ((uint32_t)0x00400000) /* Rising trigger event configuration bit of line 22 */ +#define EXTI_RTENR_TR23 ((uint32_t)0x00800000) /* Rising trigger event configuration bit of line 23 */ +#define EXTI_RTENR_TR24 ((uint32_t)0x01000000) /* Rising trigger event configuration bit of line 24 */ +#define EXTI_RTENR_TR25 ((uint32_t)0x02000000) /* Rising trigger event configuration bit of line 25 */ +#define EXTI_RTENR_TR26 ((uint32_t)0x04000000) /* Rising trigger event configuration bit of line 26 */ +#define EXTI_RTENR_TR27 ((uint32_t)0x08000000) /* Rising trigger event configuration bit of line 27 */ +#define EXTI_RTENR_TR28 ((uint32_t)0x10000000) /* Rising trigger event configuration bit of line 28 */ +#define EXTI_RTENR_TR29 ((uint32_t)0x20000000) /* Rising trigger event configuration bit of line 29 */ + +/****************** Bit definition for EXTI_FTENR register *******************/ +#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ +#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ +#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ +#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ +#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ +#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ +#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ +#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ +#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ +#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ +#define EXTI_FTENR_TR10 ((uint32_t)0x00000400) /* Falling trigger event configuration bit of line 10 */ +#define EXTI_FTENR_TR11 ((uint32_t)0x00000800) /* Falling trigger event configuration bit of line 11 */ +#define EXTI_FTENR_TR12 ((uint32_t)0x00001000) /* Falling trigger event configuration bit of line 12 */ +#define EXTI_FTENR_TR13 ((uint32_t)0x00002000) /* Falling trigger event configuration bit of line 13 */ +#define EXTI_FTENR_TR14 ((uint32_t)0x00004000) /* Falling trigger event configuration bit of line 14 */ +#define EXTI_FTENR_TR15 ((uint32_t)0x00008000) /* Falling trigger event configuration bit of line 15 */ +#define EXTI_FTENR_TR16 ((uint32_t)0x00010000) /* Falling trigger event configuration bit of line 16 */ +#define EXTI_FTENR_TR17 ((uint32_t)0x00020000) /* Falling trigger event configuration bit of line 17 */ +#define EXTI_FTENR_TR18 ((uint32_t)0x00040000) /* Falling trigger event configuration bit of line 18 */ +#define EXTI_FTENR_TR19 ((uint32_t)0x00080000) /* Falling trigger event configuration bit of line 19 */ +#define EXTI_FTENR_TR20 ((uint32_t)0x00100000) /* Falling trigger event configuration bit of line 20 */ +#define EXTI_FTENR_TR21 ((uint32_t)0x00200000) /* Falling trigger event configuration bit of line 21 */ +#define EXTI_FTENR_TR22 ((uint32_t)0x00400000) /* Falling trigger event configuration bit of line 22 */ +#define EXTI_FTENR_TR23 ((uint32_t)0x00800000) /* Falling trigger event configuration bit of line 23 */ +#define EXTI_FTENR_TR24 ((uint32_t)0x01000000) /* Falling trigger event configuration bit of line 24 */ +#define EXTI_FTENR_TR25 ((uint32_t)0x02000000) /* Falling trigger event configuration bit of line 25 */ +#define EXTI_FTENR_TR26 ((uint32_t)0x04000000) /* Falling trigger event configuration bit of line 26 */ +#define EXTI_FTENR_TR27 ((uint32_t)0x08000000) /* Falling trigger event configuration bit of line 27 */ +#define EXTI_FTENR_TR28 ((uint32_t)0x10000000) /* Falling trigger event configuration bit of line 28 */ +#define EXTI_FTENR_TR29 ((uint32_t)0x20000000) /* Falling trigger event configuration bit of line 29 */ + +/****************** Bit definition for EXTI_SWIEVR register ******************/ +#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ +#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ +#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ +#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ +#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ +#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ +#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ +#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ +#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ +#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ +#define EXTI_SWIEVR_SWIEVR10 ((uint32_t)0x00000400) /* Software Interrupt on line 10 */ +#define EXTI_SWIEVR_SWIEVR11 ((uint32_t)0x00000800) /* Software Interrupt on line 11 */ +#define EXTI_SWIEVR_SWIEVR12 ((uint32_t)0x00001000) /* Software Interrupt on line 12 */ +#define EXTI_SWIEVR_SWIEVR13 ((uint32_t)0x00002000) /* Software Interrupt on line 13 */ +#define EXTI_SWIEVR_SWIEVR14 ((uint32_t)0x00004000) /* Software Interrupt on line 14 */ +#define EXTI_SWIEVR_SWIEVR15 ((uint32_t)0x00008000) /* Software Interrupt on line 15 */ +#define EXTI_SWIEVR_SWIEVR16 ((uint32_t)0x00010000) /* Software Interrupt on line 16 */ +#define EXTI_SWIEVR_SWIEVR17 ((uint32_t)0x00020000) /* Software Interrupt on line 17 */ +#define EXTI_SWIEVR_SWIEVR18 ((uint32_t)0x00040000) /* Software Interrupt on line 18 */ +#define EXTI_SWIEVR_SWIEVR19 ((uint32_t)0x00080000) /* Software Interrupt on line 19 */ +#define EXTI_SWIEVR_SWIEVR20 ((uint32_t)0x00100000) /* Software Interrupt on line 20 */ +#define EXTI_SWIEVR_SWIEVR21 ((uint32_t)0x00200000) /* Software Interrupt on line 21 */ +#define EXTI_SWIEVR_SWIEVR22 ((uint32_t)0x00400000) /* Software Interrupt on line 22 */ +#define EXTI_SWIEVR_SWIEVR23 ((uint32_t)0x00800000) /* Software Interrupt on line 23 */ +#define EXTI_SWIEVR_SWIEVR24 ((uint32_t)0x01000000) /* Software Interrupt on line 24 */ +#define EXTI_SWIEVR_SWIEVR25 ((uint32_t)0x02000000) /* Software Interrupt on line 25 */ +#define EXTI_SWIEVR_SWIEVR26 ((uint32_t)0x04000000) /* Software Interrupt on line 26 */ +#define EXTI_SWIEVR_SWIEVR27 ((uint32_t)0x08000000) /* Software Interrupt on line 27 */ +#define EXTI_SWIEVR_SWIEVR28 ((uint32_t)0x10000000) /* Software Interrupt on line 28 */ +#define EXTI_SWIEVR_SWIEVR29 ((uint32_t)0x20000000) /* Software Interrupt on line 29 */ + +/******************* Bit definition for EXTI_INTFR register ********************/ +#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ +#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ +#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ +#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ +#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ +#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ +#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ +#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ +#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ +#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ +#define EXTI_INTF_INTF10 ((uint32_t)0x00000400) /* Pending bit for line 10 */ +#define EXTI_INTF_INTF11 ((uint32_t)0x00000800) /* Pending bit for line 11 */ +#define EXTI_INTF_INTF12 ((uint32_t)0x00001000) /* Pending bit for line 12 */ +#define EXTI_INTF_INTF13 ((uint32_t)0x00002000) /* Pending bit for line 13 */ +#define EXTI_INTF_INTF14 ((uint32_t)0x00004000) /* Pending bit for line 14 */ +#define EXTI_INTF_INTF15 ((uint32_t)0x00008000) /* Pending bit for line 15 */ +#define EXTI_INTF_INTF16 ((uint32_t)0x00010000) /* Pending bit for line 16 */ +#define EXTI_INTF_INTF17 ((uint32_t)0x00020000) /* Pending bit for line 17 */ +#define EXTI_INTF_INTF18 ((uint32_t)0x00040000) /* Pending bit for line 18 */ +#define EXTI_INTF_INTF19 ((uint32_t)0x00080000) /* Pending bit for line 19 */ +#define EXTI_INTF_INTF20 ((uint32_t)0x00100000) /* Pending bit for line 20 */ +#define EXTI_INTF_INTF21 ((uint32_t)0x00200000) /* Pending bit for line 21 */ +#define EXTI_INTF_INTF22 ((uint32_t)0x00400000) /* Pending bit for line 22 */ +#define EXTI_INTF_INTF23 ((uint32_t)0x00800000) /* Pending bit for line 23 */ +#define EXTI_INTF_INTF24 ((uint32_t)0x01000000) /* Pending bit for line 24 */ +#define EXTI_INTF_INTF25 ((uint32_t)0x02000000) /* Pending bit for line 25 */ +#define EXTI_INTF_INTF26 ((uint32_t)0x04000000) /* Pending bit for line 26 */ +#define EXTI_INTF_INTF27 ((uint32_t)0x08000000) /* Pending bit for line 27 */ +#define EXTI_INTF_INTF28 ((uint32_t)0x10000000) /* Pending bit for line 28 */ +#define EXTI_INTF_INTF29 ((uint32_t)0x20000000) /* Pending bit for line 29 */ + +/******************************************************************************/ +/* FLASH and Option Bytes Registers */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_ACTLR register ******************/ +#define FLASH_ACTLR_LATENCY ((uint8_t)0x03) /* LATENCY[2:0] bits (Latency) */ +#define FLASH_ACTLR_LATENCY_0 ((uint8_t)0x00) /* Bit 0 */ +#define FLASH_ACTLR_LATENCY_1 ((uint8_t)0x01) /* Bit 0 */ +#define FLASH_ACTLR_LATENCY_2 ((uint8_t)0x02) /* Bit 1 */ + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ + +/***************** Bit definition for FLASH_OBKEYR register ****************/ +#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ + +/****************** Bit definition for FLASH_STATR register *******************/ +#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ +#define FLASH_STATR_PGERR ((uint8_t)0x04) /* Programming Error */ +#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ +#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ +#define FLASH_STATR_FWAKE_FLAG ((uint8_t)0x40) /* Flag of wake */ +#define FLASH_STATR_TURBO ((uint8_t)0x80) /* The state of TURBO Enable */ +#define FLASH_STATR_BOOT_AVA ((uint16_t)0x100) /* The state of Init Config */ +#define FLASH_STATR_BOOT_STATUS ((uint16_t)0x200) /* The source of Execute Program */ +#define FLASH_STATR_BOOT_MODE ((uint16_t)0x400) /* The switch of user section or boot section*/ +#define FLASH_STATR_BOOT_LOCK ((uint16_t)0x800) /* Lock boot area*/ + +/******************* Bit definition for FLASH_CTLR register *******************/ +#define FLASH_CTLR_PG ((uint32_t)0x00000001) /* Programming */ +#define FLASH_CTLR_PER ((uint32_t)0x00000002) /* Sector Erase 4K */ +#define FLASH_CTLR_MER ((uint32_t)0x00000004) /* Mass Erase */ +#define FLASH_CTLR_OPTPG ((uint32_t)0x00000010) /* Option Byte Programming */ +#define FLASH_CTLR_OPTER ((uint32_t)0x00000020) /* Option Byte Erase */ +#define FLASH_CTLR_STRT ((uint32_t)0x00000040) /* Start */ +#define FLASH_CTLR_LOCK ((uint32_t)0x00000080) /* Lock */ +#define FLASH_CTLR_OBWRE ((uint32_t)0x00000200) /* Option Bytes Write Enable */ +#define FLASH_CTLR_ERRIE ((uint32_t)0x00000400) /* Error Interrupt Enable */ +#define FLASH_CTLR_EOPIE ((uint32_t)0x00001000) /* End of operation interrupt enable */ +#define FLASH_CTLR_FWAKEIE ((uint32_t)0x00002000) /* Wake inter Enable */ +#define FLASH_CTLR_FLOCK ((uint32_t)0x00008000) /* Fast Lock */ +#define FLASH_CTLR_FTPG ((uint32_t)0x00010000) /* Fast Program */ +#define FLASH_CTLR_FTER ((uint32_t)0x00020000) /* Fast Erase */ +#define FLASH_CTLR_BUFLOAD ((uint32_t)0x00040000) /* BUF Load */ +#define FLASH_CTLR_BUFRST ((uint32_t)0x00080000) /* BUF Reset */ +#define FLASH_CTLR_BER32 ((uint32_t)0x00800000) /* Block Erase 32K */ + +/******************* Bit definition for FLASH_ADDR register *******************/ +#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /* Option Byte Error */ +#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /* Read protection */ + +#define FLASH_OBR_USER ((uint16_t)0x007C) /* User Option Bytes */ +#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */ +#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /* nRST_STOP */ +#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /* nRST_STDBY */ +#define FLASH_OBR_CFGRSTT ((uint16_t)0x0060) /* Config Reset delay time */ + +#define FLASH_OBR_FIX_11 ((uint16_t)0x0300) /* fix 11 */ +#define FLASH_OBR_DATA0 ((uint32_t)0x3FC00) /* Data byte0 */ +#define FLASH_OBR_DATA1 ((uint32_t)0x3FC0000) /* Data byte1 */ + +/****************** Bit definition for FLASH_WPR register ******************/ +#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ + +/****************** Bit definition for FLASH_MODEKEYR register ******************/ +#define FLASH_MODEKEYR_MODEKEYR ((uint32_t)0xFFFFFFFF) /* Open fast program /erase */ +#define FLASH_MODEKEYR_MODEKEYR1 ((uint32_t)0x45670123) +#define FLASH_MODEKEYR_MODEKEYR2 ((uint32_t)0xCDEF89AB) + +/****************** Bit definition for BOOT_MODEKEYP register ******************/ +#define BOOT_MODEKEYP_MODEKEYR ((uint32_t)0xFFFFFFFF) /* Open Boot section */ +#define BOOT_MODEKEYP_MODEKEYR1 ((uint32_t)0x45670123) +#define BOOT_MODEKEYP_MODEKEYR2 ((uint32_t)0xCDEF89AB) + +/****************** Bit definition for FLASH_RDPR register *******************/ +#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ +#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ +#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ +#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ +#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_WRPR0 register ******************/ +#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR1 register ******************/ +#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR2 register ******************/ +#define FLASH_WRPR2_WRPR2 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR2_nWRPR2 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR3 register ******************/ +#define FLASH_WRPR3_WRPR3 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR3_nWRPR3 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/******************************************************************************/ +/* General Purpose and Alternate Function I/O */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CFGLR register *******************/ +#define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_CFGHR register *******************/ +#define GPIO_CFGHR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGHR_MODE8 ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CFGHR_MODE8_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGHR_MODE8_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGHR_MODE9 ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CFGHR_MODE9_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGHR_MODE9_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGHR_MODE10 ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CFGHR_MODE10_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGHR_MODE10_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGHR_MODE11 ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CFGHR_MODE11_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGHR_MODE11_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE12 ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CFGHR_MODE12_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGHR_MODE12_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE13 ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CFGHR_MODE13_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGHR_MODE13_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE14 ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CFGHR_MODE14_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE14_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE15 ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CFGHR_MODE15_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE15_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGHR_CNF8 ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CFGHR_CNF8_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGHR_CNF8_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGHR_CNF9 ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CFGHR_CNF9_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGHR_CNF9_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGHR_CNF10 ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CFGHR_CNF10_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGHR_CNF10_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGHR_CNF11 ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CFGHR_CNF11_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGHR_CNF11_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF12 ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CFGHR_CNF12_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGHR_CNF12_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF13 ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CFGHR_CNF13_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGHR_CNF13_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF14 ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CFGHR_CNF14_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF14_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF15 ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CFGHR_CNF15_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF15_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_INDR register *******************/ +#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */ +#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */ +#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */ +#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */ +#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */ +#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */ +#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */ +#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */ +#define GPIO_INDR_IDR8 ((uint16_t)0x0100) /* Port input data, bit 8 */ +#define GPIO_INDR_IDR9 ((uint16_t)0x0200) /* Port input data, bit 9 */ +#define GPIO_INDR_IDR10 ((uint16_t)0x0400) /* Port input data, bit 10 */ +#define GPIO_INDR_IDR11 ((uint16_t)0x0800) /* Port input data, bit 11 */ +#define GPIO_INDR_IDR12 ((uint16_t)0x1000) /* Port input data, bit 12 */ +#define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */ +#define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */ +#define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */ +#define GPIO_INDR_IDR16 ((uint32_t)0x10000) /* Port input data, bit 16 */ +#define GPIO_INDR_IDR17 ((uint32_t)0x20000) /* Port input data, bit 17 */ +#define GPIO_INDR_IDR18 ((uint32_t)0x40000) /* Port input data, bit 18 */ +#define GPIO_INDR_IDR19 ((uint32_t)0x80000) /* Port input data, bit 19 */ +#define GPIO_INDR_IDR20 ((uint32_t)0x100000) /* Port input data, bit 20 */ +#define GPIO_INDR_IDR21 ((uint32_t)0x200000) /* Port input data, bit 21 */ +#define GPIO_INDR_IDR22 ((uint32_t)0x400000) /* Port input data, bit 22 */ +#define GPIO_INDR_IDR23 ((uint32_t)0x800000) /* Port input data, bit 23 */ + +/******************* Bit definition for GPIO_OUTDR register *******************/ +#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ +#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */ +#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */ +#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */ +#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */ +#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */ +#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */ +#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */ +#define GPIO_OUTDR_ODR8 ((uint16_t)0x0100) /* Port output data, bit 8 */ +#define GPIO_OUTDR_ODR9 ((uint16_t)0x0200) /* Port output data, bit 9 */ +#define GPIO_OUTDR_ODR10 ((uint16_t)0x0400) /* Port output data, bit 10 */ +#define GPIO_OUTDR_ODR11 ((uint16_t)0x0800) /* Port output data, bit 11 */ +#define GPIO_OUTDR_ODR12 ((uint16_t)0x1000) /* Port output data, bit 12 */ +#define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */ +#define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */ +#define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */ +#define GPIO_OUTDR_ODR16 ((uint32_t)0x10000) /* Port output data, bit 16 */ +#define GPIO_OUTDR_ODR17 ((uint32_t)0x20000) /* Port output data, bit 17 */ +#define GPIO_OUTDR_ODR18 ((uint32_t)0x40000) /* Port output data, bit 18 */ +#define GPIO_OUTDR_ODR19 ((uint32_t)0x80000) /* Port output data, bit 19 */ +#define GPIO_OUTDR_ODR20 ((uint32_t)0x100000) /* Port output data, bit 20 */ +#define GPIO_OUTDR_ODR21 ((uint32_t)0x200000) /* Port output data, bit 21 */ +#define GPIO_OUTDR_ODR22 ((uint32_t)0x400000) /* Port output data, bit 22 */ +#define GPIO_OUTDR_ODR23 ((uint32_t)0x800000) /* Port output data, bit 23 */ + +/****************** Bit definition for GPIO_BSHR register *******************/ +#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ +#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ +#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ +#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ +#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ +#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ +#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ +#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ +#define GPIO_BSHR_BS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */ +#define GPIO_BSHR_BS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */ +#define GPIO_BSHR_BS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */ +#define GPIO_BSHR_BS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */ +#define GPIO_BSHR_BS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */ +#define GPIO_BSHR_BS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */ +#define GPIO_BSHR_BS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */ +#define GPIO_BSHR_BS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */ + +#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ +#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ +#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ +#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ +#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ +#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ +#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ +#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ +#define GPIO_BSHR_BR8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */ +#define GPIO_BSHR_BR9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */ +#define GPIO_BSHR_BR10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */ +#define GPIO_BSHR_BR11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */ +#define GPIO_BSHR_BR12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */ +#define GPIO_BSHR_BR13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */ +#define GPIO_BSHR_BR14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */ +#define GPIO_BSHR_BR15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BCR register *******************/ +#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ +#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ +#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ +#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ +#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ +#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ +#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ +#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ +#define GPIO_BCR_BR8 ((uint16_t)0x0100) /* Port x Reset bit 8 */ +#define GPIO_BCR_BR9 ((uint16_t)0x0200) /* Port x Reset bit 9 */ +#define GPIO_BCR_BR10 ((uint16_t)0x0400) /* Port x Reset bit 10 */ +#define GPIO_BCR_BR11 ((uint16_t)0x0800) /* Port x Reset bit 11 */ +#define GPIO_BCR_BR12 ((uint16_t)0x1000) /* Port x Reset bit 12 */ +#define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */ +#define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */ +#define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */ +#define GPIO_BCR_BR16 ((uint32_t)0x10000) /* Port x Reset bit 16 */ +#define GPIO_BCR_BR17 ((uint32_t)0x20000) /* Port x Reset bit 17 */ +#define GPIO_BCR_BR18 ((uint32_t)0x40000) /* Port x Reset bit 18 */ +#define GPIO_BCR_BR19 ((uint32_t)0x80000) /* Port x Reset bit 19 */ +#define GPIO_BCR_BR20 ((uint32_t)0x100000) /* Port x Reset bit 20 */ +#define GPIO_BCR_BR21 ((uint32_t)0x200000) /* Port x Reset bit 21 */ +#define GPIO_BCR_BR22 ((uint32_t)0x400000) /* Port x Reset bit 22 */ +#define GPIO_BCR_BR23 ((uint32_t)0x800000) /* Port x Reset bit 23 */ + + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ +#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ +#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ +#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ +#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ +#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ +#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ +#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ +#define GPIO_LCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */ +#define GPIO_LCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */ +#define GPIO_LCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */ +#define GPIO_LCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */ +#define GPIO_LCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */ +#define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */ +#define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */ +#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */ +#define GPIO_LCK16 ((uint32_t)0x00010000) /* Port x Lock bit 16 */ +#define GPIO_LCK17 ((uint32_t)0x00020000) /* Port x Lock bit 17 */ +#define GPIO_LCK18 ((uint32_t)0x00040000) /* Port x Lock bit 18 */ +#define GPIO_LCK19 ((uint32_t)0x00080000) /* Port x Lock bit 19 */ +#define GPIO_LCK20 ((uint32_t)0x00100000) /* Port x Lock bit 20 */ +#define GPIO_LCK21 ((uint32_t)0x00200000) /* Port x Lock bit 21 */ +#define GPIO_LCK22 ((uint32_t)0x00400000) /* Port x Lock bit 22 */ +#define GPIO_LCK23 ((uint32_t)0x00800000) /* Port x Lock bit 23 */ + +#define GPIO_LCKK ((uint32_t)0x01000000) /* Lock key */ + +/******************* Bit definition for GPIO_CFGXR register *******************/ +#define GPIO_CFGXR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGXR_MODE16 ((uint32_t)0x00000003) /* MODE16[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CFGXR_MODE16_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGXR_MODE16_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGXR_MODE17 ((uint32_t)0x00000030) /* MODE17[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CFGXR_MODE17_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGXR_MODE17_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGXR_MODE18 ((uint32_t)0x00000300) /* MODE18[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CFGXR_MODE18_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGXR_MODE18_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGXR_MODE19 ((uint32_t)0x00003000) /* MODE19[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CFGXR_MODE19_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGXR_MODE19_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGXR_MODE20 ((uint32_t)0x00030000) /* MODE20[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CFGXR_MODE20_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGXR_MODE20_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGXR_MODE21 ((uint32_t)0x00300000) /* MODE21[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CFGXR_MODE21_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGXR_MODE21_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGXR_MODE22 ((uint32_t)0x03000000) /* MODE22[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CFGXR_MODE22_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGXR_MODE22_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGXR_MODE23 ((uint32_t)0x30000000) /* MODE23[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CFGXR_MODE23_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGXR_MODE23_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGXR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGXR_CNF16 ((uint32_t)0x0000000C) /* CNF16[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CFGXR_CNF16_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGXR_CNF16_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGXR_CNF17 ((uint32_t)0x000000C0) /* CNF17[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CFGXR_CNF17_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGXR_CNF17_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGXR_CNF18 ((uint32_t)0x00000C00) /* CNF18[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CFGXR_CNF18_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGXR_CNF18_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGXR_CNF19 ((uint32_t)0x0000C000) /* CNF19[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CFGXR_CNF19_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGXR_CNF19_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGXR_CNF20 ((uint32_t)0x000C0000) /* CNF20[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CFGXR_CNF20_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGXR_CNF20_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGXR_CNF21 ((uint32_t)0x00C00000) /* CNF21[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CFGXR_CNF21_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGXR_CNF21_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGXR_CNF22 ((uint32_t)0x0C000000) /* CNF22[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CFGXR_CNF22_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGXR_CNF22_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGXR_CNF23 ((uint32_t)0xC0000000) /* CNF23[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CFGXR_CNF23_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGXR_CNF23_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/****************** Bit definition for GPIO_BSXR register *******************/ +#define GPIO_BSXR_BS16 ((uint32_t)0x00000001) /* Port x Set bit 0 */ +#define GPIO_BSXR_BS17 ((uint32_t)0x00000002) /* Port x Set bit 1 */ +#define GPIO_BSXR_BS18 ((uint32_t)0x00000004) /* Port x Set bit 2 */ +#define GPIO_BSXR_BS19 ((uint32_t)0x00000008) /* Port x Set bit 3 */ +#define GPIO_BSXR_BS20 ((uint32_t)0x00000010) /* Port x Set bit 4 */ +#define GPIO_BSXR_BS21 ((uint32_t)0x00000020) /* Port x Set bit 5 */ +#define GPIO_BSXR_BS22 ((uint32_t)0x00000040) /* Port x Set bit 6 */ +#define GPIO_BSXR_BS23 ((uint32_t)0x00000080) /* Port x Set bit 7 */ + +#define GPIO_BSXR_BR16 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ +#define GPIO_BSXR_BR17 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ +#define GPIO_BSXR_BR18 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ +#define GPIO_BSXR_BR19 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ +#define GPIO_BSXR_BR20 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ +#define GPIO_BSXR_BR21 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ +#define GPIO_BSXR_BR22 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ +#define GPIO_BSXR_BR23 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ + +/****************** Bit definition for AFIO_PCFR1register *******************/ +#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000003) /* SPI1_REMAP[1:0] bits (SPI1 remapping) */ +#define AFIO_PCFR1_SPI1_REMAP_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define AFIO_PCFR1_SPI1_REMAP_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x0000001C) /* I2C1_REMAP[4:2] bits (I2C1 remapping) */ +#define AFIO_PCFR1_I2C1_REMAP_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define AFIO_PCFR1_I2C1_REMAP_1 ((uint32_t)0x00000008) /* Bit 1 */ +#define AFIO_PCFR1_I2C1_REMAP_2 ((uint32_t)0x00000010) /* Bit 2 */ + +#define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x00000060) /* USART1_REMAP[6:5] bits (USART1 remapping) */ +#define AFIO_PCFR1_USART1_REMAP_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define AFIO_PCFR1_USART1_REMAP_1 ((uint32_t)0x00000040) /* Bit 1 */ + +#define AFIO_PCFR1_USART2_REMAP ((uint32_t)0x00000380) /* USART2_REMAP[9:7] bits (USART2 remapping) */ +#define AFIO_PCFR1_USART2_REMAP_0 ((uint32_t)0x00000080) /* Bit 0 */ +#define AFIO_PCFR1_USART2_REMAP_1 ((uint32_t)0x00000100) /* Bit 1 */ +#define AFIO_PCFR1_USART2_REMAP_2 ((uint32_t)0x00000200) /* Bit 2 */ + +#define AFIO_PCFR1_USART3_REMAP ((uint32_t)0x00000C00) /* USART3_REMAP[11:10] bits (USART3 remapping) */ +#define AFIO_PCFR1_USART3_REMAP_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define AFIO_PCFR1_USART3_REMAP_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define AFIO_PCFR1_USART4_REMAP ((uint32_t)0x00000700) /* USART4_REMAP[14:12] bits (USART4 remapping) */ +#define AFIO_PCFR1_USART4_REMAP_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define AFIO_PCFR1_USART4_REMAP_1 ((uint32_t)0x00000200) /* Bit 1 */ +#define AFIO_PCFR1_USART4_REMAP_2 ((uint32_t)0x00000400) /* Bit 2 */ + +#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x00003800) /* TIM1_REMAP[17:15] bits (TIM1 remapping) */ +#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00000800) /* Bit 0 */ +#define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00001000) /* Bit 1 */ +#define AFIO_PCFR1_TIM1_REMAP_2 ((uint32_t)0x00002000) /* Bit 2 */ + +#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x0001C000) /* TIM2_REMAP[20:18] bits (TIM2 remapping) */ +#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00008000) /* Bit 1 */ +#define AFIO_PCFR1_TIM2_REMAP_2 ((uint32_t)0x00010000) /* Bit 2 */ + +#define AFIO_PCFR1_TIM3_REMAP ((uint32_t)0x00060000) /* TIM3_REMAP[22:21] bits (TIM3 remapping) */ +#define AFIO_PCFR1_TIM3_REMAP_0 ((uint32_t)0x00020000) /* Bit 0 */ +#define AFIO_PCFR1_TIM3_REMAP_1 ((uint32_t)0x00040000) /* Bit 1 */ + +#define AFIO_PCFR1_PIOC_REMAP ((uint32_t)0x00080000) /* PIOC[23] bits (PIOC remapping) */ + +#define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x00700000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x00400000) /* Bit 2 */ + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint32_t)0x00000003) /* EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint32_t)0x0000000C) /* EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000030) /* EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint32_t)0x000000C0) /* EXTI 3 configuration */ +#define AFIO_EXTICR1_EXTI4 ((uint32_t)0x00000300) /* EXTI 4 configuration */ +#define AFIO_EXTICR1_EXTI5 ((uint32_t)0x00000C00) /* EXTI 5 configuration */ +#define AFIO_EXTICR1_EXTI6 ((uint32_t)0x00003000) /* EXTI 6 configuration */ +#define AFIO_EXTICR1_EXTI7 ((uint32_t)0x0000C000) /* EXTI 7 configuration */ +#define AFIO_EXTICR1_EXTI8 ((uint32_t)0x00030000) /* EXTI 8 configuration */ +#define AFIO_EXTICR1_EXTI9 ((uint32_t)0x000C0000) /* EXTI 9 configuration */ +#define AFIO_EXTICR1_EXTI10 ((uint32_t)0x00300000) /* EXTI 10 configuration */ +#define AFIO_EXTICR1_EXTI11 ((uint32_t)0x00C00000) /* EXTI 11 configuration */ +#define AFIO_EXTICR1_EXTI12 ((uint32_t)0x03000000) /* EXTI 12 configuration */ +#define AFIO_EXTICR1_EXTI13 ((uint32_t)0x0C000000) /* EXTI 13 configuration */ +#define AFIO_EXTICR1_EXTI14 ((uint32_t)0x30000000) /* EXTI 14 configuration */ +#define AFIO_EXTICR1_EXTI15 ((uint32_t)0xC0000000) /* EXTI 15 configuration */ + +#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /* PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /* PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /* PC[0] pin */ + +#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /* PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000004) /* PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000008) /* PC[1] pin */ + +#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /* PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000010) /* PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000020) /* PC[2] pin */ + +#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /* PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00000040) /* PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00000080) /* PC[3] pin */ + +#define AFIO_EXTICR1_EXTI4_PA ((uint32_t)0x00000000) /* PA[4] pin */ +#define AFIO_EXTICR1_EXTI4_PB ((uint32_t)0x00000100) /* PB[4] pin */ +#define AFIO_EXTICR1_EXTI4_PC ((uint32_t)0x00000200) /* PC[4] pin */ + +#define AFIO_EXTICR1_EXTI5_PA ((uint32_t)0x00000000) /* PA[5] pin */ +#define AFIO_EXTICR1_EXTI5_PB ((uint32_t)0x00000400) /* PB[5] pin */ +#define AFIO_EXTICR1_EXTI5_PC ((uint32_t)0x00000800) /* PC[5] pin */ + +#define AFIO_EXTICR1_EXTI6_PA ((uint32_t)0x00000000) /* PA[6] pin */ +#define AFIO_EXTICR1_EXTI6_PB ((uint32_t)0x00001000) /* PB[6] pin */ +#define AFIO_EXTICR1_EXTI6_PC ((uint32_t)0x00002000) /* PC[6] pin */ + +#define AFIO_EXTICR1_EXTI7_PA ((uint32_t)0x00000000) /* PA[7] pin */ +#define AFIO_EXTICR1_EXTI7_PB ((uint32_t)0x00004000) /* PB[7] pin */ +#define AFIO_EXTICR1_EXTI7_PC ((uint32_t)0x00008000) /* PC[7] pin */ + +#define AFIO_EXTICR1_EXTI8_PA ((uint32_t)0x00000000) /* PA[8] pin */ +#define AFIO_EXTICR1_EXTI8_PB ((uint32_t)0x00010000) /* PB[8] pin */ +#define AFIO_EXTICR1_EXTI8_PC ((uint32_t)0x00020000) /* PC[8] pin */ + +#define AFIO_EXTICR1_EXTI9_PA ((uint32_t)0x00000000) /* PA[9] pin */ +#define AFIO_EXTICR1_EXTI9_PB ((uint32_t)0x00040000) /* PB[9] pin */ +#define AFIO_EXTICR1_EXTI9_PC ((uint32_t)0x00080000) /* PC[9] pin */ + +#define AFIO_EXTICR1_EXTI10_PA ((uint32_t)0x00000000) /* PA[10] pin */ +#define AFIO_EXTICR1_EXTI10_PB ((uint32_t)0x00100000) /* PB[10] pin */ +#define AFIO_EXTICR1_EXTI10_PC ((uint32_t)0x00200000) /* PC[10] pin */ + +#define AFIO_EXTICR1_EXTI11_PA ((uint32_t)0x00000000) /* PA[11] pin */ +#define AFIO_EXTICR1_EXTI11_PB ((uint32_t)0x00400000) /* PB[11] pin */ +#define AFIO_EXTICR1_EXTI11_PC ((uint32_t)0x00800000) /* PC[11] pin */ + +#define AFIO_EXTICR1_EXTI12_PA ((uint32_t)0x00000000) /* PA[12] pin */ +#define AFIO_EXTICR1_EXTI12_PB ((uint32_t)0x01000000) /* PB[12] pin */ +#define AFIO_EXTICR1_EXTI12_PC ((uint32_t)0x02000000) /* PC[12] pin */ + +#define AFIO_EXTICR1_EXTI13_PA ((uint32_t)0x00000000) /* PA[13] pin */ +#define AFIO_EXTICR1_EXTI13_PB ((uint32_t)0x04000000) /* PB[13] pin */ +#define AFIO_EXTICR1_EXTI13_PC ((uint32_t)0x08000000) /* PC[13] pin */ + +#define AFIO_EXTICR1_EXTI14_PA ((uint32_t)0x00000000) /* PA[14] pin */ +#define AFIO_EXTICR1_EXTI14_PB ((uint32_t)0x10000000) /* PB[14] pin */ +#define AFIO_EXTICR1_EXTI14_PC ((uint32_t)0x20000000) /* PC[14] pin */ + +#define AFIO_EXTICR1_EXTI15_PA ((uint32_t)0x00000000) /* PA[15] pin */ +#define AFIO_EXTICR1_EXTI15_PB ((uint32_t)0x40000000) /* PB[15] pin */ +#define AFIO_EXTICR1_EXTI15_PC ((uint32_t)0x80000000) /* PC[15] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI16 ((uint32_t)0x00000003) /* EXTI 16 configuration */ +#define AFIO_EXTICR2_EXTI17 ((uint32_t)0x0000000C) /* EXTI 17 configuration */ +#define AFIO_EXTICR2_EXTI18 ((uint32_t)0x00000030) /* EXTI 18 configuration */ +#define AFIO_EXTICR2_EXTI19 ((uint32_t)0x000000C0) /* EXTI 19 configuration */ +#define AFIO_EXTICR2_EXTI20 ((uint32_t)0x00000300) /* EXTI 20 configuration */ +#define AFIO_EXTICR2_EXTI21 ((uint32_t)0x00000C00) /* EXTI 21 configuration */ +#define AFIO_EXTICR2_EXTI22 ((uint32_t)0x00003000) /* EXTI 22 configuration */ +#define AFIO_EXTICR2_EXTI23 ((uint32_t)0x0000C000) /* EXTI 23 configuration */ + +#define AFIO_EXTICR2_EXTI16_PA ((uint32_t)0x00000000) /* PA[16] pin */ +#define AFIO_EXTICR2_EXTI16_PB ((uint32_t)0x00000001) /* PB[16] pin */ +#define AFIO_EXTICR2_EXTI16_PC ((uint32_t)0x00000002) /* PC[16] pin */ + +#define AFIO_EXTICR2_EXTI17_PA ((uint32_t)0x00000000) /* PA[17] pin */ +#define AFIO_EXTICR2_EXTI17_PB ((uint32_t)0x00000004) /* PB[17] pin */ +#define AFIO_EXTICR2_EXTI17_PC ((uint32_t)0x00000008) /* PC[17] pin */ + +#define AFIO_EXTICR2_EXTI18_PA ((uint32_t)0x00000000) /* PA[18] pin */ +#define AFIO_EXTICR2_EXTI18_PB ((uint32_t)0x00000010) /* PB[18] pin */ +#define AFIO_EXTICR2_EXTI18_PC ((uint32_t)0x00000020) /* PC[18] pin */ + +#define AFIO_EXTICR2_EXTI19_PA ((uint32_t)0x00000000) /* PA[19] pin */ +#define AFIO_EXTICR2_EXTI19_PB ((uint32_t)0x00000040) /* PB[19] pin */ +#define AFIO_EXTICR2_EXTI19_PC ((uint32_t)0x00000080) /* PC[19] pin */ + +#define AFIO_EXTICR2_EXTI20_PA ((uint32_t)0x00000000) /* PA[20] pin */ +#define AFIO_EXTICR2_EXTI20_PB ((uint32_t)0x00000100) /* PB[20] pin */ +#define AFIO_EXTICR2_EXTI20_PC ((uint32_t)0x00000200) /* PC[20] pin */ + +#define AFIO_EXTICR2_EXTI21_PA ((uint32_t)0x00000000) /* PA[21] pin */ +#define AFIO_EXTICR2_EXTI21_PB ((uint32_t)0x00000400) /* PB[21] pin */ +#define AFIO_EXTICR2_EXTI21_PC ((uint32_t)0x00000800) /* PC[21] pin */ + +#define AFIO_EXTICR2_EXTI22_PA ((uint32_t)0x00000000) /* PA[22] pin */ +#define AFIO_EXTICR2_EXTI22_PB ((uint32_t)0x00001000) /* PB[22] pin */ +#define AFIO_EXTICR2_EXTI22_PC ((uint32_t)0x00002000) /* PC[22] pin */ + +#define AFIO_EXTICR2_EXTI23_PA ((uint32_t)0x00000000) /* PA[23] pin */ +#define AFIO_EXTICR2_EXTI23_PB ((uint32_t)0x00004000) /* PB[23] pin */ +#define AFIO_EXTICR2_EXTI23_PC ((uint32_t)0x00008000) /* PC[23] pin */ + +/******************* Bit definition for AFIO_CTLR register ********************/ +#define AFIO_CTLR_UDM_PUE ((uint32_t)0x00000003) /* PC16/UDM Pin pull-up Mode*/ +#define AFIO_CTLR_UDM_PUE_0 ((uint32_t)0x00000001) /* bit[0] */ +#define AFIO_CTLR_UDM_PUE_1 ((uint32_t)0x00000002) /* bit[1] */ + +#define AFIO_CTLR_UDP_PUE ((uint32_t)0x00000000) /* PC17/UDP Pin pull-up Mode*/ +#define AFIO_CTLR_UDP_PUE_0 ((uint32_t)0x00000004) /* bit[2] */ +#define AFIO_CTLR_UDP_PUE_1 ((uint32_t)0x00000008) /* bit[3] */ + +#define AFIO_CTLR_USB_PHY_V33 ((uint32_t)0x00000040) /* USB transceiver PHY output and pull-up limiter configuration */ +#define AFIO_CTLR_USB_IOEN ((uint32_t)0x00000080) /* USB Remap pin enable */ +#define AFIO_CTLR_USBPD_PHY_V33 ((uint32_t)0x00000100) /* USBPD transceiver PHY output and pull-up limiter configuration */ +#define AFIO_CTLR_USBPD_IN_HVT ((uint32_t)0x00000200) /* PD pin PC14/PC15 high threshold input mode */ +#define AFIO_CTLR_UDP_BC_VSRC ((uint32_t)0x00010000) /* PC17/UDP pin BC protocol source voltage enable */ +#define AFIO_CTLR_UDM_BC_VSRC ((uint32_t)0x00020000) /* PC16/UDM pin BC protocol source voltage enable */ +#define AFIO_CTLR_UDP_BC_CMPO ((uint32_t)0x00040000) /* PC17/UDP pin BC protocol comparator status */ +#define AFIO_CTLR_UDM_BC_CMPO ((uint32_t)0x00080000) /* PC16/UDM pin BC protocol comparator status */ +#define AFIO_CTLR_PA3_FILT_EN ((uint32_t)0x01000000) /* Controls the input filtering of the PA3 pin */ +#define AFIO_CTLR_PA4_FILT_EN ((uint32_t)0x02000000) /* Controls the input filtering of the PA4 pin */ +#define AFIO_CTLR_PB5_FILT_EN ((uint32_t)0x04000000) /* Controls the input filtering of the PB5 pin */ +#define AFIO_CTLR_PB6_FILT_EN ((uint32_t)0x08000000) /* Controls the input filtering of the PB6 pin */ + + +/******************************************************************************/ +/* Independent WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_CTLR register ********************/ +#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PSCR register ********************/ +#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ +#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ +#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ +#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ + +/******************* Bit definition for IWDG_RLDR register *******************/ +#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ + +/******************* Bit definition for IWDG_STATR register ********************/ +#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ +#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ + +/******************************************************************************/ +/* Inter-integrated Circuit Interface */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CTLR1 register ********************/ +#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ +#define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */ +#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ +#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ +#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ +#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ +#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ +#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ +#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ +#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ +#define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */ +#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ + +/******************* Bit definition for I2C_CTLR2 register ********************/ +#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ + +#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ +#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ +#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ +#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ +#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ + +/******************* Bit definition for I2C_OADDR1 register *******************/ +#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ +#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ + +#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ +#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ +#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ +#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ +#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ + +#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OADDR2 register *******************/ +#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ +#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ + +/******************** Bit definition for I2C_DATAR register ********************/ +#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ + +/******************* Bit definition for I2C_STAR1 register ********************/ +#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ +#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ +#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ +#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ +#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ +#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ +#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ +#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ +#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ +#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ +#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ +#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ + +/******************* Bit definition for I2C_STAR2 register ********************/ +#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ +#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ +#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ +#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ +#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ +#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ + +/******************* Bit definition for I2C_CKCFGR register ********************/ +#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ +#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ + +/******************************************************************************/ +/* Power Control */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CTLR register ********************/ +#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */ + +#define PWR_CTLR_PLS ((uint16_t)0x0060) /* PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ + +#define PWR_CTLR_LP_REG ((uint16_t)0x0200) /* Software configure flash into lower energy mode */ +#define PWR_CTLR_LP ((uint16_t)0x0C00) /* Software configure flash Status */ +#define PWR_CTLR_LP_0 ((uint16_t)0x0400) +#define PWR_CTLR_LP_1 ((uint16_t)0x0800) + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */ +#define PWR_CSR_Flash_ack ((uint16_t)0x0200) /* Flash Status */ + +/******************************************************************************/ +/* Reset and Clock Control */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CTLR register ********************/ +#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ +#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ +#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ +#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ + +/******************* Bit definition for RCC_CFGR0 register *******************/ +#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */ +#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ +#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ + +#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ +#define RCC_HPRE_DIV2 ((uint32_t)0x00000010) /* SYSCLK divided by 2 */ +#define RCC_HPRE_DIV3 ((uint32_t)0x00000020) /* SYSCLK divided by 3 */ +#define RCC_HPRE_DIV4 ((uint32_t)0x00000030) /* SYSCLK divided by 4 */ +#define RCC_HPRE_DIV5 ((uint32_t)0x00000040) /* SYSCLK divided by 5 */ +#define RCC_HPRE_DIV6 ((uint32_t)0x00000050) /* SYSCLK divided by 6 */ +#define RCC_HPRE_DIV7 ((uint32_t)0x00000060) /* SYSCLK divided by 7 */ +#define RCC_HPRE_DIV8 ((uint32_t)0x00000070) /* SYSCLK divided by 8 */ +#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ +#define RCC_HPRE_DIV32 ((uint32_t)0x000000C0) /* SYSCLK divided by 32 */ +#define RCC_HPRE_DIV64 ((uint32_t)0x000000D0) /* SYSCLK divided by 64 */ +#define RCC_HPRE_DIV128 ((uint32_t)0x000000E0) /* SYSCLK divided by 128 */ +#define RCC_HPRE_DIV256 ((uint32_t)0x000000F0) /* SYSCLK divided by 256 */ + +#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */ + +/***************** Bit definition for RCC_APB2PRSTR register *****************/ +#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ +#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */ +#define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */ +#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */ +#define RCC_ADC1RST ((uint32_t)0x00000200) /* ADC 1 interface reset */ +#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */ +#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */ +#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */ + +/***************** Bit definition for RCC_APB1PRSTR register *****************/ +#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */ +#define RCC_TIM3RST ((uint32_t)0x00000002) /* Timer 3 reset */ +#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */ +#define RCC_USART2RST ((uint32_t)0x00020000) /* USART 2 reset */ +#define RCC_USART3RST ((uint32_t)0x00040000) /* USART 3 reset */ +#define RCC_USART4RST ((uint32_t)0x00080000) /* USART 4 reset */ +#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */ +#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */ + +/****************** Bit definition for RCC_AHBPCENR register ******************/ +#define RCC_DMA1EN ((uint32_t)0x00000001) /* DMA1 clock enable */ +#define RCC_SRAMEN ((uint32_t)0x00000004) /* SRAM interface clock enable */ +#define RCC_USBFS ((uint32_t)0x00001000) /* USBFS clock enable */ +#define RCC_USBPD ((uint32_t)0x00020000) /* USBPD clock enable */ + +/****************** Bit definition for RCC_APB2PCENR register *****************/ +#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */ +#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ +#define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */ +#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */ +#define RCC_ADC1EN ((uint32_t)0x00000200) /* ADC 1 interface clock enable */ +#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */ +#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */ +#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */ + +/***************** Bit definition for RCC_APB1PCENR register ******************/ +#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/ +#define RCC_TIM3EN ((uint32_t)0x00000002) /* Timer 3 clock enable */ +#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */ +#define RCC_USART2EN ((uint32_t)0x00020000) /* USART 2 clock enable */ +#define RCC_USART3EN ((uint32_t)0x00040000) /* USART 3 clock enable */ +#define RCC_USART4EN ((uint32_t)0x00080000) /* USART 4 clock enable */ +#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */ +#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */ + +/******************* Bit definition for RCC_RSTSCKR register ********************/ +#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */ +#define RCC_OPARSTF ((uint32_t)0x02000000) /* OPA reset flag */ +#define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */ +#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */ +#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */ +#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */ +#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ +#define RCC_LPWRRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */ + +/******************* Bit definition for RCC_AHBRSTR register ********************/ +#define RCC_USBFSRST ((uint32_t)0x00001000) /* USBFS reset */ +#define RCC_PIOCRST ((uint32_t)0x00002000) /* PIOC RST */ +#define RCC_USBPDRST ((uint32_t)0x00020000) /* USBPD reset */ + +/******************************************************************************/ +/* Serial Peripheral Interface */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CTLR1 register ********************/ +#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */ +#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */ +#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */ + +#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ +#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */ +#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */ +#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */ + +#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */ +#define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080) /* Frame Format */ +#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */ +#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */ +#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */ +#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */ +#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */ +#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */ +#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */ +#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CTLR2 register ********************/ +#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */ +#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */ +#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */ +#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ +#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ +#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ +#define SPI_CTLR2_ODEN ((uint16_t)0x8000) /* SPI OD output Enable */ + +/******************** Bit definition for SPI_STATR register ********************/ +#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ +#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */ +#define SPI_STATR_CHSIDE ((uint8_t)0x04) /* Channel side */ +#define SPI_STATR_UDR ((uint8_t)0x08) /* Underrun flag */ +#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */ +#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */ +#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */ +#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */ + +/******************** Bit definition for SPI_DATAR register ********************/ +#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */ + +/******************* Bit definition for SPI_CRCR register ******************/ +#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */ + +/****************** Bit definition for SPI_RCRCR register ******************/ +#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */ + +/****************** Bit definition for SPI_TCRCR register ******************/ +#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ + +/****************** Bit definition for SPI_HSCR register *****************/ +#define SPI_HSCR_HSRXEN ((uint16_t)0x0001) /* Read Enable under SPI High speed mode */ + +/******************************************************************************/ +/* TIM */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CTLR1 register ********************/ +#define TIM_CEN ((uint16_t)0x0001) /* Counter enable */ +#define TIM_UDIS ((uint16_t)0x0002) /* Update disable */ +#define TIM_URS ((uint16_t)0x0004) /* Update request source */ +#define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */ +#define TIM_DIR ((uint16_t)0x0010) /* Direction */ + +#define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ + +#define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ + +#define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ +#define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_CMP_BK ((uint16_t)0x1000) /* voltage comparator break enable, TIM1 only */ +#define TIM_CAPOV ((uint16_t)0x4000) /* Cfg mode of capture value */ +#define TIM_CAPLVL ((uint16_t)0x8000) + +/******************* Bit definition for TIM_CTLR2 register ********************/ +#define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ +#define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ +#define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ + +#define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ +#define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */ +#define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */ +#define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */ +#define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */ +#define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */ +#define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */ +#define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */ +#define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */ + +/******************* Bit definition for TIM_SMCFGR register *******************/ +#define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ + +#define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ +#define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */ + +#define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ +#define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ + +#define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define TIM_ECE ((uint16_t)0x4000) /* External clock enable */ +#define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */ + +/******************* Bit definition for TIM_DMAINTENR register *******************/ +#define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */ +#define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ +#define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ +#define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ +#define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ +#define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */ +#define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ +#define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */ +#define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */ +#define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ +#define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ +#define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ +#define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ +#define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */ +#define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ + +/******************** Bit definition for TIM_INTFR register ********************/ +#define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ +#define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ +#define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ +#define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ +#define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ +#define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */ +#define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ +#define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */ +#define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ +#define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ +#define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ +#define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ + +/******************* Bit definition for TIM_SWEVGR register ********************/ +#define TIM_UG ((uint8_t)0x01) /* Update Generation */ +#define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */ +#define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */ +#define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */ +#define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */ +#define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */ +#define TIM_TG ((uint8_t)0x40) /* Trigger Generation */ +#define TIM_BG ((uint8_t)0x80) /* Break Generation */ + +/****************** Bit definition for TIM_CHCTLR1 register *******************/ +#define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ +#define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ + +#define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ + +#define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ +#define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ + +#define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ + +#define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/****************** Bit definition for TIM_CHCTLR2 register *******************/ +#define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ +#define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ + +#define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ + +#define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ +#define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ + +#define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ + +#define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ +#define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ +#define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */ +#define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */ +#define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ +#define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ +#define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */ +#define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */ +#define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ +#define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ +#define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */ +#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ +#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ +#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */ + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ + +/******************* Bit definition for TIM_ATRLR register ********************/ +#define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */ + +/******************* Bit definition for TIM_RPTCR register ********************/ +#define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */ + +/******************* Bit definition for TIM_CH1CVR register *******************/ +#define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */ + +/******************* Bit definition for TIM_CH2CVR register *******************/ +#define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */ + +/******************* Bit definition for TIM_CH3CVR register *******************/ +#define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */ + +/******************* Bit definition for TIM_CH4CVR register *******************/ +#define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */ + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */ +#define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */ +#define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */ +#define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ +#define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ +#define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ +#define TIM_BKE ((uint16_t)0x1000) /* Break enable */ +#define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */ +#define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */ +#define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */ + +/******************* Bit definition for TIM_DMACFGR register ********************/ +#define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ +#define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ + +#define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ +#define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ + +/******************* Bit definition for TIM_DMAADR register *******************/ +#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */ + +/******************* Bit definition for TIM_SPEC register *******************/ +#define TIM_SPEC_PWM_EN_1_2 ((uint16_t)0x0001) /* Channel 1 and Channel 2 alternate */ +#define TIM_SPEC_PWM_EN_3_4 ((uint16_t)0x0002) /* Channel 3 and Channel 4 alternate */ +#define TIM_SPEC_PWM_OC1 ((uint16_t)0x0010) /* Channel 1 invalid level under alternate mode */ +#define TIM_SPEC_PWM_OC2 ((uint16_t)0x0020) /* Channel 2 invalid level under alternate mode */ +#define TIM_SPEC_PWM_OC3 ((uint16_t)0x0040) /* Channel 3 invalid level under alternate mode */ +#define TIM_SPEC_PWM_OC4 ((uint16_t)0x0080) /* Channel 4 invalid level under alternate mode */ +#define TIM_SPEC_TOGGLE ((uint16_t)0x8000) /* valid channel indicator */ + +/******************************************************************************/ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/******************************************************************************/ + +/******************* Bit definition for USART_STATR register *******************/ +#define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */ +#define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */ +#define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */ +#define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */ +#define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */ +#define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */ +#define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */ +#define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */ +#define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */ +#define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */ + +/******************* Bit definition for USART_DATAR register *******************/ +#define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CTLR1 register *******************/ +#define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */ +#define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */ +#define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */ +#define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */ +#define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */ +#define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */ +#define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */ +#define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */ +#define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */ +#define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */ +#define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */ +#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */ +#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */ +#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */ + +/****************** Bit definition for USART_CTLR2 register *******************/ +#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */ +#define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */ +#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */ +#define USART_CTLR2_LBCL ((uint16_t)0x0100) /* Last Bit Clock pulse */ +#define USART_CTLR2_CPHA ((uint16_t)0x0200) /* Clock Phase */ +#define USART_CTLR2_CPOL ((uint16_t)0x0400) /* Clock Polarity */ +#define USART_CTLR2_CLKEN ((uint16_t)0x0800) /* Clock Enable */ + +#define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */ +#define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */ +#define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */ + +/****************** Bit definition for USART_CTLR3 register *******************/ +#define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */ +#define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */ +#define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */ +#define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */ +#define USART_CTLR3_NACK ((uint16_t)0x0010) /* Smartcard NACK enable */ +#define USART_CTLR3_SCEN ((uint16_t)0x0020) /* Smartcard mode enable */ +#define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */ +#define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */ +#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */ +#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */ +#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */ + +/****************** Bit definition for USART_GPR register ******************/ +#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */ +#define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */ +#define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */ +#define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */ +#define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */ +#define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */ +#define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */ +#define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */ +#define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define USART_GPR_GT ((uint16_t)0xFF00) /* Guard time value */ + +/******************************************************************************/ +/* Window WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CTLR register ********************/ +#define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */ +#define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */ +#define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */ +#define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */ +#define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */ +#define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */ +#define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */ + +#define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */ + +/******************* Bit definition for WWDG_CFGR register *******************/ +#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */ +#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */ +#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */ +#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */ +#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */ +#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */ +#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */ +#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */ + +#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */ +#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */ + +#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_STATR register ********************/ +#define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */ + + +#include "ch32x035_conf.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Code/DAP_X033/Peripheral/inc/ch32x035_adc.h b/Code/DAP_X033/Peripheral/inc/ch32x035_adc.h new file mode 100644 index 0000000..ec71306 --- /dev/null +++ b/Code/DAP_X033/Peripheral/inc/ch32x035_adc.h @@ -0,0 +1,210 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_adc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for the + * ADC firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_ADC_H +#define __CH32X035_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +/* ADC Init structure definition */ +typedef struct +{ + uint32_t ADC_Mode; /* Configures the ADC to operate in independent or + dual mode. + This parameter can be a value of @ref ADC_mode */ + + FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in + Scan (multichannels) or Single (one channel) mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in + Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog + to digital conversion of regular channels. This parameter + can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ + + uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right. + This parameter can be a value of @ref ADC_data_align, Note:ADC_DataAlign_Left only applies to regular channels */ + + uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted + using the sequencer for regular channel group. + This parameter must range from 1 to 16. */ + + uint32_t ADC_OutputBuffer; /* Specifies whether the ADC channel output buffer is enabled or disabled. + This parameter can be a value of @ref ADC_OutputBuffer */ + + uint32_t ADC_Pga; /* Specifies the PGA gain multiple. + This parameter can be a value of @ref ADC_Pga */ +} ADC_InitTypeDef; + +/* ADC_mode */ +#define ADC_Mode_Independent ((uint32_t)0x00000000) + +/* ADC_external_trigger_sources_for_regular_channels_conversion */ +#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00020000) +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00040000) +#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x00060000) +#define ADC_ExternalTrigConv_T2_CC1 ((uint32_t)0x00080000) +#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x000C0000) +#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) + +/* ADC_data_align */ +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) + +/* ADC_channels */ +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) +#define ADC_Channel_10 ((uint8_t)0x0A) +#define ADC_Channel_11 ((uint8_t)0x0B) +#define ADC_Channel_12 ((uint8_t)0x0C) +#define ADC_Channel_13 ((uint8_t)0x0D) +#define ADC_Channel_14 ((uint8_t)0x0E) +#define ADC_Channel_15 ((uint8_t)0x0F) + +#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_15) + +/* ADC_sampling_time */ +#define ADC_SampleTime_4Cycles ((uint8_t)0x00) +#define ADC_SampleTime_5Cycles ((uint8_t)0x01) +#define ADC_SampleTime_6Cycles ((uint8_t)0x02) +#define ADC_SampleTime_7Cycles ((uint8_t)0x03) +#define ADC_SampleTime_8Cycles ((uint8_t)0x04) +#define ADC_SampleTime_9Cycles ((uint8_t)0x05) +#define ADC_SampleTime_10Cycles ((uint8_t)0x06) +#define ADC_SampleTime_11Cycles ((uint8_t)0x07) + +/* ADC_external_trigger_sources_for_injected_channels_conversion */ +#define ADC_ExternalTrigInjecConv_T1_CC3 ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) +#define ADC_ExternalTrigInjecConv_T2_CC3 ((uint32_t)0x00002000) +#define ADC_ExternalTrigInjecConv_T2_CC4 ((uint32_t)0x00003000) +#define ADC_ExternalTrigInjecConv_T2_CC2 ((uint32_t)0x00004000) +#define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00005000) +#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x00006000) +#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) + +/* ADC_injected_channel_selection */ +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) + +/* ADC_analog_watchdog_selection */ +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) + +/* ADC_interrupts_definition */ +#define ADC_IT_EOC ((uint16_t)0x0220) +#define ADC_IT_AWD ((uint16_t)0x0140) +#define ADC_IT_JEOC ((uint16_t)0x0480) + +/* ADC_flags_definition */ +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) + +/* ADC_analog_watchdog_reset_enable_selection */ +#define ADC_AnalogWatchdog_0_RST_EN ((uint32_t)0x00001000) +#define ADC_AnalogWatchdog_1_RST_EN ((uint32_t)0x00002000) +#define ADC_AnalogWatchdog_2_RST_EN ((uint32_t)0x00004000) +#define ADC_AnalogWatchdog_3_RST_EN ((uint32_t)0x00008000) + +/* ADC_analog_watchdog_reset_flags_definition */ +#define ADC_AnalogWatchdogResetFLAG_0 ((uint32_t)0x00010000) +#define ADC_AnalogWatchdogResetFLAG_1 ((uint32_t)0x00020000) +#define ADC_AnalogWatchdogResetFLAG_2 ((uint32_t)0x00040000) +#define ADC_AnalogWatchdogResetFLAG_3 ((uint32_t)0x00080000) + +/* ADC_clock */ +#define ADC_CLK_Div4 ((uint32_t)0x00000013) +#define ADC_CLK_Div5 ((uint32_t)0x00000014) +#define ADC_CLK_Div6 ((uint32_t)0x00000025) +#define ADC_CLK_Div7 ((uint32_t)0x00000026) +#define ADC_CLK_Div8 ((uint32_t)0x00000037) +#define ADC_CLK_Div9 ((uint32_t)0x00000038) +#define ADC_CLK_Div10 ((uint32_t)0x00000049) +#define ADC_CLK_Div11 ((uint32_t)0x0000004A) +#define ADC_CLK_Div12 ((uint32_t)0x0000005B) +#define ADC_CLK_Div13 ((uint32_t)0x0000005C) +#define ADC_CLK_Div14 ((uint32_t)0x0000006D) +#define ADC_CLK_Div15 ((uint32_t)0x0000006E) +#define ADC_CLK_Div16 ((uint32_t)0x0000007F) + + +void ADC_DeInit(ADC_TypeDef *ADCx); +void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct); +void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState); +void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx); +void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number); +void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx); +uint32_t ADC_GetDualModeConversionValue(void); +void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv); +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx); +void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length); +void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel); +void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_AnalogWatchdog1ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_AnalogWatchdog2ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_AnalogWatchdog3ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT); +void ADC_AnalogWatchdogResetCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog_x, FunctionalState NewState); +void ADC_AnalogWatchdogScanCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_CLKConfig(ADC_TypeDef *ADCx, uint32_t ADC_CLK_Div_x); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Code/DAP_X033/Peripheral/inc/ch32x035_awu.h b/Code/DAP_X033/Peripheral/inc/ch32x035_awu.h new file mode 100644 index 0000000..0142551 --- /dev/null +++ b/Code/DAP_X033/Peripheral/inc/ch32x035_awu.h @@ -0,0 +1,48 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_awu.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for the + * AWU firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_AWU_H +#define __CH32X035_AWU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +/* PWR_AWU_Prescaler */ +#define AWU_Prescaler_1 ((uint32_t)0x00000000) +#define AWU_Prescaler_2 ((uint32_t)0x00000002) +#define AWU_Prescaler_4 ((uint32_t)0x00000003) +#define AWU_Prescaler_8 ((uint32_t)0x00000004) +#define AWU_Prescaler_16 ((uint32_t)0x00000005) +#define AWU_Prescaler_32 ((uint32_t)0x00000006) +#define AWU_Prescaler_64 ((uint32_t)0x00000007) +#define AWU_Prescaler_128 ((uint32_t)0x00000008) +#define AWU_Prescaler_256 ((uint32_t)0x00000009) +#define AWU_Prescaler_512 ((uint32_t)0x0000000A) +#define AWU_Prescaler_1024 ((uint32_t)0x0000000B) +#define AWU_Prescaler_2048 ((uint32_t)0x0000000C) +#define AWU_Prescaler_4096 ((uint32_t)0x0000000D) +#define AWU_Prescaler_10240 ((uint32_t)0x0000000E) +#define AWU_Prescaler_61440 ((uint32_t)0x0000000F) + + +void AutoWakeUpCmd(FunctionalState NewState); +void AWU_SetPrescaler(uint32_t AWU_Prescaler); +void AWU_SetWindowValue(uint8_t WindowValue); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Code/DAP_X033/Peripheral/inc/ch32x035_dbgmcu.h b/Code/DAP_X033/Peripheral/inc/ch32x035_dbgmcu.h new file mode 100644 index 0000000..398db44 --- /dev/null +++ b/Code/DAP_X033/Peripheral/inc/ch32x035_dbgmcu.h @@ -0,0 +1,41 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_dbgmcu.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for the + * DBGMCU firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_DBGMCU_H +#define __CH32X035_DBGMCU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +#define DBGMCU_SLEEP ((uint32_t)0x00000001) +#define DBGMCU_STOP ((uint32_t)0x00000002) +#define DBGMCU_STANDBY ((uint32_t)0x00000004) +#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) +#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) +#define DBGMCU_TIM1_STOP ((uint32_t)0x00001000) +#define DBGMCU_TIM2_STOP ((uint32_t)0x00002000) +#define DBGMCU_TIM3_STOP ((uint32_t)0x00004000) + +uint32_t DBGMCU_GetREVID(void); +uint32_t DBGMCU_GetDEVID(void); +uint32_t __get_DEBUG_CR(void); +void __set_DEBUG_CR(uint32_t value); +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); +uint32_t DBGMCU_GetCHIPID( void ); +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Code/DAP_X033/Peripheral/inc/ch32x035_dma.h b/Code/DAP_X033/Peripheral/inc/ch32x035_dma.h new file mode 100644 index 0000000..88b6c87 --- /dev/null +++ b/Code/DAP_X033/Peripheral/inc/ch32x035_dma.h @@ -0,0 +1,184 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_dma.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for the + * DMA firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_DMA_H +#define __CH32X035_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +/* DMA Init structure definition */ +typedef struct +{ + uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */ + + uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */ + + uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination. + This parameter can be a value of @ref DMA_data_transfer_direction */ + + uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel. + The data unit is equal to the configuration set in DMA_PeripheralDataSize + or DMA_MemoryDataSize members depending in the transfer direction. */ + + uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + + uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + + uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_peripheral_data_size */ + + uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width. + This parameter can be a value of @ref DMA_memory_data_size */ + + uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_circular_normal_mode. + @note: The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_priority_level */ + + uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer. + This parameter can be a value of @ref DMA_memory_to_memory */ +} DMA_InitTypeDef; + +/* DMA_data_transfer_direction */ +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) + +/* DMA_peripheral_incremented_mode */ +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) + +/* DMA_memory_incremented_mode */ +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) + +/* DMA_peripheral_data_size */ +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) + +/* DMA_memory_data_size */ +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) + +/* DMA_circular_normal_mode */ +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) + +/* DMA_priority_level */ +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) + +/* DMA_memory_to_memory */ +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) + +/* DMA_interrupts_definition */ +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_HT ((uint32_t)0x00000004) +#define DMA_IT_TE ((uint32_t)0x00000008) + +#define DMA1_IT_GL1 ((uint32_t)0x00000001) +#define DMA1_IT_TC1 ((uint32_t)0x00000002) +#define DMA1_IT_HT1 ((uint32_t)0x00000004) +#define DMA1_IT_TE1 ((uint32_t)0x00000008) +#define DMA1_IT_GL2 ((uint32_t)0x00000010) +#define DMA1_IT_TC2 ((uint32_t)0x00000020) +#define DMA1_IT_HT2 ((uint32_t)0x00000040) +#define DMA1_IT_TE2 ((uint32_t)0x00000080) +#define DMA1_IT_GL3 ((uint32_t)0x00000100) +#define DMA1_IT_TC3 ((uint32_t)0x00000200) +#define DMA1_IT_HT3 ((uint32_t)0x00000400) +#define DMA1_IT_TE3 ((uint32_t)0x00000800) +#define DMA1_IT_GL4 ((uint32_t)0x00001000) +#define DMA1_IT_TC4 ((uint32_t)0x00002000) +#define DMA1_IT_HT4 ((uint32_t)0x00004000) +#define DMA1_IT_TE4 ((uint32_t)0x00008000) +#define DMA1_IT_GL5 ((uint32_t)0x00010000) +#define DMA1_IT_TC5 ((uint32_t)0x00020000) +#define DMA1_IT_HT5 ((uint32_t)0x00040000) +#define DMA1_IT_TE5 ((uint32_t)0x00080000) +#define DMA1_IT_GL6 ((uint32_t)0x00100000) +#define DMA1_IT_TC6 ((uint32_t)0x00200000) +#define DMA1_IT_HT6 ((uint32_t)0x00400000) +#define DMA1_IT_TE6 ((uint32_t)0x00800000) +#define DMA1_IT_GL7 ((uint32_t)0x01000000) +#define DMA1_IT_TC7 ((uint32_t)0x02000000) +#define DMA1_IT_HT7 ((uint32_t)0x04000000) +#define DMA1_IT_TE7 ((uint32_t)0x08000000) +#define DMA1_IT_GL8 ((uint32_t)0x10000000) +#define DMA1_IT_TC8 ((uint32_t)0x20000000) +#define DMA1_IT_HT8 ((uint32_t)0x40000000) +#define DMA1_IT_TE8 ((uint32_t)0x80000000) + +/* DMA_flags_definition */ +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) +#define DMA1_FLAG_GL8 ((uint32_t)0x10000000) +#define DMA1_FLAG_TC8 ((uint32_t)0x20000000) +#define DMA1_FLAG_HT8 ((uint32_t)0x40000000) +#define DMA1_FLAG_TE8 ((uint32_t)0x80000000) + +void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx); +void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct); +void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState); +void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber); +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx); +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); +void DMA_ClearFlag(uint32_t DMAy_FLAG); +ITStatus DMA_GetITStatus(uint32_t DMAy_IT); +void DMA_ClearITPendingBit(uint32_t DMAy_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Code/DAP_X033/Peripheral/inc/ch32x035_exti.h b/Code/DAP_X033/Peripheral/inc/ch32x035_exti.h new file mode 100644 index 0000000..0f16f69 --- /dev/null +++ b/Code/DAP_X033/Peripheral/inc/ch32x035_exti.h @@ -0,0 +1,99 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_exti.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for the + * EXTI firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_EXTI_H +#define __CH32X035_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +/* EXTI mode enumeration */ +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +} EXTIMode_TypeDef; + +/* EXTI Trigger enumeration */ +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +} EXTITrigger_TypeDef; + +/* EXTI Init Structure definition */ +typedef struct +{ + uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled. + This parameter can be any combination of @ref EXTI_Lines */ + + EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ +} EXTI_InitTypeDef; + +/* EXTI_Lines */ +#define EXTI_Line0 ((uint32_t)0x00000001) /* External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00000002) /* External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00000004) /* External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00000008) /* External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00000010) /* External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00000020) /* External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00000040) /* External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00000080) /* External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00000100) /* External interrupt line 8 */ +#define EXTI_Line9 ((uint32_t)0x00000200) /* External interrupt line 9 */ +#define EXTI_Line10 ((uint32_t)0x00000400) /* External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00000800) /* External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x00001000) /* External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x00002000) /* External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x00004000) /* External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x00008000) /* External interrupt line 15 */ +#define EXTI_Line16 ((uint32_t)0x00010000) /* External interrupt line 16 */ +#define EXTI_Line17 ((uint32_t)0x00020000) /* External interrupt line 17 */ +#define EXTI_Line18 ((uint32_t)0x00040000) /* External interrupt line 18 */ +#define EXTI_Line19 ((uint32_t)0x00080000) /* External interrupt line 19 */ +#define EXTI_Line20 ((uint32_t)0x00100000) /* External interrupt line 20 */ +#define EXTI_Line21 ((uint32_t)0x00200000) /* External interrupt line 21 */ +#define EXTI_Line22 ((uint32_t)0x00400000) /* External interrupt line 22 */ +#define EXTI_Line23 ((uint32_t)0x00800000) /* External interrupt line 23 */ +#define EXTI_Line24 ((uint32_t)0x01000000) /* External interrupt line 24 Connected to the PC18(SDI on) */ +#define EXTI_Line25 ((uint32_t)0x02000000) /* External interrupt line 25 Connected to the PC19(SDI on) */ +#define EXTI_Line26 ((uint32_t)0x04000000) /* External interrupt line 26 Connected to the PVD Output */ +#define EXTI_Line27 ((uint32_t)0x08000000) /* External interrupt line 27 Connected to the Auto Wake-up event */ +#define EXTI_Line28 ((uint32_t)0x10000000) /* External interrupt line 28 Connected to the the USBFS Wake-up event */ +#define EXTI_Line29 ((uint32_t)0x20000000) /* External interrupt line 29 Connected to the the USB PD Wake-up event */ + + +void EXTI_DeInit(void); +void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); +void EXTI_ClearFlag(uint32_t EXTI_Line); +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClearITPendingBit(uint32_t EXTI_Line); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Code/DAP_X033/Peripheral/inc/ch32x035_flash.h b/Code/DAP_X033/Peripheral/inc/ch32x035_flash.h new file mode 100644 index 0000000..13bfa96 --- /dev/null +++ b/Code/DAP_X033/Peripheral/inc/ch32x035_flash.h @@ -0,0 +1,149 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_flash.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for the FLASH + * firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_FLASH_H +#define __CH32X035_FLASH_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +/* FLASH Status */ +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT, + FLASH_RDP, + FLASH_OP_RANGE_ERROR = 0xFD, + FLASH_ALIGN_ERROR = 0xFE, + FLASH_ADR_RANGE_ERROR = 0xFF, +} FLASH_Status; + +/* Flash_Latency */ +#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */ + +/* Values to be used with devices (1page = 256Byte) */ +#define FLASH_WRProt_Pages0to7 ((uint32_t)0x00000001) /* Write protection of page 0 to 7 */ +#define FLASH_WRProt_Pages8to15 ((uint32_t)0x00000002) /* Write protection of page 8 to 15 */ +#define FLASH_WRProt_Pages16to23 ((uint32_t)0x00000004) /* Write protection of page 16 to 23 */ +#define FLASH_WRProt_Pages24to31 ((uint32_t)0x00000008) /* Write protection of page 24 to 31 */ +#define FLASH_WRProt_Pages32to39 ((uint32_t)0x00000010) /* Write protection of page 32 to 39 */ +#define FLASH_WRProt_Pages40to47 ((uint32_t)0x00000020) /* Write protection of page 40 to 47 */ +#define FLASH_WRProt_Pages48to55 ((uint32_t)0x00000040) /* Write protection of page 48 to 55 */ +#define FLASH_WRProt_Pages56to63 ((uint32_t)0x00000080) /* Write protection of page 56 to 63 */ +#define FLASH_WRProt_Pages64to71 ((uint32_t)0x00000100) /* Write protection of page 64 to 71 */ +#define FLASH_WRProt_Pages72to79 ((uint32_t)0x00000200) /* Write protection of page 72 to 79 */ +#define FLASH_WRProt_Pages80to87 ((uint32_t)0x00000400) /* Write protection of page 80 to 87 */ +#define FLASH_WRProt_Pages88to95 ((uint32_t)0x00000800) /* Write protection of page 88 to 95 */ +#define FLASH_WRProt_Pages96to103 ((uint32_t)0x00001000) /* Write protection of page 96 to 103 */ +#define FLASH_WRProt_Pages104to111 ((uint32_t)0x00002000) /* Write protection of page 104 to 111 */ +#define FLASH_WRProt_Pages112to119 ((uint32_t)0x00004000) /* Write protection of page 112 to 119 */ +#define FLASH_WRProt_Pages120to127 ((uint32_t)0x00008000) /* Write protection of page 120 to 127 */ +#define FLASH_WRProt_Pages128to135 ((uint32_t)0x00010000) /* Write protection of page 128 to 135 */ +#define FLASH_WRProt_Pages136to143 ((uint32_t)0x00020000) /* Write protection of page 136 to 143 */ +#define FLASH_WRProt_Pages144to151 ((uint32_t)0x00040000) /* Write protection of page 144 to 151 */ +#define FLASH_WRProt_Pages152to159 ((uint32_t)0x00080000) /* Write protection of page 152 to 159 */ +#define FLASH_WRProt_Pages160to167 ((uint32_t)0x00100000) /* Write protection of page 160 to 167 */ +#define FLASH_WRProt_Pages168to175 ((uint32_t)0x00200000) /* Write protection of page 168 to 175 */ +#define FLASH_WRProt_Pages176to183 ((uint32_t)0x00400000) /* Write protection of page 176 to 183 */ +#define FLASH_WRProt_Pages184to191 ((uint32_t)0x00800000) /* Write protection of page 184 to 191 */ +#define FLASH_WRProt_Pages192to199 ((uint32_t)0x01000000) /* Write protection of page 192 to 199 */ +#define FLASH_WRProt_Pages200to207 ((uint32_t)0x02000000) /* Write protection of page 200 to 207 */ +#define FLASH_WRProt_Pages208to215 ((uint32_t)0x04000000) /* Write protection of page 208 to 215 */ +#define FLASH_WRProt_Pages216to223 ((uint32_t)0x08000000) /* Write protection of page 216 to 223 */ +#define FLASH_WRProt_Pages224to231 ((uint32_t)0x10000000) /* Write protection of page 224 to 231 */ +#define FLASH_WRProt_Pages232to239 ((uint32_t)0x20000000) /* Write protection of page 232 to 239 */ +#define FLASH_WRProt_Pages240to247 ((uint32_t)0x40000000) /* Write protection of page 240 to 247 */ + + +#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /* Write protection of all Pages */ + +/* Option_Bytes_IWatchdog */ +#define OB_IWDG_SW ((uint8_t)0x01) /* Software IWDG selected */ +#define OB_IWDG_HW ((uint8_t)0x00) /* Hardware IWDG selected */ + +/* Option_Bytes_nRST_STOP */ +#define OB_STOP_NoRST ((uint8_t)0x02) /* No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint8_t)0x00) /* Reset generated when entering in STOP */ + +/* Option_Bytes_nRST_STDBY */ +#define OB_STDBY_NoRST ((uint8_t)0x04) /* No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint8_t)0x00) /* Reset generated when entering in STANDBY */ + +/* Option_Bytes_RST_ENandDT */ +#define OB_RST_NoEN ((uint8_t)0x18) /* Reset IO disable */ +#define OB_RST_EN_DT12ms ((uint8_t)0x10) /* Reset IO enable and Ignore delay time 12ms */ +#define OB_RST_EN_DT1ms ((uint8_t)0x08) /* Reset IO enable and Ignore delay time 1ms */ +#define OB_RST_EN_DT128us ((uint8_t)0x00) /* Reset IO enable and Ignore delay time 128us */ + +/* FLASH_Interrupts */ +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ +#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ +#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */ + +/* FLASH_Flags */ +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ + +/* System_Reset_Start_Mode */ +#define Start_Mode_USER ((uint32_t)0x00000000) +#define Start_Mode_BOOT ((uint32_t)0x00004000) + + +/*Functions used for all CH32V00x devices*/ +void FLASH_SetLatency(uint32_t FLASH_Latency); +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_ErasePage(uint32_t Page_Address); +FLASH_Status FLASH_EraseAllPages(void); +FLASH_Status FLASH_EraseOptionBytes(void); +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); +FLASH_Status FLASH_EnableReadOutProtection(void); +FLASH_Status FLASH_UserOptionByteConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY, uint8_t OB_RST); +uint32_t FLASH_GetUserOptionByte(void); +uint32_t FLASH_GetWriteProtectionOptionByte(void); +FlagStatus FLASH_GetReadOutProtectionStatus(void); +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); +void FLASH_ClearFlag(uint32_t FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); +void FLASH_Unlock_Fast(void); +void FLASH_Lock_Fast(void); +void FLASH_BufReset(void); +void FLASH_BufLoad(uint32_t Address, uint32_t Data0); +void FLASH_ErasePage_Fast(uint32_t Page_Address); +void FLASH_ProgramPage_Fast(uint32_t Page_Address); +void SystemReset_StartMode(uint32_t Mode); +FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length); +FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Code/DAP_X033/Peripheral/inc/ch32x035_gpio.h b/Code/DAP_X033/Peripheral/inc/ch32x035_gpio.h new file mode 100644 index 0000000..c208aa6 --- /dev/null +++ b/Code/DAP_X033/Peripheral/inc/ch32x035_gpio.h @@ -0,0 +1,181 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_gpio.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for the + * GPIO firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_GPIO_H +#define __CH32X035_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +/* Output Maximum frequency selection */ +typedef enum +{ + GPIO_Speed_50MHz = 1, +} GPIOSpeed_TypeDef; + +/* Configuration Mode enumeration */ +typedef enum +{ + GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, /* Only PA0--PA15 and PC16--PC17 support input pull-down */ + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_PP = 0x18 +} GPIOMode_TypeDef; + +/* GPIO Init structure definition */ +typedef struct +{ + uint32_t GPIO_Pin; /* Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIOSpeed_TypeDef */ + + GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIOMode_TypeDef */ +} GPIO_InitTypeDef; + +/* Bit_SET and Bit_RESET enumeration */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +} BitAction; + +/* GPIO_pins_define */ +#define GPIO_Pin_0 ((uint32_t)0x000001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((uint32_t)0x000002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((uint32_t)0x000004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((uint32_t)0x000008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((uint32_t)0x000010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((uint32_t)0x000020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((uint32_t)0x000040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((uint32_t)0x000080) /* Pin 7 selected */ +#define GPIO_Pin_8 ((uint32_t)0x000100) /* Pin 8 selected */ +#define GPIO_Pin_9 ((uint32_t)0x000200) /* Pin 9 selected */ +#define GPIO_Pin_10 ((uint32_t)0x000400) /* Pin 10 selected */ +#define GPIO_Pin_11 ((uint32_t)0x000800) /* Pin 11 selected */ +#define GPIO_Pin_12 ((uint32_t)0x001000) /* Pin 12 selected */ +#define GPIO_Pin_13 ((uint32_t)0x002000) /* Pin 13 selected */ +#define GPIO_Pin_14 ((uint32_t)0x004000) /* Pin 14 selected */ +#define GPIO_Pin_15 ((uint32_t)0x008000) /* Pin 15 selected */ +#define GPIO_Pin_16 ((uint32_t)0x010000) /* Pin 16 selected */ +#define GPIO_Pin_17 ((uint32_t)0x020000) /* Pin 17 selected */ +#define GPIO_Pin_18 ((uint32_t)0x040000) /* Pin 18 selected */ +#define GPIO_Pin_19 ((uint32_t)0x080000) /* Pin 19 selected */ +#define GPIO_Pin_20 ((uint32_t)0x100000) /* Pin 20 selected */ +#define GPIO_Pin_21 ((uint32_t)0x200000) /* Pin 21 selected */ +#define GPIO_Pin_22 ((uint32_t)0x400000) /* Pin 22 selected */ +#define GPIO_Pin_23 ((uint32_t)0x800000) /* Pin 23 selected */ +#define GPIO_Pin_All ((uint32_t)0xFFFFFF) /* All pins selected */ + +/* GPIO_Remap_define */ +/* PCFR1 */ +#define GPIO_PartialRemap1_SPI1 ((uint32_t)0x00100001) /* SPI1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_SPI1 ((uint32_t)0x00100002) /* SPI1 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_SPI1 ((uint32_t)0x00100003) /* SPI1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_I2C1 ((uint32_t)0x08000004) /* I2C1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_I2C1 ((uint32_t)0x08000008) /* I2C1 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_I2C1 ((uint32_t)0x0800000C) /* I2C1 Partial3 Alternate Function mapping */ +#define GPIO_PartialRemap4_I2C1 ((uint32_t)0x08000010) /* I2C1 Partial4 Alternate Function mapping */ +#define GPIO_FullRemap_I2C1 ((uint32_t)0x08000014) /* I2C1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_USART1 ((uint32_t)0x00150020) /* USART1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_USART1 ((uint32_t)0x00150040) /* USART1 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_USART1 ((uint32_t)0x00150060) /* USART1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_USART2 ((uint32_t)0x08000080) /* USART2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_USART2 ((uint32_t)0x08000100) /* USART2 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_USART2 ((uint32_t)0x08000180) /* USART2 Partial3 Alternate Function mapping */ +#define GPIO_FullRemap_USART2 ((uint32_t)0x08000200) /* USART2 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_USART3 ((uint32_t)0x00100400) /* USART3 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_USART3 ((uint32_t)0x00100800) /* USART3 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_USART3 ((uint32_t)0x00100C00) /* USART3 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_USART4 ((uint32_t)0x08001000) /* USART4 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_USART4 ((uint32_t)0x08002000) /* USART4 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_USART4 ((uint32_t)0x08003000) /* USART4 Partial3 Alternate Function mapping */ +#define GPIO_PartialRemap4_USART4 ((uint32_t)0x08004000) /* USART4 Partial4 Alternate Function mapping */ +#define GPIO_FullRemap_USART4 ((uint32_t)0x08007000) /* USART4 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM1 ((uint32_t)0x08400001) /* TIM1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM1 ((uint32_t)0x08400002) /* TIM1 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_TIM1 ((uint32_t)0x08400003) /* TIM1 Partial3 Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((uint32_t)0x08400004) /* TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x08200004) /* TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x08200008) /* TIM2 Partial2 Alternate Function mapping */ +#define GPIO_PartialRemap3_TIM2 ((uint32_t)0x0820000C) /* TIM2 Partial3 Alternate Function mapping */ +#define GPIO_PartialRemap4_TIM2 ((uint32_t)0x08200010) /* TIM2 Partial4 Alternate Function mapping */ +#define GPIO_PartialRemap5_TIM2 ((uint32_t)0x08200014) /* TIM2 Partial5 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((uint32_t)0x08200018) /* TIM2 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM3 ((uint32_t)0x00300020) /* TIM3 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM3 ((uint32_t)0x00300040) /* TIM3 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM3 ((uint32_t)0x00300060) /* TIM3 Full Alternate Function mapping */ +#define GPIO_Remap_PIOC ((uint32_t)0x00200080) /* PIOC Alternate Function mapping */ +#define GPIO_Remap_SWJ_Disable ((uint32_t)0x08300400) /* SDI Disabled (SDI) */ + +/* GPIO_Port_Sources */ +#define GPIO_PortSourceGPIOA ((uint8_t)0x00) +#define GPIO_PortSourceGPIOB ((uint8_t)0x01) +#define GPIO_PortSourceGPIOC ((uint8_t)0x02) + +/* GPIO_Pin_sources */ +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) +#define GPIO_PinSource16 ((uint8_t)0x10) +#define GPIO_PinSource17 ((uint8_t)0x11) +#define GPIO_PinSource18 ((uint8_t)0x12) +#define GPIO_PinSource19 ((uint8_t)0x13) +#define GPIO_PinSource20 ((uint8_t)0x14) +#define GPIO_PinSource21 ((uint8_t)0x15) +#define GPIO_PinSource22 ((uint8_t)0x16) +#define GPIO_PinSource23 ((uint8_t)0x17) + + +void GPIO_DeInit(GPIO_TypeDef *GPIOx); +void GPIO_AFIODeInit(void); +void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct); +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); +uint32_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); +uint32_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx); +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef *GPIOx, uint32_t PortVal); +void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint16_t GPIO_PinSource); +void GPIO_IPD_Unused(void); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Code/DAP_X033/Peripheral/inc/ch32x035_i2c.h b/Code/DAP_X033/Peripheral/inc/ch32x035_i2c.h new file mode 100644 index 0000000..37e29db --- /dev/null +++ b/Code/DAP_X033/Peripheral/inc/ch32x035_i2c.h @@ -0,0 +1,416 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_i2c.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for the + * I2C firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_I2C_H +#define __CH32X035_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +/* I2C Init structure definition */ +typedef struct +{ + uint32_t I2C_ClockSpeed; /* Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint16_t I2C_Mode; /* Specifies the I2C mode. + This parameter can be a value of @ref I2C_mode */ + + uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint16_t I2C_OwnAddress1; /* Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint16_t I2C_Ack; /* Enables or disables the acknowledgement. + This parameter can be a value of @ref I2C_acknowledgement */ + + uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged. + This parameter can be a value of @ref I2C_acknowledged_address */ +} I2C_InitTypeDef; + +/* I2C_mode */ +#define I2C_Mode_I2C ((uint16_t)0x0000) + +/* I2C_duty_cycle_in_fast_mode */ +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ + +/* I2C_acknowledgement */ +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) + +/* I2C_transfer_direction */ +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) + +/* I2C_acknowledged_address */ +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) + +/* I2C_registers */ +#define I2C_Register_CTLR1 ((uint8_t)0x00) +#define I2C_Register_CTLR2 ((uint8_t)0x04) +#define I2C_Register_OADDR1 ((uint8_t)0x08) +#define I2C_Register_OADDR2 ((uint8_t)0x0C) +#define I2C_Register_DATAR ((uint8_t)0x10) +#define I2C_Register_STAR1 ((uint8_t)0x14) +#define I2C_Register_STAR2 ((uint8_t)0x18) +#define I2C_Register_CKCFGR ((uint8_t)0x1C) +#define I2C_Register_RTR ((uint8_t)0x20) + +/* I2C_PEC_position */ +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) + +/* I2C_NACK_position */ +#define I2C_NACKPosition_Next ((uint16_t)0x0800) +#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) + +/* I2C_interrupts_definition */ +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) + +/* I2C_interrupts_definition */ +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +/* SR2 register flags */ +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/* SR1 register flags */ +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + +/****************I2C Master Events (Events grouped in order of communication)********************/ + +/******************************************************************************************************************** + * @brief Start communicate + * + * After master use I2C_GenerateSTART() function sending the START condition,the master + * has to wait for event 5(the Start condition has been correctly + * released on the I2C bus ). + * + */ +/* EVT5 */ +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ + +/******************************************************************************************************************** + * @brief Address Acknowledge + * + * When start condition correctly released on the bus(check EVT5), the + * master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate + * it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will be set: + * + * + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED + * is set + * + * 3) In case of 10-Bit addressing mode, the master (after generating the START + * and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode. + * Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent + * on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part + * of the 10-bit address (LSB) . Then master should wait for event 6. + * + * + */ + +/* EVT6 */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +/*EVT9 */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * If START condition has generated and slave address + * been acknowledged. then the master has to check one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EVT7 then use + * I2C_ReceiveData() function to read the data received from the slave . + * + * 2) Master Transmitter mode: The master use I2C_SendData() function to send data + * then to wait on event EVT8 or EVT8_2. + * These two events are similar: + * - EVT8 means that the data has been written in the data register and is + * being shifted out. + * - EVT8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EVT8 is sufficient for the application. + * Using EVT8_2 will leads to a slower communication speed but will more reliable . + * EVT8_2 is also more suitable than EVT8 for testing on the last data transmission + * + * + * Note: + * In case the user software does not guarantee that this event EVT7 is managed before + * the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower. + * + * + */ + +/* Master Receive mode */ +/* EVT7 */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ + +/* Master Transmitter mode*/ +/* EVT8 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +/* EVT8_2 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + +/******************I2C Slave Events (Events grouped in order of communication)******************/ + +/******************************************************************************************************************** + * @brief Start Communicate events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a start condition of master device generate on the bus. + * If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus. + * + * + * + * a) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * b) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_OwnAddress2Config() and enabled + * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * c) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) + * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. + * + */ + +/* EVT1 */ +/* a) Case of One Single Address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ + +/* b) Case of Dual address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ + +/* c) Case of General Call enabled for the slave */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * Wait on one of these events when EVT1 has already been checked : + * + * - Slave Receiver mode: + * - EVT2--The device is expecting to receive a data byte . + * - EVT4--The device is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EVT3--When a byte has been transmitted by the slave and the Master is expecting + * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and + * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee + * the EVT3 is managed before the current byte end of transfer The second one can optionally + * be used. + * - EVT3_2--When the master sends a NACK to tell slave device that data transmission + * shall end . The slave device has to stop sending + * data bytes and wait a Stop condition from bus. + * + * Note: + * If the user software does not guarantee that the event 2 is + * managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time . + * In this case the communication will be slower. + * + */ + +/* Slave Receiver mode*/ +/* EVT2 */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +/* EVT4 */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ + +/* Slave Transmitter mode*/ +/* EVT3 */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +/*EVT3_2 */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + + +void I2C_DeInit(I2C_TypeDef *I2Cx); +void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address); +void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState); +void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data); +uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx); +void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction); +uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register); +void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition); +void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition); +void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState); +uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx); +void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle); + + +/***************************************************************************************** + * + * I2C State Monitoring Functions + * + **************************************************************************************** + * This I2C driver provides three different ways for I2C state monitoring + * profit the application requirements and constraints: + * + * + * a) First way: + * Using I2C_CheckEvent() function: + * It compares the status registers (STARR1 and STAR2) content to a given event + * (can be the combination of more flags). + * If the current status registers includes the given flags will return SUCCESS. + * and if the current status registers miss flags will returns ERROR. + * - When to use: + * - This function is suitable for most applications as well as for startup + * activity since the events are fully described in the product reference manual + * (CH64xRM). + * - It is also suitable for users who need to define their own events. + * - Limitations: + * - If an error occurs besides to the monitored error, + * the I2C_CheckEvent() function may return SUCCESS despite the communication + * in corrupted state. it is suggeted to use error interrupts to monitor the error + * events and handle them in IRQ handler. + * + * + * Note: + * The following functions are recommended for error management: : + * - I2C_ITConfig() main function of configure and enable the error interrupts. + * - I2Cx_ER_IRQHandler() will be called when the error interrupt happen. + * Where x is the peripheral instance (I2C1, I2C2 ...) + * - I2Cx_ER_IRQHandler() will call I2C_GetFlagStatus() or I2C_GetITStatus() functions + * to determine which error occurred. + * - I2C_ClearFlag() \ I2C_ClearITPendingBit() \ I2C_SoftwareResetCmd() + * \ I2C_GenerateStop() will be use to clear the error flag and source, + * and return to correct communication status. + * + * + * b) Second way: + * Using the function to get a single word(uint32_t) composed of status register 1 and register 2. + * (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1). + * - When to use: + * + * - This function is suitable for the same applications above but it + * don't have the limitations of I2C_GetFlagStatus() function . + * The returned value could be compared to events already defined in the + * library (ch64x_i2c.h) or to custom values defined by user. + * - This function can be used to monitor the status of multiple flags simultaneously. + * - Contrary to the I2C_CheckEvent () function, this function can choose the time to + * accept the event according to the user's needs (when all event flags are set and + * no other flags are set, or only when the required flags are set) + * + * - Limitations: + * - User may need to define his own events. + * - Same remark concerning the error management is applicable for this + * function if user decides to check only regular communication flags (and + * ignores error flags). + * + * + * c) Third way: + * Using the function I2C_GetFlagStatus() get the status of + * one single flag . + * - When to use: + * - This function could be used for specific applications or in debug phase. + * - It is suitable when only one flag checking is needed . + * + * - Limitations: + * - Call this function to access the status register. Some flag bits may be cleared. + * - Function may need to be called twice or more in order to monitor one single event. + */ + + + +/********************************************************* + * + * a) Basic state monitoring(First way) + ******************************************************** + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); +/********************************************************* + * + * b) Advanced state monitoring(Second way:) + ******************************************************** + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); +/********************************************************* + * + * c) Flag-based state monitoring(Third way) + ********************************************************* + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); + +void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT); +void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Code/DAP_X033/Peripheral/inc/ch32x035_iwdg.h b/Code/DAP_X033/Peripheral/inc/ch32x035_iwdg.h new file mode 100644 index 0000000..4afc622 --- /dev/null +++ b/Code/DAP_X033/Peripheral/inc/ch32x035_iwdg.h @@ -0,0 +1,50 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_iwdg.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for the + * IWDG firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_IWDG_H +#define __CH32X035_IWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +/* IWDG_WriteAccess */ +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) + +/* IWDG_prescaler */ +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) + +/* IWDG_Flag */ +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) + +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); +void IWDG_SetReload(uint16_t Reload); +void IWDG_ReloadCounter(void); +void IWDG_Enable(void); +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Code/DAP_X033/Peripheral/inc/ch32x035_misc.h b/Code/DAP_X033/Peripheral/inc/ch32x035_misc.h new file mode 100644 index 0000000..aeda03c --- /dev/null +++ b/Code/DAP_X033/Peripheral/inc/ch32x035_misc.h @@ -0,0 +1,45 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_misc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for the + * miscellaneous firmware library functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_MISC_H +#define __CH32X035_MISC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +/* NVIC Init Structure definition */ +typedef struct +{ + uint8_t NVIC_IRQChannel; + uint8_t NVIC_IRQChannelPreemptionPriority; + uint8_t NVIC_IRQChannelSubPriority; + FunctionalState NVIC_IRQChannelCmd; +} NVIC_InitTypeDef; + +/* Preemption_Priority_Group */ +#define NVIC_PriorityGroup_0 ((uint32_t)0x00) +#define NVIC_PriorityGroup_1 ((uint32_t)0x01) +#define NVIC_PriorityGroup_2 ((uint32_t)0x02) +#define NVIC_PriorityGroup_3 ((uint32_t)0x03) +#define NVIC_PriorityGroup_4 ((uint32_t)0x04) + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Code/DAP_X033/Peripheral/inc/ch32x035_opa.h b/Code/DAP_X033/Peripheral/inc/ch32x035_opa.h new file mode 100644 index 0000000..e408a6b --- /dev/null +++ b/Code/DAP_X033/Peripheral/inc/ch32x035_opa.h @@ -0,0 +1,221 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_opa.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for the + * OPA firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_OPA_H +#define __CH32X035_OPA_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +/* OPA_member_enumeration */ +typedef enum +{ + OPA1 = 0, + OPA2 +} OPA_Num_TypeDef; + +/* OPA_out_channel_enumeration */ +typedef enum +{ + OUT_IO_OUT0 = 0, + OUT_IO_OUT1 +} OPA_Mode_TypeDef; + +/* OPA_PSEL_enumeration */ +typedef enum +{ + CHP0 = 0, + CHP1, + CHP2, + CHP_OFF +} OPA_PSEL_TypeDef; + +/* OPA_FB_enumeration */ +typedef enum +{ + FB_OFF = 0, + FB_ON +} OPA_FB_TypeDef; + +/* OPA_NSEL_enumeration */ +typedef enum +{ + CHN0 = 0, + CHN1, + CHN2_PGA_16xIN, + CHN_PGA_4xIN, + CHN_PGA_8xIN, + CHN_PGA_16xIN, + CHN_PGA_32xIN, + CHN_OFF +} OPA_NSEL_TypeDef; + +/* OPA_PSEL_POLL_enumeration */ +typedef enum +{ + CHP_OPA1_OFF_OPA2_OFF = 0, + CHP_OPA1_ON_OPA2_OFF, + CHP_OPA1_OFF_OPA2_ON, + CHP_OPA1_ON_OPA2_ON +} OPA_PSEL_POLL_TypeDef; + +/* OPA_BKIN_EN_enumeration */ +typedef enum +{ + BKIN_OPA1_OFF_OPA2_OFF = 0, + BKIN_OPA1_ON_OPA2_OFF, + BKIN_OPA1_OFF_OPA2_ON, + BKIN_OPA1_ON_OPA2_ON +} OPA_BKIN_EN_TypeDef; + +/* OPA_RST_EN_enumeration */ +typedef enum +{ + RST_OPA1_OFF_OPA2_OFF = 0, + RST_OPA1_ON_OPA2_OFF, + RST_OPA1_OFF_OPA2_ON, + RST_OPA1_ON_OPA2_ON +} OPA_RST_EN_TypeDef; + +/* OPA_BKIN_SEL_enumeration */ +typedef enum +{ + BKIN_OPA1_TIM1_OPA2_TIM2 = 0, + BKIN_OPA1_TIM2_OPA2_TIM1 +} OPA_BKIN_SEL_TypeDef; + +/* OPA_OUT_IE_enumeration */ +typedef enum +{ + OUT_IE_OPA1_OFF_OPA2_OFF = 0, + OUT_IE_OPA1_ON_OPA2_OFF, + OUT_IE_OPA1_OFF_OPA2_ON, + OUT_IE_OPA1_ON_OPA2_ON +} OPA_OUT_IE_TypeDef; + +/* OPA_CNT_IE_enumeration */ +typedef enum +{ + CNT_IE_OFF = 0, + CNT_IE_ON, +} OPA_CNT_IE_TypeDef; + +/* OPA_NMI_IE_enumeration */ +typedef enum +{ + NMI_IE_OFF = 0, + NMI_IE_ON, +} OPA_NMI_IE_TypeDef; + +/* OPA_PSEL_POLL_NUM_enumeration */ +typedef enum +{ + CHP_POLL_NUM_1 = 0, + CHP_POLL_NUM_2, + CHP_POLL_NUM_3 +} OPA_PSEL_POLL_NUM_TypeDef; + + +/* OPA Init Structure definition */ +typedef struct +{ + uint16_t OPA_POLL_Interval; /* OPA polling interval = (OPA_POLL_Interval+1)*1us + This parameter must range from 0 to 0x1FF.*/ + OPA_Num_TypeDef OPA_NUM; /* Specifies the members of OPA */ + OPA_Mode_TypeDef Mode; /* Specifies the mode of OPA */ + OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ + OPA_FB_TypeDef FB; /* Specifies the internal feedback resistor of OPA */ + OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ + OPA_PSEL_POLL_TypeDef PSEL_POLL; /* Specifies the positive channel poll of OPA */ + OPA_BKIN_EN_TypeDef BKIN_EN; /* Specifies the brake input source of OPA */ + OPA_RST_EN_TypeDef RST_EN; /* Specifies the reset source of OPA */ + OPA_BKIN_SEL_TypeDef BKIN_SEL; /* Specifies the brake input source selection of OPA */ + OPA_OUT_IE_TypeDef OUT_IE; /* Specifies the out interrupt of OPA */ + OPA_CNT_IE_TypeDef CNT_IE; /* Specifies the out interrupt rising edge of sampling data */ + OPA_NMI_IE_TypeDef NMI_IE; /* Specifies the out NIM interrupt of OPA */ + OPA_PSEL_POLL_NUM_TypeDef POLL_NUM; /* Specifies the number of forward inputs*/ +} OPA_InitTypeDef; + +/* CMP_member_enumeration */ +typedef enum +{ + CMP1 = 0, + CMP2, + CMP3 +} CMP_Num_TypeDef; + +/* CMP_out_channel_enumeration */ +typedef enum +{ + OUT_IO_TIM2 = 0, + OUT_IO0 +} CMP_Mode_TypeDef; + +/* CMP_NSEL_enumeration */ +typedef enum +{ + CMP_CHN0 = 0, + CMP_CHN1, +} CMP_NSEL_TypeDef; + +/* CMP_PSEL_enumeration */ +typedef enum +{ + CMP_CHP1 = 0, + CMP_CHP2, +} CMP_PSEL_TypeDef; + +/* CMP_HYEN_enumeration */ +typedef enum +{ + CMP_HYEN1 = 0, + CMP_HYEN2, +} CMP_HYEN_TypeDef; + +/* CMP Init Structure definition */ +typedef struct +{ + CMP_Num_TypeDef CMP_NUM; /* Specifies the members of CMP */ + CMP_Mode_TypeDef Mode; /* Specifies the mode of CMP */ + CMP_NSEL_TypeDef NSEL; /* Specifies the negative channel of CMP */ + CMP_PSEL_TypeDef PSEL; /* Specifies the positive channel of CMP */ + CMP_HYEN_TypeDef HYEN; /* Specifies the hysteresis comparator of CMP */ +} CMP_InitTypeDef; + +/* OPA_flags_definition */ +#define OPA_FLAG_OUT_OPA1 ((uint16_t)0x1000) +#define OPA_FLAG_OUT_OPA2 ((uint16_t)0x2000) +#define OPA_FLAG_OUT_CNT ((uint16_t)0x4000) + +void OPA_Unlock(void); +void OPA_Lock(void); +void OPA_POLL_Unlock(void); +void OPA_POLL_Lock(void); +void OPA_CMP_Unlock(void); +void OPA_CMP_Lock(void); +void OPA_Init(OPA_InitTypeDef *OPA_InitStruct); +void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct); +void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState); +void OPA_CMP_Init(CMP_InitTypeDef *CMP_InitStruct); +void OPA_CMP_StructInit(CMP_InitTypeDef *CMP_InitStruct); +void OPA_CMP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState); +FlagStatus OPA_GetFlagStatus( uint16_t OPA_FLAG); +void OPA_ClearFlag(uint16_t OPA_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Code/DAP_X033/Peripheral/inc/ch32x035_pwr.h b/Code/DAP_X033/Peripheral/inc/ch32x035_pwr.h new file mode 100644 index 0000000..d075e12 --- /dev/null +++ b/Code/DAP_X033/Peripheral/inc/ch32x035_pwr.h @@ -0,0 +1,50 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_pwr.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for the PWR + * firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_PWR_H +#define __CH32X035_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +/* PVD_detection_level */ +#define PWR_PVDLevel_2V1 ((uint32_t)0x00000000) +#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) +#define PWR_PVDLevel_3V0 ((uint32_t)0x00000040) +#define PWR_PVDLevel_4V0 ((uint32_t)0x00000060) + +/* STOP_mode_entry */ +#define PWR_STOPEntry_WFI ((uint8_t)0x01) +#define PWR_STOPEntry_WFE ((uint8_t)0x02) + +/* PWR_Flag */ +#define PWR_FLAG_PVDO ((uint32_t)0x00000004) +#define PWR_FLAG_FLASH ((uint32_t)0x00000020) + +/* PWR_VDD_Supply_Voltage */ +typedef enum {PWR_VDD_5V = 0, PWR_VDD_3V3 = !PWR_VDD_5V} PWR_VDD; + +void PWR_DeInit(void); +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); +void PWR_EnterSTOPMode(uint8_t PWR_STOPEntry); +void PWR_EnterSTANDBYMode(void); +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); +PWR_VDD PWR_VDD_SupplyVoltage(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Code/DAP_X033/Peripheral/inc/ch32x035_rcc.h b/Code/DAP_X033/Peripheral/inc/ch32x035_rcc.h new file mode 100644 index 0000000..11320da --- /dev/null +++ b/Code/DAP_X033/Peripheral/inc/ch32x035_rcc.h @@ -0,0 +1,111 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_rcc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file provides all the RCC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_RCC_H +#define __CH32X035_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +/* RCC_Exported_Types */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */ + uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */ + uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */ + uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */ +} RCC_ClocksTypeDef; + +/* AHB_clock_source */ +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000010) +#define RCC_SYSCLK_Div3 ((uint32_t)0x00000020) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000030) +#define RCC_SYSCLK_Div5 ((uint32_t)0x00000040) +#define RCC_SYSCLK_Div6 ((uint32_t)0x00000050) +#define RCC_SYSCLK_Div7 ((uint32_t)0x00000060) +#define RCC_SYSCLK_Div8 ((uint32_t)0x00000070) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div32 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000F0) + +/* AHB_peripheral */ +#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) +#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) +#define RCC_AHBPeriph_USBFS ((uint32_t)0x00001000) +#define RCC_AHBPeriph_IO2W ((uint32_t)0x00002000) +#define RCC_AHBPeriph_USBPD ((uint32_t)0x00020000) + +/* APB2_peripheral */ +#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) +#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) +#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) +#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) +#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) +#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) +#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) + +/* APB1_peripheral */ +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) +#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) +#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) +#define RCC_APB1Periph_USART4 ((uint32_t)0x00080000) +#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) + +/* Clock_source_to_output_on_MCO_pin */ +#define RCC_MCO_NoClock ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) + +/* RCC_Flag */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_OPARST ((uint8_t)0x79) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) + +/* SysTick_clock_source */ +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) + + +void RCC_DeInit(void); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks); +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_MCOConfig(uint8_t RCC_MCO); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Code/DAP_X033/Peripheral/inc/ch32x035_spi.h b/Code/DAP_X033/Peripheral/inc/ch32x035_spi.h new file mode 100644 index 0000000..27f624c --- /dev/null +++ b/Code/DAP_X033/Peripheral/inc/ch32x035_spi.h @@ -0,0 +1,153 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_spi.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for the + * SPI firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_SPI_H +#define __CH32X035_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +/* SPI Init structure definition */ +typedef struct +{ + uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_data_direction */ + + uint16_t SPI_Mode; /* Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint16_t SPI_DataSize; /* Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint16_t SPI_CPOL; /* Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler. + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_transmission */ + + uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */ +} SPI_InitTypeDef; + +/* SPI_data_direction */ +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) + +/* SPI_mode */ +#define SPI_Mode_Master ((uint16_t)0x0104) +#define SPI_Mode_Slave ((uint16_t)0x0000) + +/* SPI_data_size */ +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) + +/* SPI_Clock_Polarity */ +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002) + +/* SPI_Clock_Phase */ +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) + +/* SPI_Slave_Select_management */ +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) + +/* SPI_BaudRate_Prescaler */ +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) + +/* SPI_MSB_LSB_transmission */ +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB ((uint16_t)0x0080)//not support SPI slave mode + +/* SPI_I2S_DMA_transfer_requests */ +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) + +/* SPI_NSS_internal_software_management */ +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) + +/* SPI_CRC_Transmit_Receive */ +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) + +/* SPI_direction_transmit_receive */ +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) + +/* SPI_I2S_interrupts_definition */ +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) + +/* SPI_I2S_flags_definition */ +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) + +void SPI_I2S_DeInit(SPI_TypeDef *SPIx); +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct); +void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct); +void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); +void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); +void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); +void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data); +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState); +void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize); +void SPI_TransmitCRC(SPI_TypeDef *SPIx); +void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState); +uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx); +void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction); +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); +void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Code/DAP_X033/Peripheral/inc/ch32x035_tim.h b/Code/DAP_X033/Peripheral/inc/ch32x035_tim.h new file mode 100644 index 0000000..0cfda49 --- /dev/null +++ b/Code/DAP_X033/Peripheral/inc/ch32x035_tim.h @@ -0,0 +1,530 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_tim.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for the + * TIM firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_TIM_H +#define __CH32X035_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +/* TIM Time Base Init structure definition */ +typedef struct +{ + uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_CounterMode; /* Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode (TIM1 and TIM2) */ + + uint16_t TIM_Period; /* Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF. */ + + uint16_t TIM_ClockDivision; /* Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_TimeBaseInitTypeDef; + +/* TIM Output Compare Init structure definition */ +typedef struct +{ + uint16_t TIM_OCMode; /* Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_state */ + + uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_state + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_OCPolarity; /* Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_OCInitTypeDef; + +/* TIM Input Capture Init structure definition */ +typedef struct +{ + uint16_t TIM_Channel; /* Specifies the TIM channel. + This parameter can be a value of @ref TIM_Channel */ + + uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint16_t TIM_ICSelection; /* Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint16_t TIM_ICFilter; /* Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitTypeDef; + +/* BDTR structure definition */ +typedef struct +{ + uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ + + uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state. + This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters. + This parameter can be a value of @ref Lock_level */ + + uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref Break_Input_enable_disable */ + + uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref Break_Polarity */ + + uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BDTRInitTypeDef; + +/* TIM_Output_Compare_and_PWM_modes */ +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) + +/* TIM_One_Pulse_Mode */ +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) + +/* TIM_Channel */ +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) + +/* TIM_Clock_Division_CKD */ +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) + +/* TIM_Counter_Mode */ +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) + +/* TIM_Output_Compare_Polarity */ +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) + +/* TIM_Output_Compare_N_Polarity */ +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) + +/* TIM_Output_Compare_state */ +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) + +/* TIM_Output_Compare_N_state */ +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) + +/* TIM_Capture_Compare_state */ +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) + +/* TIM_Capture_Compare_N_state */ +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) + +/* Break_Input_enable_disable */ +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) + +/* Break_Polarity */ +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) + +/* TIM_AOE_Bit_Set_Reset */ +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) + +/* Lock_level */ +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) + +/* OSSI_Off_State_Selection_for_Idle_mode_state */ +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) + +/* OSSR_Off_State_Selection_for_Run_mode_state */ +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Idle_State */ +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Output_Compare_N_Idle_State */ +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Input_Capture_Polarity */ +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) + +/* TIM_Input_Capture_Selection */ +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ + +/* TIM_Input_Capture_Prescaler */ +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ + +/* TIM_interrupt_sources */ +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) + +/* TIM_DMA_Base_address */ +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) + +/* TIM_DMA_Burst_Length */ +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) + +/* TIM_DMA_sources */ +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) + +/* TIM_External_Trigger_Prescaler */ +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) + +/* TIM_Internal_Trigger_Selection */ +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) + +/* TIM_TIx_External_Clock_Source */ +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) + +/* TIM_External_Trigger_Polarity */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) + +/* TIM_Prescaler_Reload_Mode */ +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) + +/* TIM_Forced_Action */ +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) + +/* TIM_Encoder_Mode */ +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) + +/* TIM_Event_Source */ +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) + +/* TIM_Update_Source */ +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \ + or the setting of UG bit, or an update generation \ + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ + +/* TIM_Output_Compare_Preload_State */ +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Fast_State */ +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Clear_State */ +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) + +/* TIM_Trigger_Output_Source */ +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) + +/* TIM_Slave_Mode */ +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) + +/* TIM_Master_Slave_Mode */ +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) + +/* TIM_Flags */ +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) + +/* TIM_Legacy */ +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers + +/* TIM_Supersede_Mode_OC1 */ +#define TIM_Supersede_Mode_OC1_H ((uint16_t)0x0000) +#define TIM_Supersede_Mode_OC1_L ((uint16_t)0x0010) + +/* TIM_Supersede_Mode_OC2 */ +#define TIM_Supersede_Mode_OC2_H ((uint16_t)0x0000) +#define TIM_Supersede_Mode_OC2_L ((uint16_t)0x0020) + +/* TIM_Supersede_Mode_OC3 */ +#define TIM_Supersede_Mode_OC3_H ((uint16_t)0x0000) +#define TIM_Supersede_Mode_OC3_L ((uint16_t)0x0040) + +/* TIM_Supersede_Mode_OC4 */ +#define TIM_Supersede_Mode_OC4_H ((uint16_t)0x0000) +#define TIM_Supersede_Mode_OC4_L ((uint16_t)0x0080) + + + +void TIM_DeInit(TIM_TypeDef *TIMx); +void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); +void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState); +void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource); +void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState); +void TIM_InternalClockConfig(TIM_TypeDef *TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); +void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode); +void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); +void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); +void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); +void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); +void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); +void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource); +void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode); +void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter); +void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload); +void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1); +void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2); +void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3); +void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4); +void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD); +uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx); +uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx); +uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx); +uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx); +uint16_t TIM_GetCounter(TIM_TypeDef *TIMx); +uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT); +void TIM_CaptureModeCmd(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_IndicateCaptureLevelCmd(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_OC12_SupersedeModeCmd(TIM_TypeDef *TIMx, uint16_t TIM_Supersede_Mode_OC1, uint16_t TIM_Supersede_Mode_OC2, FunctionalState NewState); +void TIM_OC34_SupersedeModeCmd(TIM_TypeDef *TIMx, uint16_t TIM_Supersede_Mode_OC3, uint16_t TIM_Supersede_Mode_OC4, FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Code/DAP_X033/Peripheral/inc/ch32x035_usart.h b/Code/DAP_X033/Peripheral/inc/ch32x035_usart.h new file mode 100644 index 0000000..79fe683 --- /dev/null +++ b/Code/DAP_X033/Peripheral/inc/ch32x035_usart.h @@ -0,0 +1,185 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_usart.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for the + * USART firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_USART_H +#define __CH32X035_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +/* USART Init Structure definition */ +typedef struct +{ + uint32_t USART_BaudRate; /* This member configures the USART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) + - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ + + uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint16_t USART_Parity; /* Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode */ + + uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} USART_InitTypeDef; + +/* USART Clock Init Structure definition */ +typedef struct +{ + uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_Clock */ + + uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +} USART_ClockInitTypeDef; + +/* USART_Word_Length */ +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +/* USART_Stop_Bits */ +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) + +/* USART_Parity */ +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) + +/* USART_Mode */ +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) + +/* USART_Hardware_Flow_Control */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) + +/* USART_Clock */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) + +/* USART_Clock_Polarity */ +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) + +/* USART_Clock_Phase */ +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) + +/* USART_Last_Bit */ +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) + +/* USART_Interrupt_definition */ +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_ORE_RX ((uint16_t)0x0325) +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE_ER ((uint16_t)0x0360) +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) + +#define USART_IT_ORE USART_IT_ORE_ER + +/* USART_DMA_Requests */ +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) + +/* USART_WakeUp_methods */ +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) + +/* USART_LIN_Break_Detection_Length */ +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) + +/* USART_IrDA_Low_Power */ +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) + +/* USART_Flags */ +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) + +void USART_DeInit(USART_TypeDef *USARTx); +void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct); +void USART_StructInit(USART_InitTypeDef *USART_InitStruct); +void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct); +void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState); +void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState); +void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address); +void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp); +void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength); +void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_SendData(USART_TypeDef *USARTx, uint16_t Data); +uint16_t USART_ReceiveData(USART_TypeDef *USARTx); +void USART_SendBreak(USART_TypeDef *USARTx); +void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime); +void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler); +void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode); +void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState); +FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG); +void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT); +void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Code/DAP_X033/Peripheral/inc/ch32x035_usb.h b/Code/DAP_X033/Peripheral/inc/ch32x035_usb.h new file mode 100644 index 0000000..68647b0 --- /dev/null +++ b/Code/DAP_X033/Peripheral/inc/ch32x035_usb.h @@ -0,0 +1,522 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_usb.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for the USB + * firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_USB_H +#define __CH32X035_USB_H + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +/*******************************************************************************/ +/* Header File */ +#include "stdint.h" + +/*******************************************************************************/ +/* USB Communication Related Macro Definition */ + +/* USB PID */ +#ifndef USB_PID_SETUP +#define USB_PID_NULL 0x00 +#define USB_PID_SOF 0x05 +#define USB_PID_SETUP 0x0D +#define USB_PID_IN 0x09 +#define USB_PID_OUT 0x01 +#define USB_PID_NYET 0x06 +#define USB_PID_ACK 0x02 +#define USB_PID_NAK 0x0A +#define USB_PID_STALL 0x0E +#define USB_PID_DATA0 0x03 +#define USB_PID_DATA1 0x0B +#define USB_PID_PRE 0x0C +#endif + +/* USB standard device request code */ +#ifndef USB_GET_DESCRIPTOR +#define USB_GET_STATUS 0x00 +#define USB_CLEAR_FEATURE 0x01 +#define USB_SET_FEATURE 0x03 +#define USB_SET_ADDRESS 0x05 +#define USB_GET_DESCRIPTOR 0x06 +#define USB_SET_DESCRIPTOR 0x07 +#define USB_GET_CONFIGURATION 0x08 +#define USB_SET_CONFIGURATION 0x09 +#define USB_GET_INTERFACE 0x0A +#define USB_SET_INTERFACE 0x0B +#define USB_SYNCH_FRAME 0x0C +#endif + +#define DEF_STRING_DESC_LANG 0x00 +#define DEF_STRING_DESC_MANU 0x01 +#define DEF_STRING_DESC_PROD 0x02 +#define DEF_STRING_DESC_SERN 0x03 + +/* USB hub class request code */ +#ifndef HUB_GET_DESCRIPTOR +#define HUB_GET_STATUS 0x00 +#define HUB_CLEAR_FEATURE 0x01 +#define HUB_GET_STATE 0x02 +#define HUB_SET_FEATURE 0x03 +#define HUB_GET_DESCRIPTOR 0x06 +#define HUB_SET_DESCRIPTOR 0x07 +#endif + +/* USB HID class request code */ +#ifndef HID_GET_REPORT +#define HID_GET_REPORT 0x01 +#define HID_GET_IDLE 0x02 +#define HID_GET_PROTOCOL 0x03 +#define HID_SET_REPORT 0x09 +#define HID_SET_IDLE 0x0A +#define HID_SET_PROTOCOL 0x0B +#endif + +/* Bit Define for USB Request Type */ +#ifndef USB_REQ_TYP_MASK +#define USB_REQ_TYP_IN 0x80 +#define USB_REQ_TYP_OUT 0x00 +#define USB_REQ_TYP_READ 0x80 +#define USB_REQ_TYP_WRITE 0x00 +#define USB_REQ_TYP_MASK 0x60 +#define USB_REQ_TYP_STANDARD 0x00 +#define USB_REQ_TYP_CLASS 0x20 +#define USB_REQ_TYP_VENDOR 0x40 +#define USB_REQ_TYP_RESERVED 0x60 +#define USB_REQ_RECIP_MASK 0x1F +#define USB_REQ_RECIP_DEVICE 0x00 +#define USB_REQ_RECIP_INTERF 0x01 +#define USB_REQ_RECIP_ENDP 0x02 +#define USB_REQ_RECIP_OTHER 0x03 +#define USB_REQ_FEAT_REMOTE_WAKEUP 0x01 +#define USB_REQ_FEAT_ENDP_HALT 0x00 +#endif + +/* USB Descriptor Type */ +#ifndef USB_DESCR_TYP_DEVICE +#define USB_DESCR_TYP_DEVICE 0x01 +#define USB_DESCR_TYP_CONFIG 0x02 +#define USB_DESCR_TYP_STRING 0x03 +#define USB_DESCR_TYP_INTERF 0x04 +#define USB_DESCR_TYP_ENDP 0x05 +#define USB_DESCR_TYP_QUALIF 0x06 +#define USB_DESCR_TYP_SPEED 0x07 +#define USB_DESCR_TYP_OTG 0x09 +#define USB_DESCR_TYP_BOS 0X0F +#define USB_DESCR_TYP_HID 0x21 +#define USB_DESCR_TYP_REPORT 0x22 +#define USB_DESCR_TYP_PHYSIC 0x23 +#define USB_DESCR_TYP_CS_INTF 0x24 +#define USB_DESCR_TYP_CS_ENDP 0x25 +#define USB_DESCR_TYP_HUB 0x29 +#endif + +/* USB Device Class */ +#ifndef USB_DEV_CLASS_HUB +#define USB_DEV_CLASS_RESERVED 0x00 +#define USB_DEV_CLASS_AUDIO 0x01 +#define USB_DEV_CLASS_COMMUNIC 0x02 +#define USB_DEV_CLASS_HID 0x03 +#define USB_DEV_CLASS_MONITOR 0x04 +#define USB_DEV_CLASS_PHYSIC_IF 0x05 +#define USB_DEV_CLASS_POWER 0x06 +#define USB_DEV_CLASS_PRINTER 0x07 +#define USB_DEV_CLASS_STORAGE 0x08 +#define USB_DEV_CLASS_HUB 0x09 +#define USB_DEV_CLASS_VEN_SPEC 0xFF +#endif + +/* USB Hub Class Request */ +#ifndef HUB_GET_HUB_DESCRIPTOR +#define HUB_CLEAR_HUB_FEATURE 0x20 +#define HUB_CLEAR_PORT_FEATURE 0x23 +#define HUB_GET_BUS_STATE 0xA3 +#define HUB_GET_HUB_DESCRIPTOR 0xA0 +#define HUB_GET_HUB_STATUS 0xA0 +#define HUB_GET_PORT_STATUS 0xA3 +#define HUB_SET_HUB_DESCRIPTOR 0x20 +#define HUB_SET_HUB_FEATURE 0x20 +#define HUB_SET_PORT_FEATURE 0x23 +#endif + +/* Hub Class Feature Selectors */ +#ifndef HUB_PORT_RESET +#define HUB_C_HUB_LOCAL_POWER 0 +#define HUB_C_HUB_OVER_CURRENT 1 +#define HUB_PORT_CONNECTION 0 +#define HUB_PORT_ENABLE 1 +#define HUB_PORT_SUSPEND 2 +#define HUB_PORT_OVER_CURRENT 3 +#define HUB_PORT_RESET 4 +#define HUB_PORT_POWER 8 +#define HUB_PORT_LOW_SPEED 9 +#define HUB_C_PORT_CONNECTION 16 +#define HUB_C_PORT_ENABLE 17 +#define HUB_C_PORT_SUSPEND 18 +#define HUB_C_PORT_OVER_CURRENT 19 +#define HUB_C_PORT_RESET 20 +#endif + +/* USB HID Class Request Code */ +#ifndef HID_GET_REPORT +#define HID_GET_REPORT 0x01 +#define HID_GET_IDLE 0x02 +#define HID_GET_PROTOCOL 0x03 +#define HID_SET_REPORT 0x09 +#define HID_SET_IDLE 0x0A +#define HID_SET_PROTOCOL 0x0B +#endif + +/* USB UDisk */ +#ifndef USB_BO_CBW_SIZE +#define USB_BO_CBW_SIZE 0x1F +#define USB_BO_CSW_SIZE 0x0D +#endif +#ifndef USB_BO_CBW_SIG0 +#define USB_BO_CBW_SIG0 0x55 +#define USB_BO_CBW_SIG1 0x53 +#define USB_BO_CBW_SIG2 0x42 +#define USB_BO_CBW_SIG3 0x43 +#define USB_BO_CSW_SIG0 0x55 +#define USB_BO_CSW_SIG1 0x53 +#define USB_BO_CSW_SIG2 0x42 +#define USB_BO_CSW_SIG3 0x53 +#endif + +/* USB CDC Class request code */ +#ifndef CDC_GET_LINE_CODING +#define CDC_GET_LINE_CODING 0X21 /* This request allows the host to find out the currently configured line coding */ +#define CDC_SET_LINE_CODING 0x20 /* Configures DTE rate, stop-bits, parity, and number-of-character */ +#define CDC_SET_LINE_CTLSTE 0X22 /* This request generates RS-232/V.24 style control signals */ +#define CDC_SEND_BREAK 0X23 /* Sends special carrier modulation used to specify RS-232 style break */ +#endif +/*******************************************************************************/ +/* USBFS Related Register Macro Definition */ + +/* R8_USB_CTRL */ +#define USBFS_UC_HOST_MODE 0x80 +#define USBFS_UC_LOW_SPEED 0x40 +#define USBFS_UC_DEV_PU_EN 0x20 +#define USBFS_UC_SYS_CTRL_MASK 0x30 +#define USBFS_UC_SYS_CTRL0 0x00 +#define USBFS_UC_SYS_CTRL1 0x10 +#define USBFS_UC_SYS_CTRL2 0x20 +#define USBFS_UC_SYS_CTRL3 0x30 +#define USBFS_UC_INT_BUSY 0x08 +#define USBFS_UC_RESET_SIE 0x04 +#define USBFS_UC_CLR_ALL 0x02 +#define USBFS_UC_DMA_EN 0x01 + +/* R8_USB_INT_EN */ +#define USBFS_UIE_DEV_SOF 0x80 +#define USBFS_UIE_DEV_NAK 0x40 +#define USBFS_UIE_FIFO_OV 0x10 +#define USBFS_UIE_HST_SOF 0x08 +#define USBFS_UIE_SUSPEND 0x04 +#define USBFS_UIE_TRANSFER 0x02 +#define USBFS_UIE_DETECT 0x01 +#define USBFS_UIE_BUS_RST 0x01 + +/* R8_USB_DEV_AD */ +#define USBFS_UDA_GP_BIT 0x80 +#define USBFS_USB_ADDR_MASK 0x7F + +/* R8_USB_MIS_ST */ +#define USBFS_UMS_SOF_PRES 0x80 +#define USBFS_UMS_SOF_ACT 0x40 +#define USBFS_UMS_SIE_FREE 0x20 +#define USBFS_UMS_R_FIFO_RDY 0x10 +#define USBFS_UMS_BUS_RESET 0x08 +#define USBFS_UMS_SUSPEND 0x04 +#define USBFS_UMS_DM_LEVEL 0x02 +#define USBFS_UMS_DEV_ATTACH 0x01 + +/* R8_USB_INT_FG */ +#define USBFS_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received for USB device mode +#define USBFS_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBFS_U_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define USBFS_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear +#define USBFS_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear +#define USBFS_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear +#define USBFS_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear +#define USBFS_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear +#define USBFS_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear + +/* R8_USB_INT_ST */ +#define USBFS_SETUP_ACT 0x80 // RO, indicate current USB transfer SETUP is complete +#define USBFS_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBFS_UIS_TOKEN_MASK 0x30 // RO, bit mask of current token PID code received for USB device mode +#define USBFS_UIS_TOKEN_OUT 0x00 +#define USBFS_UIS_TOKEN_SOF 0x10 +#define USBFS_UIS_TOKEN_IN 0x20 +#define USBFS_UIS_TOKEN_SETUP 0x30 +// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode +// 00: OUT token PID received +// 01: SOF token PID received +// 10: IN token PID received +// 11: SETUP token PID received +#define USBFS_UIS_ENDP_MASK 0x0F // RO, bit mask of current transfer endpoint number for USB device mode +#define USBFS_UIS_H_RES_MASK 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received + +/* R8_UDEV_CTRL */ +#define USBFS_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBFS_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBFS_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBFS_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed +#define USBFS_UD_GP_BIT 0x02 // general purpose bit +#define USBFS_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable + +/* R8_UEP4_1_MOD */ +#define USBFS_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT) +#define USBFS_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN) +#define USBFS_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1 +// bUEPn_RX_EN & bUEPn_TX_EN & bUEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA +// 0 0 x: disable endpoint and disable buffer +// 1 0 0: 64 bytes buffer for receiving (OUT endpoint) +// 1 0 1: dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes +// 0 1 0: 64 bytes buffer for transmittal (IN endpoint) +// 0 1 1: dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes +// 1 1 0: 64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes +// 1 1 1: dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes +#define USBFS_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT) +#define USBFS_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN) +// bUEP4_RX_EN & bUEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA +// 0 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) +// 1 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes +// 0 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes +// 1 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) +// + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes +#define USBFS_UEP4_BUF_MOD 0x01 + +/* R8_UEP2_3_MOD */ +#define USBFS_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT) +#define USBFS_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN) +#define USBFS_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3 +#define USBFS_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT) +#define USBFS_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN) +#define USBFS_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2 + +/* R8_UEP567_MOD */ + +#define USBFS_UEP5_RX_EN 0x02 // enable USB endpoint 5 receiving (OUT) +#define USBFS_UEP5_TX_EN 0x01 // enable USB endpoint 5 transmittal (IN) +#define USBFS_UEP6_RX_EN 0x08 // enable USB endpoint 6 receiving (OUT) +#define USBFS_UEP6_TX_EN 0x04 // enable USB endpoint 6 transmittal (IN) +#define USBFS_UEP7_RX_EN 0x20 // enable USB endpoint 7 receiving (OUT) +#define USBFS_UEP7_TX_EN 0x10 // enable USB endpoint 7 transmittal (IN) + +/* R8_UEPn_TX_CTRL */ +#define USBFS_UEP_T_AUTO_TOG (1<<4) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBFS_UEP_T_TOG (1<<6) // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 +#define USBFS_UEP_T_RES_MASK (3<<0) // bit mask of handshake response type for USB endpoint X transmittal (IN) +#define USBFS_UEP_T_RES_ACK (0<<1) +#define USBFS_UEP_T_RES_NONE (1<<0) +#define USBFS_UEP_T_RES_NAK (1<<1) +#define USBFS_UEP_T_RES_STALL (3<<0) +// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN) +// 00: DATA0 or DATA1 then expecting ACK (ready) +// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) +// host aux setup + +/* R8_UEPn_RX_CTRL, n=0-7 */ +#define USBFS_UEP_R_AUTO_TOG (1<<4) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBFS_UEP_R_TOG (1<<7) // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 +#define USBFS_UEP_R_RES_MASK (3<<2) // bit mask of handshake response type for USB endpoint X receiving (OUT) +#define USBFS_UEP_R_RES_ACK (0<<3) +#define USBFS_UEP_R_RES_NONE (1<<2) +#define USBFS_UEP_R_RES_NAK (1<<3) +#define USBFS_UEP_R_RES_STALL (3<<2) +// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT) +// 00: ACK (ready) +// 01: no response, time out to host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) + +/* R8_UHOST_CTRL */ +#define USBFS_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBFS_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBFS_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBFS_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed +#define USBFS_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset +#define USBFS_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached + +/* R32_UH_EP_MOD */ +#define USBFS_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal +#define USBFS_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint +// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for transmittal (OUT endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes +#define USBFS_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving +#define USBFS_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint +// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for receiving (IN endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes + +/* R8_UH_SETUP */ +#define USBFS_UH_PRE_PID_EN 0x80 // USB host PRE PID enable for low speed device via hub +#define USBFS_UH_SOF_EN 0x40 // USB host automatic SOF enable + +/* R8_UH_EP_PID */ +#define USBFS_UH_TOKEN_MASK 0xF0 // bit mask of token PID for USB host transfer +#define USBFS_UH_ENDP_MASK 0x0F // bit mask of endpoint number for USB host transfer + + /* R8_UH_RX_CTRL */ + #define USBFS_UH_R_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle + #define USBFS_UH_R_TOG (1<<7) // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 + #define USBFS_UH_R_RES 0x01 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions + + /* R8_UH_TX_CTRL */ + #define USBFS_UH_T_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle + #define USBFS_UH_T_TOG (1<<6) // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1 + #define USBFS_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions + + +/*******************************************************************************/ +/* Struct Definition */ + +/* USB Setup Request */ +typedef struct __attribute__((packed)) _USB_SETUP_REQ +{ + uint8_t bRequestType; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} USB_SETUP_REQ, *PUSB_SETUP_REQ; + +/* USB Device Descriptor */ +typedef struct __attribute__((packed)) _USB_DEVICE_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + uint16_t idVendor; + uint16_t idProduct; + uint16_t bcdDevice; + uint8_t iManufacturer; + uint8_t iProduct; + uint8_t iSerialNumber; + uint8_t bNumConfigurations; +} USB_DEV_DESCR, *PUSB_DEV_DESCR; + +/* USB Configuration Descriptor */ +typedef struct __attribute__((packed)) _USB_CONFIG_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wTotalLength; + uint8_t bNumInterfaces; + uint8_t bConfigurationValue; + uint8_t iConfiguration; + uint8_t bmAttributes; + uint8_t MaxPower; +} USB_CFG_DESCR, *PUSB_CFG_DESCR; + +/* USB Interface Descriptor */ +typedef struct __attribute__((packed)) _USB_INTERF_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; + uint8_t bNumEndpoints; + uint8_t bInterfaceClass; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; + uint8_t iInterface; +} USB_ITF_DESCR, *PUSB_ITF_DESCR; + +/* USB Endpoint Descriptor */ +typedef struct __attribute__((packed)) _USB_ENDPOINT_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint8_t wMaxPacketSizeL; + uint8_t wMaxPacketSizeH; + uint8_t bInterval; +} USB_ENDP_DESCR, *PUSB_ENDP_DESCR; + +/* USB Configuration Descriptor Set */ +typedef struct __attribute__((packed)) _USB_CONFIG_DESCR_LONG +{ + USB_CFG_DESCR cfg_descr; + USB_ITF_DESCR itf_descr; + USB_ENDP_DESCR endp_descr[ 1 ]; +} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG; + +/* USB HUB Descriptor */ +typedef struct __attribute__((packed)) _USB_HUB_DESCR +{ + uint8_t bDescLength; + uint8_t bDescriptorType; + uint8_t bNbrPorts; + uint8_t wHubCharacteristicsL; + uint8_t wHubCharacteristicsH; + uint8_t bPwrOn2PwrGood; + uint8_t bHubContrCurrent; + uint8_t DeviceRemovable; + uint8_t PortPwrCtrlMask; +} USB_HUB_DESCR, *PUSB_HUB_DESCR; + +/* USB HID Descriptor */ +typedef struct __attribute__((packed)) _USB_HID_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdHID; + uint8_t bCountryCode; + uint8_t bNumDescriptors; + uint8_t bDescriptorTypeX; + uint8_t wDescriptorLengthL; + uint8_t wDescriptorLengthH; +} USB_HID_DESCR, *PUSB_HID_DESCR; + +/* USB UDisk */ +typedef struct __attribute__((packed)) _UDISK_BOC_CBW +{ + uint32_t mCBW_Sig; + uint32_t mCBW_Tag; + uint32_t mCBW_DataLen; + uint8_t mCBW_Flag; + uint8_t mCBW_LUN; + uint8_t mCBW_CB_Len; + uint8_t mCBW_CB_Buf[ 16 ]; +} UDISK_BOC_CBW, *PXUDISK_BOC_CBW; + +/* USB UDisk */ +typedef struct __attribute__((packed)) _UDISK_BOC_CSW +{ + uint32_t mCBW_Sig; + uint32_t mCBW_Tag; + uint32_t mCSW_Residue; + uint8_t mCSW_Status; +} UDISK_BOC_CSW, *PXUDISK_BOC_CSW; + + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32X035_USB_H */ diff --git a/Code/DAP_X033/Peripheral/inc/ch32x035_usbpd.h b/Code/DAP_X033/Peripheral/inc/ch32x035_usbpd.h new file mode 100644 index 0000000..7ca1008 --- /dev/null +++ b/Code/DAP_X033/Peripheral/inc/ch32x035_usbpd.h @@ -0,0 +1,412 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_usbpd.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for the USBPD + * firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_USBPD_H +#define __CH32X035_USBPD_H + + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32x035.h" + +#ifndef VOID +#define VOID void +#endif +#ifndef CONST +#define CONST const +#endif +#ifndef BOOL +typedef unsigned char BOOL; +#endif +#ifndef BOOLEAN +typedef unsigned char BOOLEAN; +#endif +#ifndef CHAR +typedef char CHAR; +#endif +#ifndef INT8 +typedef char INT8; +#endif +#ifndef INT16 +typedef short INT16; +#endif +#ifndef INT32 +typedef long INT32; +#endif +#ifndef UINT8 +typedef unsigned char UINT8; +#endif +#ifndef UINT16 +typedef unsigned short UINT16; +#endif +#ifndef UINT32 +typedef unsigned long UINT32; +#endif +#ifndef UINT8V +typedef unsigned char volatile UINT8V; +#endif +#ifndef UINT16V +typedef unsigned short volatile UINT16V; +#endif +#ifndef UINT32V +typedef unsigned long volatile UINT32V; +#endif + +#ifndef PVOID +typedef void *PVOID; +#endif +#ifndef PCHAR +typedef char *PCHAR; +#endif +#ifndef PCHAR +typedef const char *PCCHAR; +#endif +#ifndef PINT8 +typedef char *PINT8; +#endif +#ifndef PINT16 +typedef short *PINT16; +#endif +#ifndef PINT32 +typedef long *PINT32; +#endif +#ifndef PUINT8 +typedef unsigned char *PUINT8; +#endif +#ifndef PUINT16 +typedef unsigned short *PUINT16; +#endif +#ifndef PUINT32 +typedef unsigned long *PUINT32; +#endif +#ifndef PUINT8V +typedef volatile unsigned char *PUINT8V; +#endif +#ifndef PUINT16V +typedef volatile unsigned short *PUINT16V; +#endif +#ifndef PUINT32V +typedef volatile unsigned long *PUINT32V; +#endif + + /******************************************************************************/ +/* Related macro definitions */ + +/* Define the return value of the function */ +#ifndef SUCCESS +#define SUCCESS 0 +#endif +#ifndef FAIL +#define FAIL 0xFF +#endif + +/* Register Bit Definition */ +/* USBPD->CONFIG */ +#define PD_FILT_ED (1<<0) /* PD pin input filter enable */ +#define PD_ALL_CLR (1<<1) /* Clear all interrupt flags */ +#define CC_SEL (1<<2) /* Select PD communication port */ +#define PD_DMA_EN (1<<3) /* Enable DMA for USBPD */ +#define PD_RST_EN (1<<4) /* PD mode reset command enable */ +#define WAKE_POLAR (1<<5) /* PD port wake-up level */ +#define IE_PD_IO (1<<10) /* PD IO interrupt enable */ +#define IE_RX_BIT (1<<11) /* Receive bit interrupt enable */ +#define IE_RX_BYTE (1<<12) /* Receive byte interrupt enable */ +#define IE_RX_ACT (1<<13) /* Receive completion interrupt enable */ +#define IE_RX_RESET (1<<14) /* Reset interrupt enable */ +#define IE_TX_END (1<<15) /* Transfer completion interrupt enable */ + +/* USBPD->CONTROL */ +#define PD_TX_EN (1<<0) /* USBPD transceiver mode and transmit enable */ +#define BMC_START (1<<1) /* BMC send start signal */ +#define RX_STATE_0 (1<<2) /* PD received state bit 0 */ +#define RX_STATE_1 (1<<3) /* PD received state bit 1 */ +#define RX_STATE_2 (1<<4) /* PD received state bit 2 */ +#define DATA_FLAG (1<<5) /* Cache data valid flag bit */ +#define TX_BIT_BACK (1<<6) /* Indicates the current bit status of the BMC when sending the code */ +#define BMC_BYTE_HI (1<<7) /* Indicates the current half-byte status of the PD data being sent and received */ + +/* USBPD->TX_SEL */ +#define TX_SEL1 (0<<0) +#define TX_SEL1_SYNC1 (0<<0) /* 0-SYNC1 */ +#define TX_SEL1_RST1 (1<<0) /* 1-RST1 */ +#define TX_SEL2_Mask (3<<2) +#define TX_SEL2_SYNC1 (0<<2) /* 00-SYNC1 */ +#define TX_SEL2_SYNC3 (1<<2) /* 01-SYNC3 */ +#define TX_SEL2_RST1 (2<<2) /* 1x-RST1 */ +#define TX_SEL3_Mask (3<<4) +#define TX_SEL3_SYNC1 (0<<4) /* 00-SYNC1 */ +#define TX_SEL3_SYNC3 (1<<4) /* 01-SYNC3 */ +#define TX_SEL3_RST1 (2<<4) /* 1x-RST1 */ +#define TX_SEL4_Mask (3<<6) +#define TX_SEL4_SYNC2 (0<<6) /* 00-SYNC2 */ +#define TX_SEL4_SYNC3 (1<<6) /* 01-SYNC3 */ +#define TX_SEL4_RST2 (2<<6) /* 1x-RST2 */ + +/* USBPD->STATUS */ +#define BMC_AUX_Mask (3<<0) /* Clear BMC auxiliary information */ +#define BMC_AUX_INVALID (0<<0) /* 00-Invalid */ +#define BMC_AUX_SOP0 (1<<0) /* 01-SOP0 */ +#define BMC_AUX_SOP1_HRST (2<<0) /* 10-SOP1 hard reset */ +#define BMC_AUX_SOP2_CRST (3<<0) /* 11-SOP2 cable reset */ +#define BUF_ERR (1<<2) /* BUFFER or DMA error interrupt flag */ +#define IF_RX_BIT (1<<3) /* Receive bit or 5bit interrupt flag */ +#define IF_RX_BYTE (1<<4) /* Receive byte or SOP interrupt flag */ +#define IF_RX_ACT (1<<5) /* Receive completion interrupt flag */ +#define IF_RX_RESET (1<<6) /* Receive reset interrupt flag */ +#define IF_TX_END (1<<7) /* Transfer completion interrupt flag */ + +/* USBPD->PORT_CC1 */ +/* USBPD->PORT_CC2 */ +#define PA_CC_AI (1<<0) /* CC port comparator analogue input */ +#define CC_PD (1<<1) /* CC port pull-down resistor enable */ +#define CC_PU_Mask (3<<2) /* Clear CC port pull-up current */ +#define CC_NO_PU (0<<2) /* 00-Prohibit pull-up current */ +#define CC_PU_330 (1<<2) /* 01-330uA */ +#define CC_PU_180 (2<<2) /* 10-180uA */ +#define CC_PU_80 (3<<2) /* 11-80uA */ +#define CC_LVE (1<<4) /* CC port output low voltage enable */ +#define CC_CMP_Mask (7<<5) /* Clear CC_CMP*/ +#define CC_NO_CMP (0<<5) /* 000-closed */ +#define CC_CMP_22 (2<<5) /* 010-0.22V */ +#define CC_CMP_45 (3<<5) /* 011-0.45V */ +#define CC_CMP_55 (4<<5) /* 100-0.55V */ +#define CC_CMP_66 (5<<5) /* 101-0.66V */ +#define CC_CMP_95 (6<<5) /* 110-0.95V */ +#define CC_CMP_123 (7<<5) /* 111-1.23V */ +#define USBPD_IN_HVT (1<<9) +/********************************************************* + * PD pin PC14/PC15 high threshold input mode: + * 1-High threshold input (2.2V typical), to reduce the I/O power consumption during PD communication + * 0-Normal GPIO threshold input + * *******************************************************/ +#define USBPD_PHY_V33 (1<<8) +/********************************************************** +* PD transceiver PHY pull-up limit configuration bits: +* 1-Direct use of VDD for GPIO applications or PD applications with VDD voltage of 3.3V +* 0-LDO buck enabled, limited to approx 3.3V, for PD applications with VDD more than 4V +* ********************************************************/ + +/* Control Message Types */ +#define DEF_TYPE_RESERVED 0x00 +#define DEF_TYPE_GOODCRC 0x01 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_GOTOMIN 0x02 /* Send By: Source */ +#define DEF_TYPE_ACCEPT 0x03 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_REJECT 0x04 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_PING 0x05 /* Send By: Source */ +#define DEF_TYPE_PS_RDY 0x06 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_SRC_CAP 0x07 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_SNK_CAP 0x08 /* Send By: Source,DRP */ +#define DEF_TYPE_DR_SWAP 0x09 /* Send By: Source,Sink */ +#define DEF_TYPE_PR_SWAP 0x0A /* Send By: Source,Sink */ +#define DEF_TYPE_VCONN_SWAP 0x0B /* Send By: Source,Sink */ +#define DEF_TYPE_WAIT 0x0C /* Send By: Source,Sink */ +#define DEF_TYPE_SOFT_RESET 0x0D /* Send By: Source,Sink */ +#define DEF_TYPE_DATA_RESET 0x0E /* Send By: Source,Sink */ +#define DEF_TYPE_DATA_RESET_CMP 0x0F /* Send By: Source,Sink */ +#define DEF_TYPE_NOT_SUPPORT 0x10 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_GET_SRC_CAP_EX 0x11 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_STATUS 0x12 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_STATUS_R 0X02 /* ext=1 */ +#define DEF_TYPE_FR_SWAP 0x13 /* Send By: Sink */ +#define DEF_TYPE_GET_PPS_STATUS 0x14 /* Send By: Sink */ +#define DEF_TYPE_GET_CTY_CODES 0x15 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_SNK_CAP_EX 0x16 /* Send By: Source,DRP */ +#define DEF_TYPE_GET_SRC_INFO 0x17 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_REVISION 0x18 /* Send By: Source,Sink */ + +/* Data Message Types */ +#define DEF_TYPE_SRC_CAP 0x01 /* Send By: Source,Dual-Role Power */ +#define DEF_TYPE_REQUEST 0x02 /* Send By: Sink */ +#define DEF_TYPE_BIST 0x03 /* Send By: Tester,Source,Sink */ +#define DEF_TYPE_SNK_CAP 0x04 /* Send By: Sink,Dual-Role Power */ +#define DEF_TYPE_BAT_STATUS 0x05 /* Send By: Source,Sink */ +#define DEF_TYPE_ALERT 0x06 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_CTY_INFO 0x07 /* Send By: Source,Sink */ +#define DEF_TYPE_ENTER_USB 0x08 /* Send By: DFP */ +#define DEF_TYPE_EPR_REQUEST 0x09 /* Send By: Sink */ +#define DEF_TYPE_EPR_MODE 0x0A /* Send By: Source,Sink */ +#define DEF_TYPE_SRC_INFO 0x0B /* Send By: Source */ +#define DEF_TYPE_REVISION 0x0C /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_VENDOR_DEFINED 0x0F /* Send By: Source,Sink,Cable Plug */ + +/* Vendor Define Message Command */ +#define DEF_VDM_DISC_IDENT 0x01 +#define DEF_VDM_DISC_SVID 0x02 +#define DEF_VDM_DISC_MODE 0x03 +#define DEF_VDM_ENTER_MODE 0x04 +#define DEF_VDM_EXIT_MODE 0x05 +#define DEF_VDM_ATTENTION 0x06 +#define DEF_VDM_DP_S_UPDATE 0x10 +#define DEF_VDM_DP_CONFIG 0x11 + +/* PD Revision */ +#define DEF_PD_REVISION_10 0x00 +#define DEF_PD_REVISION_20 0x01 +#define DEF_PD_REVISION_30 0x02 + + +/* PD PHY Channel */ +#define DEF_PD_CC1 0x00 +#define DEF_PD_CC2 0x01 + +#define PIN_CC1 GPIO_Pin_14 +#define PIN_CC2 GPIO_Pin_15 + +/* PD Tx Status */ +#define DEF_PD_TX_OK 0x00 +#define DEF_PD_TX_FAIL 0x01 + +/* PDO INDEX */ +#define PDO_INDEX_1 1 +#define PDO_INDEX_2 2 +#define PDO_INDEX_3 3 +#define PDO_INDEX_4 4 +#define PDO_INDEX_5 5 + +/******************************************************************************/ + +#define UPD_TMR_TX_48M (80-1) /* timer value for USB PD BMC transmittal @Fsys=48MHz */ +#define UPD_TMR_RX_48M (120-1) /* timer value for USB PD BMC receiving @Fsys=48MHz */ +#define UPD_TMR_TX_24M (40-1) /* timer value for USB PD BMC transmittal @Fsys=24MHz */ +#define UPD_TMR_RX_24M (60-1) /* timer value for USB PD BMC receiving @Fsys=24MHz */ +#define UPD_TMR_TX_12M (20-1) /* timer value for USB PD BMC transmittal @Fsys=12MHz */ +#define UPD_TMR_RX_12M (30-1) /* timer value for USB PD BMC receiving @Fsys=12MHz */ + +#define MASK_PD_STAT 0x03 /* Bit mask for current PD status */ +#define PD_RX_SOP0 0x01 /* SOP0 received */ +#define PD_RX_SOP1_HRST 0x02 /* SOP1 or Hard Reset received */ +#define PD_RX_SOP2_CRST 0x03 /* SOP2 or Cable Reset received */ + +#define UPD_SOP0 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC1 | TX_SEL4_SYNC2 ) /* SOP1 */ +#define UPD_SOP1 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC3 | TX_SEL4_SYNC3 ) /* SOP2 */ +#define UPD_SOP2 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC3 | TX_SEL3_SYNC1 | TX_SEL4_SYNC3 ) /* SOP3 */ +#define UPD_HARD_RESET ( TX_SEL1_RST1 | TX_SEL2_RST1 | TX_SEL3_RST1 | TX_SEL4_RST2 ) /* Hard Reset*/ +#define UPD_CABLE_RESET ( TX_SEL1_RST1 | TX_SEL2_SYNC1 | TX_SEL3_RST1 | TX_SEL4_SYNC3 ) /* Cable Reset*/ + + +#define bCC_CMP_22 0X01 +#define bCC_CMP_45 0X02 +#define bCC_CMP_55 0X04 +#define bCC_CMP_66 0X08 +#define bCC_CMP_95 0X10 +#define bCC_CMP_123 0X20 +#define bCC_CMP_220 0X40 + +/******************************************************************************/ +/* PD State Machine */ +typedef enum +{ + STA_IDLE = 0, /* 0: No task status */ + STA_DISCONNECT, /* 1: Disconnection */ + STA_SRC_CONNECT, /* 2: SRC connect */ + STA_RX_SRC_CAP_WAIT, /* 3: Waiting to receive SRC_CAP */ + STA_RX_SRC_CAP, /* 4: SRC_CAP received */ + STA_TX_REQ, /* 5: Send REQUEST */ + STA_RX_ACCEPT_WAIT, /* 6: Waiting to receive ACCEPT */ + STA_RX_ACCEPT, /* 7: ACCEPT received */ + STA_RX_REJECT, /* 8: REJECT received */ + STA_RX_PS_RDY_WAIT, /* 9: Waiting to receive PS_RDY */ + STA_RX_PS_RDY, /* 10: PS_RDY received */ + STA_SINK_CONNECT, /* 11: SNK access */ + STA_TX_SRC_CAP, /* 12: Send SRC_CAP */ + STA_RX_REQ_WAIT, /* 13: Waiting to receive REQUEST */ + STA_RX_REQ, /* 14: REQUEST received */ + STA_TX_ACCEPT, /* 15: Send ACCEPT */ + STA_TX_REJECT, /* 16: Send REJECT */ + STA_ADJ_VOL, /* 17: Adjustment of output voltage and current */ + STA_TX_PS_RDY, /* 18: Send PS_RDY */ + STA_TX_DR_SWAP, /* 19: Send DR_SWAP */ + STA_RX_DR_SWAP_ACCEPT, /* 20: Waiting to receive the answer ACCEPT from DR_SWAP */ + STA_TX_PR_SWAP, /* 21: Send PR_SWAP */ + STA_RX_PR_SWAP_ACCEPT, /* 22: Waiting to receive the answer ACCEPT from PR_SWAP */ + STA_RX_PR_SWAP_PS_RDY, /* 23: Waiting to receive the answer PS_RDY from PR_SWAP */ + STA_TX_PR_SWAP_PS_RDY, /* 24: Send answer PS_RDY for PR_SWAP */ + STA_PR_SWAP_RECON_WAIT, /* 25: Wait for PR_SWAP before reconnecting */ + STA_SRC_RECON_WAIT, /* 26: Waiting for SRC to reconnect */ + STA_SINK_RECON_WAIT, /* 27: Waiting for SNK to reconnect */ + STA_RX_APD_PS_RDY_WAIT, /* 28: Waiting for PS_RDY from the receiving adapter */ + STA_RX_APD_PS_RDY, /* 29: PS_RDY received from the adapter */ + STA_MODE_SWITCH, /* 30: Mode switching */ + STA_TX_SOFTRST, /* 31: Sending a software reset */ + STA_TX_HRST, /* 32: Send hardware reset */ + STA_PHY_RST, /* 33: PHY reset */ + STA_APD_IDLE_WAIT, /* 34: Waiting for the adapter to become idle */ +} CC_STATUS; + +/******************************************************************************/ +/* PD Message Header Struct */ +typedef union +{ + struct _Message_Header + { + UINT8 MsgType: 5; /* Message Type */ + UINT8 PDRole: 1; /* 0-UFP; 1-DFP */ + UINT8 SpecRev: 2; /* 00-Rev1.0; 01-Rev2.0; 10-Rev3.0; */ + UINT8 PRRole: 1; /* 0-Sink; 1-Source */ + UINT8 MsgID: 3; + UINT8 NumDO: 3; + UINT8 Ext: 1; + }Message_Header; + UINT16 Data; +}_Message_Header; + +/******************************************************************************/ +/* Bit definition */ +typedef union +{ + struct _BITS_ + { + UINT8 Msg_Recvd: 1; /* Notify the main program of the receipt of a PD packet */ + UINT8 Connected: 1; /* PD Physical Layer Connected Flag */ + UINT8 Stop_Det_Chk: 1; /* 0-Enable detection; 1-Disable disconnection detection */ + UINT8 PD_Role: 1; /* 0-UFP; 1-DFP */ + UINT8 PR_Role: 1; /* 0-Sink; 1-Source */ + UINT8 Auto_Ack_PRRole: 1; /* Role used by auto-responder 0:SINK; 1:SOURCE */ + UINT8 PD_Version: 1; /* PD version 0-PD2.0; 1-PD3.0 */ + UINT8 VDM_Version: 1; /* VDM Version 0-1.0 1-2.0 */ + UINT8 HPD_Connected: 1; /* HPD Physical Layer Connected Flag */ + UINT8 HPD_Det_Chk: 1; /* 0-turn off HPD connection detection; 1-turn on HPD connection detection */ + UINT8 CC_Sel_En: 1; /* 0-CC channel selection toggle enable; 1-CC channel selection toggle disable */ + UINT8 CC_Sel_State: 1; /* 0-CC channel selection switches to 0; 1-CC channel selection switches to 1 */ + UINT8 PD_Comm_Succ: 1; /* 0-PD communication unsuccessful; 1-PD communication successful; */ + UINT8 Recv: 3; + }Bit; + UINT16 Bit_Flag; +}_BIT_FLAG; + +/* PD control-related structures */ +typedef struct _PD_CONTROL +{ + CC_STATUS PD_State; /* PD communication status machine */ + CC_STATUS PD_State_Last; /* PD communication status machine (last value) */ + UINT8 Msg_ID; /* ID of the message sent */ + UINT8 Det_Timer; /* PD connection status detection timing */ + UINT8 Det_Cnt; /* Number of PD connection status detections */ + UINT8 Det_Sel_Cnt; /* Number of SEL toggles for PD connection status detection */ + UINT8 HPD_Det_Timer; /* HPD connection detection timing */ + UINT8 HPD_Det_Cnt; /* HPD pin connection status detection count */ + UINT16 PD_Comm_Timer; /* PD shared timing variables */ + UINT8 ReqPDO_Idx; /* Index of the requested PDO, valid values 1-7 */ + UINT16 PD_BusIdle_Timer; /* Bus Idle Time Timer */ + UINT8 Mode_Try_Cnt; /* Number of retries for current mode, highest bit marks mode */ + UINT8 Err_Op_Cnt; /* Exception operation count */ + UINT8 Adapter_Idle_Cnt; /* Adapter communication idle timing */ + _BIT_FLAG Flag; /* Flag byte bit definition */ +}PD_CONTROL, *pPD_CONTROL; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Code/DAP_X033/Peripheral/inc/ch32x035_wwdg.h b/Code/DAP_X033/Peripheral/inc/ch32x035_wwdg.h new file mode 100644 index 0000000..689b6fd --- /dev/null +++ b/Code/DAP_X033/Peripheral/inc/ch32x035_wwdg.h @@ -0,0 +1,41 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_wwdg.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains all the functions prototypes for the WWDG + * firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_WWDG_H +#define __CH32X035_WWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32x035.h" + +/* WWDG_Prescaler */ +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) + +void WWDG_DeInit(void); +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); +void WWDG_SetWindowValue(uint8_t WindowValue); +void WWDG_EnableIT(void); +void WWDG_SetCounter(uint8_t Counter); +void WWDG_Enable(uint8_t Counter); +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Code/DAP_X033/Peripheral/src/ch32x035_adc.c b/Code/DAP_X033/Peripheral/src/ch32x035_adc.c new file mode 100644 index 0000000..c8455b7 --- /dev/null +++ b/Code/DAP_X033/Peripheral/src/ch32x035_adc.c @@ -0,0 +1,1125 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_adc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file provides all the ADC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_adc.h" +#include "ch32x035_rcc.h" + +/* ADC DISCNUM mask */ +#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CTLR1_DISCEN_Set ((uint32_t)0x00000800) +#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) + +/* ADC JAUTO mask */ +#define CTLR1_JAUTO_Set ((uint32_t)0x00000400) +#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000) +#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) + +/* ADC AWDCH mask */ +#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) + +/* CTLR1 register Mask */ +#define CTLR1_CLEAR_Mask ((uint32_t)0xE0F0FEFF) + +/* ADC ADON mask */ +#define CTLR2_ADON_Set ((uint32_t)0x00000001) +#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CTLR2_DMA_Set ((uint32_t)0x00000100) +#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF) + +/* ADC RSTCAL mask */ +#define CTLR2_RSTCAL_Set ((uint32_t)0x00000008) + +/* ADC CAL mask */ +#define CTLR2_CAL_Set ((uint32_t)0x00000004) + +/* ADC SWSTART mask */ +#define CTLR2_SWSTART_Set ((uint32_t)0x00400000) + +/* ADC EXTTRIG mask */ +#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000) +#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) +#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) + +/* ADC JEXTSEL mask */ +#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000) +#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) + +/* ADC JSWSTART mask */ +#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) +#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CTLR2_TSVREFE_Set ((uint32_t)0x00800000) +#define CTLR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) + +/* CTLR2 register Mask */ +#define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define RSQR3_SQ_Set ((uint32_t)0x0000001F) +#define RSQR2_SQ_Set ((uint32_t)0x0000001F) +#define RSQR1_SQ_Set ((uint32_t)0x0000001F) + +/* RSQR1 register Mask */ +#define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define ISQR_JSQ_Set ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define ISQR_JL_Set ((uint32_t)0x00300000) +#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SAMPTR1_SMP_Set ((uint32_t)0x00000007) +#define SAMPTR2_SMP_Set ((uint32_t)0x00000007) + +/* ADC IDATARx registers offset */ +#define IDATAR_Offset ((uint8_t)0x28) + +/* ADC1 RDATAR register base address */ +#define RDATAR_ADDRESS ((uint32_t)0x4001244C) + +/* ADC CLK */ +#define CTLR3_CLK_Mask ((uint32_t)0xFFFFFE00) + +/********************************************************************* + * @fn ADC_DeInit + * + * @brief Deinitializes the ADCx peripheral registers to their default + * reset values. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return none + */ +void ADC_DeInit(ADC_TypeDef *ADCx) +{ + if(ADCx == ADC1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); + } +} + +/********************************************************************* + * @fn ADC_Init + * + * @brief Initializes the ADCx peripheral according to the specified + * parameters in the ADC_InitStruct. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_InitStruct - pointer to an ADC_InitTypeDef structure that + * contains the configuration information for the specified ADC + * peripheral. + * + * @return none + */ +void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct) +{ + uint32_t tmpreg1 = 0; + uint8_t tmpreg2 = 0; + + tmpreg1 = ADCx->CTLR1; + tmpreg1 &= CTLR1_CLEAR_Mask; + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | (uint32_t)ADC_InitStruct->ADC_OutputBuffer | + (uint32_t)ADC_InitStruct->ADC_Pga | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); + ADCx->CTLR1 = tmpreg1; + + tmpreg1 = ADCx->CTLR2; + tmpreg1 &= CTLR2_CLEAR_Mask; + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | + ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); + ADCx->CTLR2 = tmpreg1; + + tmpreg1 = ADCx->RSQR1; + tmpreg1 &= RSQR1_CLEAR_Mask; + tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); + tmpreg1 |= (uint32_t)tmpreg2 << 20; + ADCx->RSQR1 = tmpreg1; +} + +/********************************************************************* + * @fn ADC_StructInit + * + * @brief Fills each ADC_InitStruct member with its default value. + * + * @param ADC_InitStruct - pointer to an ADC_InitTypeDef structure that + * contains the configuration information for the specified ADC + * peripheral. + * + * @return none + */ +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct) +{ + ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; + ADC_InitStruct->ADC_ScanConvMode = DISABLE; + ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; + ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStruct->ADC_NbrOfChannel = 1; +} + +/********************************************************************* + * @fn ADC_Cmd + * + * @brief Enables or disables the specified ADC peripheral. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_ADON_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_ADON_Reset; + } +} + +/********************************************************************* + * @fn ADC_DMACmd + * + * @brief Enables or disables the specified ADC DMA request. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_DMA_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_DMA_Reset; + } +} + +/********************************************************************* + * @fn ADC_ITConfig + * + * @brief Enables or disables the specified ADC interrupts. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt sources to be enabled or disabled. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState) +{ + uint8_t itmask = 0; + + itmask = (uint8_t)ADC_IT; + + if(NewState != DISABLE) + { + ADCx->CTLR1 |= itmask; + } + else + { + ADCx->CTLR1 &= (~(uint32_t)itmask); + } +} + +/********************************************************************* + * @fn ADC_SoftwareStartConvCmd + * + * @brief Enables or disables the selected ADC software start conversion. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_EXTTRIG_SWSTART_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_EXTTRIG_SWSTART_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetSoftwareStartConvStatus + * + * @brief Gets the selected ADC Software start conversion Status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus - SET or RESET. + */ + +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_SWSTART_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_DiscModeChannelCountConfig + * + * @brief Configures the discontinuous mode for the selected ADC regular + * group channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * Number - specifies the discontinuous mode regular channel + * count value(1-8). + * + * @return None + */ +void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + tmpreg1 = ADCx->CTLR1; + tmpreg1 &= CTLR1_DISCNUM_Reset; + tmpreg2 = Number - 1; + tmpreg1 |= tmpreg2 << 13; + ADCx->CTLR1 = tmpreg1; +} + +/********************************************************************* + * @fn ADC_DiscModeCmd + * + * @brief Enables or disables the discontinuous mode on regular group + * channel for the specified ADC. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_DISCEN_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_DISCEN_Reset; + } +} + +/********************************************************************* + * @fn ADC_RegularChannelConfig + * + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_10 - ADC Channel10 selected. + * ADC_Channel_11 - ADC Channel11 selected. + * ADC_Channel_12 - ADC Channel12 selected. + * ADC_Channel_13 - ADC Channel13 selected. + * ADC_Channel_14 - ADC Channel14 selected. + * ADC_Channel_15 - ADC Channel15 selected. + * Rank - The rank in the regular group sequencer. + * This parameter must be between 1 to 16. + * ADC_SampleTime - The sample time value to be set for the selected channel. + * ADC_SampleTime_4Cycles - Sample time equal to 4 cycles. + * ADC_SampleTime_5Cycles - Sample time equal to 5 cycles. + * ADC_SampleTime_6Cycles - Sample time equal to 6 cycles. + * ADC_SampleTime_7Cycles - Sample time equal to 7 cycles. + * ADC_SampleTime_8Cycles - Sample time equal to 8 cycles. + * ADC_SampleTime_9Cycles - Sample time equal to 9 cycles. + * ADC_SampleTime_10Cycles - Sample time equal to 10 cycles. + * ADC_SampleTime_11Cycles - Sample time equal to 11 cycles. + * + * @return None + */ +void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + + if(ADC_Channel > ADC_Channel_9) + { + tmpreg1 = ADCx->SAMPTR1; + tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR1 = tmpreg1; + } + else + { + tmpreg1 = ADCx->SAMPTR2; + tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR2 = tmpreg1; + } + + if(Rank < 7) + { + tmpreg1 = ADCx->RSQR3; + tmpreg2 = RSQR3_SQ_Set << (5 * (Rank - 1)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); + tmpreg1 |= tmpreg2; + ADCx->RSQR3 = tmpreg1; + } + else if(Rank < 13) + { + tmpreg1 = ADCx->RSQR2; + tmpreg2 = RSQR2_SQ_Set << (5 * (Rank - 7)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); + tmpreg1 |= tmpreg2; + ADCx->RSQR2 = tmpreg1; + } + else + { + tmpreg1 = ADCx->RSQR1; + tmpreg2 = RSQR1_SQ_Set << (5 * (Rank - 13)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); + tmpreg1 |= tmpreg2; + ADCx->RSQR1 = tmpreg1; + } +} + +/********************************************************************* + * @fn ADC_ExternalTrigConvCmd + * + * @brief Enables or disables the ADCx conversion through external trigger. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_EXTTRIG_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_EXTTRIG_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetConversionValue + * + * @brief Returns the last ADCx conversion result data for regular channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return ADCx->RDATAR - The Data conversion value. + */ +uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx) +{ + return (uint16_t)ADCx->RDATAR; +} + +/********************************************************************* + * @fn ADC_GetDualModeConversionValue + * + * @brief Returns the last ADC1 conversion result data in dual mode. + * + * @return RDATAR_ADDRESS - The Data conversion value. + */ +uint32_t ADC_GetDualModeConversionValue(void) +{ + return (*(__IO uint32_t *)RDATAR_ADDRESS); +} + +/********************************************************************* + * @fn ADC_AutoInjectedConvCmd + * + * @brief Enables or disables the selected ADC automatic injected group + * conversion after regular one. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_JAUTO_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_JAUTO_Reset; + } +} + +/********************************************************************* + * @fn ADC_InjectedDiscModeCmd + * + * @brief Enables or disables the discontinuous mode for injected group + * channel for the specified ADC. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_JDISCEN_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_JDISCEN_Reset; + } +} + +/********************************************************************* + * @fn ADC_ExternalTrigInjectedConvConfig + * + * @brief Configures the ADCx external trigger for injected channels conversion. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_ExternalTrigInjecConv - specifies the ADC trigger to start + * injected conversion. + * ADC_ExternalTrigInjecConv_T1_CC3 - Timer1 TRGO event selected. + * ADC_ExternalTrigInjecConv_T1_CC4 - Timer1 capture compare4 selected. + * ADC_ExternalTrigInjecConv_T2_CC3 - Timer2 capture compare3 selected. + * ADC_ExternalTrigInjecConv_T2_CC4 - Timer2 capture compare4 selected. + * ADC_ExternalTrigInjecConv_T2_CC2 - Timer2 capture compare2 selected. + * ADC_ExternalTrigInjecConv_T3_CC2 - Timer3 capture compare2 selected. + * ADC_ExternalTrigInjecConv_ADC_ETRGREG - ADC ETRGREG selected. + * ADC_ExternalTrigInjecConv_None: Injected conversion started + * by software and not by external trigger. + * + * @return None + */ +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR2; + tmpreg &= CTLR2_JEXTSEL_Reset; + tmpreg |= ADC_ExternalTrigInjecConv; + ADCx->CTLR2 = tmpreg; +} + +/********************************************************************* + * @fn ADC_ExternalTrigInjectedConvCmd + * + * @brief Enables or disables the ADCx injected channels conversion through + * external trigger. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_JEXTTRIG_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_JEXTTRIG_Reset; + } +} + +/********************************************************************* + * @fn ADC_SoftwareStartInjectedConvCmd + * + * @brief Enables or disables the selected ADC start of the injected + * channels conversion. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_JEXTTRIG_JSWSTART_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_JEXTTRIG_JSWSTART_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetSoftwareStartInjectedConvCmdStatus + * + * @brief Gets the selected ADC Software start injected conversion Status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_JSWSTART_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_InjectedChannelConfig + * + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_10 - ADC Channel10 selected. + * ADC_Channel_11 - ADC Channel11 selected. + * ADC_Channel_12 - ADC Channel12 selected. + * ADC_Channel_13 - ADC Channel13 selected. + * ADC_Channel_14 - ADC Channel14 selected. + * ADC_Channel_15 - ADC Channel15 selected. + * Rank - The rank in the regular group sequencer. + * This parameter must be between 1 to 4. + * ADC_SampleTime - The sample time value to be set for the selected channel. + * ADC_SampleTime_4Cycles - Sample time equal to 4 cycles. + * ADC_SampleTime_5Cycles - Sample time equal to 5 cycles. + * ADC_SampleTime_6Cycles - Sample time equal to 6 cycles. + * ADC_SampleTime_7Cycles - Sample time equal to 7 cycles. + * ADC_SampleTime_8Cycles - Sample time equal to 8 cycles. + * ADC_SampleTime_9Cycles - Sample time equal to 9 cycles. + * ADC_SampleTime_10Cycles - Sample time equal to 10 cycles. + * ADC_SampleTime_11Cycles - Sample time equal to 11 cycles. + * + * @return None + */ +void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; + + if(ADC_Channel > ADC_Channel_9) + { + tmpreg1 = ADCx->SAMPTR1; + tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR1 = tmpreg1; + } + else + { + tmpreg1 = ADCx->SAMPTR2; + tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR2 = tmpreg1; + } + + tmpreg1 = ADCx->ISQR; + tmpreg3 = (tmpreg1 & ISQR_JL_Set) >> 20; + tmpreg2 = ISQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + tmpreg1 |= tmpreg2; + ADCx->ISQR = tmpreg1; +} + +/********************************************************************* + * @fn ADC_InjectedSequencerLengthConfig + * + * @brief Configures the sequencer length for injected channels. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * Length - The sequencer length. + * This parameter must be a number between 1 to 4. + * + * @return None + */ +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + tmpreg1 = ADCx->ISQR; + tmpreg1 &= ISQR_JL_Reset; + tmpreg2 = Length - 1; + tmpreg1 |= tmpreg2 << 20; + ADCx->ISQR = tmpreg1; +} + +/********************************************************************* + * @fn ADC_SetInjectedOffset + * + * @brief Set the injected channels conversion value offset. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_InjectedChannel: the ADC injected channel to set its offset. + * ADC_InjectedChannel_1 - Injected Channel1 selected. + * ADC_InjectedChannel_2 - Injected Channel2 selected. + * ADC_InjectedChannel_3 - Injected Channel3 selected. + * ADC_InjectedChannel_4 - Injected Channel4 selected. + * Offset - the offset value for the selected ADC injected channel. + * This parameter must be a 12bit value. + * + * @return None + */ +void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel; + + *(__IO uint32_t *)tmp = (uint32_t)Offset; +} + +/********************************************************************* + * @fn ADC_GetInjectedConversionValue + * + * @brief Returns the ADC injected channel conversion result. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_InjectedChannel - the ADC injected channel to set its offset. + * ADC_InjectedChannel_1 - Injected Channel1 selected. + * ADC_InjectedChannel_2 - Injected Channel2 selected. + * ADC_InjectedChannel_3 - Injected Channel3 selected. + * ADC_InjectedChannel_4 - Injected Channel4 selected. + * + * @return tmp - The Data conversion value. + */ +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel + IDATAR_Offset; + + return (uint16_t)(*(__IO uint32_t *)tmp); +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogCmd + * + * @brief Enables or disables the analog watchdog on single/all regular + * or injected channels. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_AnalogWatchdog - the ADC analog watchdog configuration. + * ADC_AnalogWatchdog_SingleRegEnable - Analog watchdog on a + * single regular channel. + * ADC_AnalogWatchdog_SingleInjecEnable - Analog watchdog on a + * single injected channel. + * ADC_AnalogWatchdog_SingleRegOrInjecEnable - Analog watchdog + * on a single regular or injected channel. + * ADC_AnalogWatchdog_AllRegEnable - Analog watchdog on all + * regular channel. + * ADC_AnalogWatchdog_AllInjecEnable - Analog watchdog on all + * injected channel. + * ADC_AnalogWatchdog_AllRegAllInjecEnable - Analog watchdog on + * all regular and injected channels. + * ADC_AnalogWatchdog_None - No channel guarded by the analog + * watchdog. + * + * @return none + */ +void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR1; + tmpreg &= CTLR1_AWDMode_Reset; + tmpreg |= ADC_AnalogWatchdog; + ADCx->CTLR1 = tmpreg; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogThresholdsConfig + * + * @brief Configures the high and low thresholds of the analog watchdog. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * HighThreshold - the ADC analog watchdog High threshold value. + * This parameter must be a 12bit value. + * LowThreshold - the ADC analog watchdog Low threshold value. + * This parameter must be a 12bit value. + * + * @return none + */ +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + ADCx->WDHTR = HighThreshold; + ADCx->WDLTR = LowThreshold; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdog1ThresholdsConfig + * + * @brief Configures the high and low thresholds of the analog watchdog1. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * HighThreshold - the ADC analog watchdog1 High threshold value. + * This parameter must be a 12bit value. + * LowThreshold - the ADC analog watchdog1 Low threshold value. + * This parameter must be a 12bit value. + * + * @return none + */ +void ADC_AnalogWatchdog1ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + ADCx->WDTR1 = (uint32_t)HighThreshold<<16; + ADCx->WDTR1 |= (uint32_t)LowThreshold; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdog2ThresholdsConfig + * + * @brief Configures the high and low thresholds of the analog watchdog2. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * HighThreshold - the ADC analog watchdog2 High threshold value. + * This parameter must be a 12bit value. + * LowThreshold - the ADC analog watchdog2 Low threshold value. + * This parameter must be a 12bit value. + * + * @return none + */ +void ADC_AnalogWatchdog2ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + ADCx->WDTR2 = (uint32_t)HighThreshold<<16; + ADCx->WDTR2 |= (uint32_t)LowThreshold; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdog3ThresholdsConfig + * + * @brief Configures the high and low thresholds of the analog watchdog3. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * HighThreshold - the ADC analog watchdog3 High threshold value. + * This parameter must be a 12bit value. + * LowThreshold - the ADC analog watchdog3 Low threshold value. + * This parameter must be a 12bit value. + * + * @return none + */ +void ADC_AnalogWatchdog3ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + ADCx->WDTR3 = (uint32_t)HighThreshold<<16; + ADCx->WDTR3 |= (uint32_t)LowThreshold; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogSingleChannelConfig + * + * @brief Configures the analog watchdog guarded single channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_10 - ADC Channel10 selected. + * ADC_Channel_11 - ADC Channel11 selected. + * ADC_Channel_12 - ADC Channel12 selected. + * ADC_Channel_13 - ADC Channel13 selected. + * ADC_Channel_14 - ADC Channel14 selected. + * ADC_Channel_15 - ADC Channel15 selected. + * + * @return None + */ +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR1; + tmpreg &= CTLR1_AWDCH_Reset; + tmpreg |= ADC_Channel; + ADCx->CTLR1 = tmpreg; +} + +/********************************************************************* + * @fn ADC_GetFlagStatus + * + * @brief Checks whether the specified ADC flag is set or not. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_FLAG - specifies the flag to check. + * ADC_FLAG_AWD - Analog watchdog flag. + * ADC_FLAG_EOC - End of conversion flag. + * ADC_FLAG_JEOC - End of injected group conversion flag. + * ADC_FLAG_JSTRT - Start of injected group conversion flag. + * ADC_FLAG_STRT - Start of regular group conversion flag. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->STATR & ADC_FLAG) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_ClearFlag + * + * @brief Clears the ADCx's pending flags. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_FLAG - specifies the flag to clear. + * ADC_FLAG_AWD - Analog watchdog flag. + * ADC_FLAG_EOC - End of conversion flag. + * ADC_FLAG_JEOC - End of injected group conversion flag. + * ADC_FLAG_JSTRT - Start of injected group conversion flag. + * ADC_FLAG_STRT - Start of regular group conversion flag. + * + * @return none + */ +void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) +{ + ADCx->STATR = ~(uint32_t)ADC_FLAG; +} + +/********************************************************************* + * @fn ADC_GetITStatus + * + * @brief Checks whether the specified ADC interrupt has occurred or not. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt source to check. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * + * @return FlagStatus: SET or RESET. + */ +ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t itmask = 0, enablestatus = 0; + + itmask = ADC_IT >> 8; + enablestatus = (ADCx->CTLR1 & (uint8_t)ADC_IT); + + if(((ADCx->STATR & itmask) != (uint32_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_ClearITPendingBit + * + * @brief Clears the ADCx's interrupt pending bits. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt pending bit to clear. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * + * @return none + */ +void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT) +{ + uint8_t itmask = 0; + + itmask = (uint8_t)(ADC_IT >> 8); + ADCx->STATR = ~(uint32_t)itmask; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogResetCmd + * + * @brief Enables or disables the analog watchdog reset + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_AnalogWatchdog_x - Analog watchdog X. + * ADC_AnalogWatchdog_0_RST_EN. + * ADC_AnalogWatchdog_1_RST_EN. + * ADC_AnalogWatchdog_2_RST_EN. + * ADC_AnalogWatchdog_3_RST_EN. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_AnalogWatchdogResetCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog_x, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + ADCx->CTLR3 |= ADC_AnalogWatchdog_x; + } + else + { + ADCx->CTLR3 &= ~ADC_AnalogWatchdog_x; + } +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogScanCmd + * + * @brief Enable ADC clock duty cycle adjustment. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_AnalogWatchdogScanCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + ADCx->CTLR3 |= (1<<9); + } + else + { + ADCx->CTLR3 &= ~(1<<9); + } +} + +/********************************************************************* + * @fn ADC_CLKConfig + * + * @brief Configures the PADC clock. + * Note - ADC_CLK_Div_x > H_Level_Cycles_x + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_CLK_Div_x - defines the ADC clock divider. + * ADC_CLK_Div4 - ADC clock = SYSCLK/4 + * ADC_CLK_Div5 - ADC clock = SYSCLK/5 + * ADC_CLK_Div6 - ADC clock = SYSCLK/6 + * ADC_CLK_Div7 - ADC clock = SYSCLK/7 + * ADC_CLK_Div8 - ADC clock = SYSCLK/8 + * ADC_CLK_Div9 - ADC clock = SYSCLK/9 + * ADC_CLK_Div10 - ADC clock = SYSCLK/10 + * ADC_CLK_Div11 - ADC clock = SYSCLK/11 + * ADC_CLK_Div12 - ADC clock = SYSCLK/12 + * ADC_CLK_Div13 - ADC clock = SYSCLK/13 + * ADC_CLK_Div14 - ADC clock = SYSCLK/14 + * ADC_CLK_Div15 - ADC clock = SYSCLK/15 + * ADC_CLK_Div16 - ADC clock = SYSCLK/16 + * @return none + */ +void ADC_CLKConfig(ADC_TypeDef *ADCx, uint32_t ADC_CLK_Div_x) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR3; + + tmpreg &= CTLR3_CLK_Mask; + tmpreg |= ADC_CLK_Div_x; + ADCx->CTLR3 = tmpreg; +} + diff --git a/Code/DAP_X033/Peripheral/src/ch32x035_awu.c b/Code/DAP_X033/Peripheral/src/ch32x035_awu.c new file mode 100644 index 0000000..2e0fdff --- /dev/null +++ b/Code/DAP_X033/Peripheral/src/ch32x035_awu.c @@ -0,0 +1,92 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_awu.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file provides all the AWU firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_awu.h" + +/* PSC registers bit mask */ +#define AWUPSC_MASK ((uint32_t)0xFFFFFFF0) + +/* WR register bit mask */ +#define AWUWR_MASK ((uint32_t)0xFFFFFFC0) + +/********************************************************************* + * @fn AutoWakeUpCmd + * + * @brief Enables or disables the Auto WakeUp functionality. + * + * @param NewState - new state of the Auto WakeUp functionality + * (ENABLE or DISABLE). + * + * @return none + */ +void AutoWakeUpCmd(FunctionalState NewState) +{ + if(NewState) + { + AWU->CSR |= (1 << 1); + } + else + { + AWU->CSR &= ~(1 << 1); + } +} + +/********************************************************************* + * @fn AWU_SetPrescaler + * + * @brief Sets the Auto Wake up Prescaler + * + * @param AWU_Prescaler - specifies the Auto Wake up Prescaler + * AWU_Prescaler_1 - AWU counter clock = LSI/1 + * AWU_Prescaler_2 - AWU counter clock = LSI/2 + * AWU_Prescaler_4 - AWU counter clock = LSI/4 + * AWU_Prescaler_8 - AWU counter clock = LSI/8 + * AWU_Prescaler_16 - AWU counter clock = LSI/16 + * AWU_Prescaler_32 - AWU counter clock = LSI/32 + * AWU_Prescaler_64 - AWU counter clock = LSI/64 + * AWU_Prescaler_128 - AWU counter clock = LSI/128 + * AWU_Prescaler_256 - AWU counter clock = LSI/256 + * AWU_Prescaler_512 - AWU counter clock = LSI/512 + * AWU_Prescaler_1024 - AWU counter clock = LSI/1024 + * AWU_Prescaler_2048 - AWU counter clock = LSI/2048 + * AWU_Prescaler_4096 - AWU counter clock = LSI/4096 + * AWU_Prescaler_10240 - AWU counter clock = LSI/10240 + * AWU_Prescaler_61440 - AWU counter clock = LSI/61440 + * + * @return none + */ +void AWU_SetPrescaler(uint32_t AWU_Prescaler) +{ + uint32_t tmpreg = 0; + tmpreg = AWU->PSC & AWUPSC_MASK; + tmpreg |= AWU_Prescaler; + AWU->PSC = tmpreg; +} + +/********************************************************************* + * @fn AWU_SetWindowValue + * + * @brief Sets the WWDG window value + * + * @param WindowValue - specifies the window value to be compared to the + * downcounter,which must be lower than 0x3F + * + * @return none + */ +void AWU_SetWindowValue(uint8_t WindowValue) +{ + __IO uint32_t tmpreg = 0; + + tmpreg = AWU->WR & AWUWR_MASK; + tmpreg |= WindowValue; + + AWU->WR = tmpreg; +} diff --git a/Code/DAP_X033/Peripheral/src/ch32x035_dbgmcu.c b/Code/DAP_X033/Peripheral/src/ch32x035_dbgmcu.c new file mode 100644 index 0000000..2bebff9 --- /dev/null +++ b/Code/DAP_X033/Peripheral/src/ch32x035_dbgmcu.c @@ -0,0 +1,120 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_dbgmcu.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file provides all the DBGMCU firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_dbgmcu.h" + +#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) + +/********************************************************************* + * @fn DBGMCU_GetREVID + * + * @brief Returns the device revision identifier. + * + * @return Revision identifier. + */ +uint32_t DBGMCU_GetREVID(void) +{ + return ((*(uint32_t *)0x1FFFF704) >> 16); +} + +/********************************************************************* + * @fn DBGMCU_GetDEVID + * + * @brief Returns the device identifier. + * + * @return Device identifier. + */ +uint32_t DBGMCU_GetDEVID(void) +{ + return ((*(uint32_t *)0x1FFFF704) & IDCODE_DEVID_MASK); +} + +/********************************************************************* + * @fn __get_DEBUG_CR + * + * @brief Return the DEBUGE Control Register + * + * @return DEBUGE Control value + */ +uint32_t __get_DEBUG_CR(void) +{ + uint32_t result; + + __asm volatile("csrr %0,""0x7C0" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_DEBUG_CR + * + * @brief Set the DEBUGE Control Register + * + * @param value - set DEBUGE Control value + * + * @return none + */ +void __set_DEBUG_CR(uint32_t value) +{ + __asm volatile("csrw 0x7C0, %0" : : "r"(value)); +} + + +/********************************************************************* + * @fn DBGMCU_Config + * + * @brief Configures the specified peripheral and low power mode behavior + * when the MCU under Debug mode. + * + * @param DBGMCU_Periph - specifies the peripheral and low power mode. + * DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted + * DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted + * DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted + * DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted + * DBGMCU_TIM3_STOP - TIM3 counter stopped when Core is halted + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + uint32_t val; + + if(NewState != DISABLE) + { + __set_DEBUG_CR(DBGMCU_Periph); + } + else + { + val = __get_DEBUG_CR(); + val &= ~(uint32_t)DBGMCU_Periph; + __set_DEBUG_CR(val); + } + +} +/********************************************************************* + * @fn DBGMCU_GetCHIPID + * + * @brief Returns the CHIP identifier. + * + * @return Device identifier. + * ChipID List- + * CH32X035R8T6-0x035006x1 + * CH32X035C8T6-0x035106x1 + * CH32X035F8U6-0x035E06x1 + * CH32X035G8U6-0x035606x1 + * CH32X035G8R6-0x035B06x1 + * CH32X035F7P6-0x035706x1 + * CH32X033F8P6-0x035A06x1 + */ +uint32_t DBGMCU_GetCHIPID( void ) +{ + return( *( uint32_t * )0x1FFFF704 ); +} diff --git a/Code/DAP_X033/Peripheral/src/ch32x035_dma.c b/Code/DAP_X033/Peripheral/src/ch32x035_dma.c new file mode 100644 index 0000000..7e19bcf --- /dev/null +++ b/Code/DAP_X033/Peripheral/src/ch32x035_dma.c @@ -0,0 +1,432 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_dma.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file provides all the DMA firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_dma.h" +#include "ch32x035_rcc.h" + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) +#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) +#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) +#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) +#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) +#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) +#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) +#define DMA1_Channel8_IT_Mask ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8)) + +/* DMA2 FLAG mask */ +#define FLAG_Mask ((uint32_t)0x10000000) + +/* DMA registers Masks */ +#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/********************************************************************* + * @fn DMA_DeInit + * + * @brief Deinitializes the DMAy Channelx registers to their default + * reset values. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * + * @return none + */ +void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx) +{ + DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); + DMAy_Channelx->CFGR = 0; + DMAy_Channelx->CNTR = 0; + DMAy_Channelx->PADDR = 0; + DMAy_Channelx->MADDR = 0; + if(DMAy_Channelx == DMA1_Channel1) + { + DMA1->INTFCR |= DMA1_Channel1_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel2) + { + DMA1->INTFCR |= DMA1_Channel2_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel3) + { + DMA1->INTFCR |= DMA1_Channel3_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel4) + { + DMA1->INTFCR |= DMA1_Channel4_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel5) + { + DMA1->INTFCR |= DMA1_Channel5_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel6) + { + DMA1->INTFCR |= DMA1_Channel6_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel7) + { + DMA1->INTFCR |= DMA1_Channel7_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel8) + { + DMA1->INTFCR |= DMA1_Channel8_IT_Mask; + } +} + +/********************************************************************* + * @fn DMA_Init + * + * @brief Initializes the DMAy Channelx according to the specified + * parameters in the DMA_InitStruct. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains + * contains the configuration information for the specified DMA Channel. + * + * @return none + */ +void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct) +{ + uint32_t tmpreg = 0; + + tmpreg = DMAy_Channelx->CFGR; + tmpreg &= CFGR_CLEAR_Mask; + tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; + + DMAy_Channelx->CFGR = tmpreg; + DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize; + DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr; + DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr; +} + +/********************************************************************* + * @fn DMA_StructInit + * + * @brief Fills each DMA_InitStruct member with its default value. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains + * contains the configuration information for the specified DMA Channel. + * + * @return none + */ +void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct) +{ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + DMA_InitStruct->DMA_MemoryBaseAddr = 0; + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; + DMA_InitStruct->DMA_BufferSize = 0; + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; +} + +/********************************************************************* + * @fn DMA_Cmd + * + * @brief Enables or disables the specified DMAy Channelx. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). + * + * @return none + */ +void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMAy_Channelx->CFGR |= DMA_CFGR1_EN; + } + else + { + DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); + } +} + +/********************************************************************* + * @fn DMA_ITConfig + * + * @brief Enables or disables the specified DMAy Channelx interrupts. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * DMA_IT - specifies the DMA interrupts sources to be enabled + * or disabled. + * DMA_IT_TC - Transfer complete interrupt mask + * DMA_IT_HT - Half transfer interrupt mask + * DMA_IT_TE - Transfer error interrupt mask + * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). + * + * @return none + */ +void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMAy_Channelx->CFGR |= DMA_IT; + } + else + { + DMAy_Channelx->CFGR &= ~DMA_IT; + } +} + +/********************************************************************* + * @fn DMA_SetCurrDataCounter + * + * @brief Sets the number of data units in the current DMAy Channelx transfer. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * DataNumber - The number of data units in the current DMAy Channelx + * transfer. + * + * @return none + */ +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber) +{ + DMAy_Channelx->CNTR = DataNumber; +} + +/********************************************************************* + * @fn DMA_GetCurrDataCounter + * + * @brief Returns the number of remaining data units in the current + * DMAy Channelx transfer. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 8 for DMA1 to select the DMA Channel. + * + * @return DataNumber - The number of remaining data units in the current + * DMAy Channelx transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx) +{ + return ((uint16_t)(DMAy_Channelx->CNTR)); +} + +/********************************************************************* + * @fn DMA_GetFlagStatus + * + * @brief Checks whether the specified DMAy Channelx flag is set or not. + * + * @param DMAy_FLAG - specifies the flag to check. + * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. + * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. + * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. + * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. + * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. + * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. + * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. + * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. + * DMA1_FLAG_GL8 - DMA1 Channel8 global flag. + * DMA1_FLAG_TC8 - DMA1 Channel8 transfer complete flag. + * DMA1_FLAG_HT8 - DMA1 Channel8 half transfer flag. + * DMA1_FLAG_TE8 - DMA1 Channel8 transfer error flag. + + * @return The new state of DMAy_FLAG (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + tmpreg = DMA1->INTFR; + + if((tmpreg & DMAy_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn DMA_ClearFlag + * + * @brief Clears the DMAy Channelx's pending flags. + * + * @param DMAy_FLAG - specifies the flag to check. + * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. + * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. + * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. + * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. + * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. + * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. + * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. + * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. + * DMA1_FLAG_GL8 - DMA1 Channel8 global flag. + * DMA1_FLAG_TC8 - DMA1 Channel8 transfer complete flag. + * DMA1_FLAG_HT8 - DMA1 Channel8 half transfer flag. + * DMA1_FLAG_TE8 - DMA1 Channel8 transfer error flag. + * @return none + */ +void DMA_ClearFlag(uint32_t DMAy_FLAG) +{ + DMA1->INTFCR = DMAy_FLAG; +} + +/********************************************************************* + * @fn DMA_GetITStatus + * + * @brief Checks whether the specified DMAy Channelx interrupt has + * occurred or not. + * + * @param DMAy_IT - specifies the DMAy interrupt source to check. + * DMA1_IT_GL1 - DMA1 Channel1 global flag. + * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_IT_GL2 - DMA1 Channel2 global flag. + * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_IT_GL3 - DMA1 Channel3 global flag. + * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_IT_GL4 - DMA1 Channel4 global flag. + * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_IT_GL5 - DMA1 Channel5 global flag. + * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_IT_GL6 - DMA1 Channel6 global flag. + * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_IT_GL7 - DMA1 Channel7 global flag. + * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. + * DMA1_IT_GL8 - DMA1 Channel8 global flag. + * DMA1_IT_TC8 - DMA1 Channel8 transfer complete flag. + * DMA1_IT_HT8 - DMA1 Channel8 half transfer flag. + * DMA1_IT_TE8 - DMA1 Channel8 transfer error flag. + * @return The new state of DMAy_IT (SET or RESET). + */ +ITStatus DMA_GetITStatus(uint32_t DMAy_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + tmpreg = DMA1->INTFR; + + if((tmpreg & DMAy_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn DMA_ClearITPendingBit + * + * @brief Clears the DMAy Channelx's interrupt pending bits. + * + * @param DMAy_IT - specifies the DMAy interrupt source to check. + * DMA1_IT_GL1 - DMA1 Channel1 global flag. + * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_IT_GL2 - DMA1 Channel2 global flag. + * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_IT_GL3 - DMA1 Channel3 global flag. + * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_IT_GL4 - DMA1 Channel4 global flag. + * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_IT_GL5 - DMA1 Channel5 global flag. + * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_IT_GL6 - DMA1 Channel6 global flag. + * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_IT_GL7 - DMA1 Channel7 global flag. + * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. + * DMA1_IT_GL8 - DMA1 Channel8 global flag. + * DMA1_IT_TC8 - DMA1 Channel8 transfer complete flag. + * DMA1_IT_HT8 - DMA1 Channel8 half transfer flag. + * DMA1_IT_TE8 - DMA1 Channel8 transfer error flag. + * @return none + */ +void DMA_ClearITPendingBit(uint32_t DMAy_IT) +{ + DMA1->INTFCR = DMAy_IT; +} diff --git a/Code/DAP_X033/Peripheral/src/ch32x035_exti.c b/Code/DAP_X033/Peripheral/src/ch32x035_exti.c new file mode 100644 index 0000000..b18c383 --- /dev/null +++ b/Code/DAP_X033/Peripheral/src/ch32x035_exti.c @@ -0,0 +1,182 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_exti.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file provides all the EXTI firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_exti.h" + +/* No interrupt selected */ +#define EXTI_LINENONE ((uint32_t)0x00000) + +/********************************************************************* + * @fn EXTI_DeInit + * + * @brief Deinitializes the EXTI peripheral registers to their default + * reset values. + * + * @return none. + */ +void EXTI_DeInit(void) +{ + EXTI->INTENR = 0x00000000; + EXTI->EVENR = 0x00000000; + EXTI->RTENR = 0x00000000; + EXTI->FTENR = 0x00000000; + EXTI->INTFR = 0x000FFFFF; +} + +/********************************************************************* + * @fn EXTI_Init + * + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure + * + * @return none. + */ +void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct) +{ + uint32_t tmp = 0; + + tmp = (uint32_t)EXTI_BASE; + if(EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line; + tmp += EXTI_InitStruct->EXTI_Mode; + *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; + EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line; + if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + EXTI->RTENR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTENR |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp += EXTI_InitStruct->EXTI_Mode; + *(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/********************************************************************* + * @fn EXTI_StructInit + * + * @brief Fills each EXTI_InitStruct member with its reset value. + * + * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure + * + * @return none. + */ +void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/********************************************************************* + * @fn EXTI_GenerateSWInterrupt + * + * @brief Generates a Software interrupt. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return none. + */ +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + EXTI->SWIEVR |= EXTI_Line; +} + +/********************************************************************* + * @fn EXTI_GetFlagStatus + * + * @brief Checks whether the specified EXTI line flag is set or not. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return The new state of EXTI_Line (SET or RESET). + */ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn EXTI_ClearFlag + * + * @brief Clears the EXTI's line pending flags. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return None + */ +void EXTI_ClearFlag(uint32_t EXTI_Line) +{ + EXTI->INTFR = EXTI_Line; +} + +/********************************************************************* + * @fn EXTI_GetITStatus + * + * @brief Checks whether the specified EXTI line is asserted or not. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return The new state of EXTI_Line (SET or RESET). + */ +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + enablestatus = EXTI->INTENR & EXTI_Line; + if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn EXTI_ClearITPendingBit + * + * @brief Clears the EXTI's line pending bits. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return none + */ +void EXTI_ClearITPendingBit(uint32_t EXTI_Line) +{ + EXTI->INTFR = EXTI_Line; +} diff --git a/Code/DAP_X033/Peripheral/src/ch32x035_flash.c b/Code/DAP_X033/Peripheral/src/ch32x035_flash.c new file mode 100644 index 0000000..5f3e9ff --- /dev/null +++ b/Code/DAP_X033/Peripheral/src/ch32x035_flash.c @@ -0,0 +1,1022 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_flash.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file provides all the FLASH firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_flash.h" + +/* Flash Access Control Register bits */ +#define ACR_LATENCY_Mask ((uint32_t)0x00000038) + +/* Flash Control Register bits */ +#define CR_PER_Set ((uint32_t)0x00000002) +#define CR_PER_Reset ((uint32_t)0xFFFFFFFD) +#define CR_MER_Set ((uint32_t)0x00000004) +#define CR_MER_Reset ((uint32_t)0xFFFFFFFB) +#define CR_OPTPG_Set ((uint32_t)0x00000010) +#define CR_OPTPG_Reset ((uint32_t)0xFFFFFFEF) +#define CR_OPTER_Set ((uint32_t)0x00000020) +#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF) +#define CR_STRT_Set ((uint32_t)0x00000040) +#define CR_LOCK_Set ((uint32_t)0x00000080) +#define CR_FLOCK_Set ((uint32_t)0x00008000) +#define CR_PAGE_PG ((uint32_t)0x00010000) +#define CR_PAGE_ER ((uint32_t)0x00020000) +#define CR_BUF_LOAD ((uint32_t)0x00040000) +#define CR_BUF_RST ((uint32_t)0x00080000) +#define CR_BER32 ((uint32_t)0x00800000) + +/* FLASH Status Register bits */ +#define SR_BSY ((uint32_t)0x00000001) +#define SR_WRPRTERR ((uint32_t)0x00000010) +#define SR_EOP ((uint32_t)0x00000020) + +/* FLASH Mask */ +#define RDPRT_Mask ((uint32_t)0x00000002) +#define WRP0_Mask ((uint32_t)0x000000FF) +#define WRP1_Mask ((uint32_t)0x0000FF00) +#define WRP2_Mask ((uint32_t)0x00FF0000) +#define WRP3_Mask ((uint32_t)0xFF000000) + +/* FLASH Keys */ +#define RDP_Key ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/* FLASH BANK address */ +#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x000B0000) +#define ProgramTimeout ((uint32_t)0x00005000) + +/* Flash Program Vaild Address */ +#define ValidAddrStart (FLASH_BASE) +#define ValidAddrEnd (FLASH_BASE + 0xF800) + +/* FLASH Size */ +#define Size_256B 0x100 +#define Size_1KB 0x400 +#define Size_32KB 0x8000 + +/******************************************************************************** + * @fn FLASH_SetLatency + * + * @brief Sets the code latency value. + * + * @param FLASH_Latency - specifies the FLASH Latency value. + * FLASH_Latency_0 - FLASH Zero Latency cycle + * FLASH_Latency_1 - FLASH One Latency cycle + * FLASH_Latency_2 - FLASH Two Latency cycles + * + * @return None + */ +void FLASH_SetLatency(uint32_t FLASH_Latency) +{ + uint32_t tmpreg = 0; + + tmpreg = FLASH->ACTLR; + tmpreg &= ACR_LATENCY_Mask; + tmpreg |= FLASH_Latency; + FLASH->ACTLR = tmpreg; +} + +/******************************************************************************** + * @fn FLASH_Unlock + * + * @brief Unlocks the FLASH Program Erase Controller. + * + * @return None + */ +void FLASH_Unlock(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +/******************************************************************************** + * @fn FLASH_Lock + * + * @brief Locks the FLASH Program Erase Controller. + * + * @return None + */ +void FLASH_Lock(void) +{ + FLASH->CTLR |= CR_LOCK_Set; +} + +/******************************************************************************** + * @fn FLASH_ErasePage + * + * @brief Erases a specified FLASH page(1KB). + * + * @param Page_Address - The page address to be erased. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ErasePage(uint32_t Page_Address) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_PER_Set; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_PER_Reset; + } + + return status; +} + +/******************************************************************************** + * @fn FLASH_EraseAllPages + * + * @brief Erases all FLASH pages. + * + * @return FLASH Status - The returned value can be:FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllPages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_MER_Set; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_MER_Reset; + } + + return status; +} + +/******************************************************************************** + * @fn FLASH_EraseOptionBytes + * + * @brief Erases the FLASH option bytes. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseOptionBytes(void) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH_Unlock(); + + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_OPTER_Reset; + + FLASH_Lock(); + } + return status; +} + +/********************************************************************* + * @fn FLASH_OptionBytePR + * + * @brief Programs option bytes. + * + * @param pbuf - data. + * + * @return none + */ +void FLASH_OptionBytePR(u32* pbuf) +{ + uint8_t i; + + FLASH_EraseOptionBytes(); + FLASH_Unlock_Fast(); + FLASH_BufReset(); + + for(i=0; i<4; i++) + { + FLASH_BufLoad((OB_BASE + 4*i), *pbuf++); + } + + FLASH_ProgramPage_Fast(OB_BASE); + FLASH_Lock_Fast(); +} + +/********************************************************************* + * @fn FLASH_EnableWriteProtection + * + * @brief Write protects the desired sectors + * + * @param FLASH_Sectors - specifies the address of the pages to be write protected. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE , FLASH_TIMEOUT or FLASH_RDP. + */ +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages) +{ + uint8_t WRP0_Data = 0xFF, WRP1_Data = 0xFF, WRP2_Data = 0xFF, WRP3_Data = 0xFF; + uint32_t buf[4]; + uint8_t i; + FLASH_Status status = FLASH_COMPLETE; + + if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + status = FLASH_RDP; + } + else{ + FLASH_Pages = (uint32_t)(~FLASH_Pages); + WRP0_Data = (uint8_t)(FLASH_Pages & WRP0_Mask); + WRP1_Data = (uint8_t)((FLASH_Pages & WRP1_Mask) >> 8); + WRP2_Data = (uint8_t)((FLASH_Pages & WRP2_Mask) >> 16); + WRP3_Data = (uint8_t)((FLASH_Pages & WRP3_Mask) >> 24); + + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + for(i=0; i<4; i++){ + buf[i] = *(uint32_t*)(OB_BASE + 4*i); + } + + buf[2] = ((uint32_t)(((uint32_t)(WRP0_Data) & 0x00FF) + (((uint32_t)(~WRP0_Data) & 0x00FF) << 8) \ + + (((uint32_t)(WRP1_Data) & 0x00FF) << 16) + (((uint32_t)(~WRP1_Data) & 0x00FF) << 24))); + buf[3] = ((uint32_t)(((uint32_t)(WRP2_Data) & 0x00FF) + (((uint32_t)(~WRP2_Data) & 0x00FF) << 8) \ + + (((uint32_t)(WRP3_Data) & 0x00FF) << 16) + (((uint32_t)(~WRP3_Data) & 0x00FF) << 24))); + + FLASH_OptionBytePR(buf); + } + } + + return status; +} + +/********************************************************************* + * @fn FLASH_EnableReadOutProtection + * + * @brief Enables the read out protection. + * + * @param Newstate - new state of the ReadOut Protection(ENABLE or DISABLE). + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE, FLASH_TIMEOUT or FLASH_RDP. + */ +FLASH_Status FLASH_EnableReadOutProtection(void) +{ + FLASH_Status status = FLASH_COMPLETE; + uint32_t buf[4]; + uint8_t i; + + if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + status = FLASH_RDP; + } + else{ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + for(i=0; i<4; i++){ + buf[i] = *(uint32_t*)(OB_BASE + 4*i); + } + + buf[0] = 0x000000FF + (buf[0] & 0xFFFF0000); + FLASH_OptionBytePR(buf); + } + } + + return status; +} + +/********************************************************************* + * @fn FLASH_UserOptionByteConfig + * + * @brief Programs the FLASH User Option Byte - IWDG_SW / RST_STOP / RST_STDBY. + * + * @param OB_IWDG - Selects the IWDG mode + * OB_IWDG_SW - Software IWDG selected + * OB_IWDG_HW - Hardware IWDG selected + * OB_STOP - Reset event when entering STOP mode. + * OB_STOP_NoRST - No reset generated when entering in STOP + * OB_STOP_RST - Reset generated when entering in STOP + * OB_STDBY - Reset event when entering Standby mode. + * OB_STDBY_NoRST - No reset generated when entering in STANDBY + * OB_STDBY_RST - Reset generated when entering in STANDBY + * OB_RST - Selects the reset IO mode and Ignore delay time + * OB_RST_NoEN - Reset IO disable + * OB_RST_EN_DT12ms - Reset IO enable and Ignore delay time 12ms + * OB_RST_EN_DT1ms - Reset IO enable and Ignore delay time 1ms + * OB_RST_EN_DT128us - Reset IO enable and Ignore delay time 128us + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE , FLASH_TIMEOUT or FLASH_RDP. + */ +FLASH_Status FLASH_UserOptionByteConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY, uint8_t OB_RST) +{ + FLASH_Status status = FLASH_COMPLETE; + uint8_t UserByte; + uint32_t buf[4]; + uint8_t i; + + if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + status = FLASH_RDP; + } + else{ + UserByte = OB_IWDG | (uint8_t)(OB_STOP | (uint8_t)(OB_STDBY | (uint8_t)(OB_RST | (uint8_t)0xE0))); + + for(i=0; i<4; i++){ + buf[i] = *(uint32_t*)(OB_BASE + 4*i); + } + buf[0] = ((uint32_t)((((uint32_t)(UserByte) & 0x00FF) << 16) + (((uint32_t)(~UserByte) & 0x00FF) << 24))) + 0x00005AA5; + + FLASH_OptionBytePR(buf); + } + + return status; +} + +/********************************************************************* + * @fn FLASH_GetUserOptionByte + * + * @brief Returns the FLASH User Option Bytes values. + * + * @return The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1), + * RST_STDBY(Bit2) ,RST_MOD(bit[4:3]) ,DATA0(bit[17:10]) and + * DATA1(bit[25:18]). + */ +uint32_t FLASH_GetUserOptionByte(void) +{ + return (uint32_t)(FLASH->OBR >> 2); +} + +/********************************************************************* + * @fn FLASH_GetWriteProtectionOptionByte + * + * @brief Returns the FLASH Write Protection Option Bytes Register value. + * + * @return The FLASH Write Protection Option Bytes Register value. + */ +uint32_t FLASH_GetWriteProtectionOptionByte(void) +{ + return (uint32_t)(FLASH->WPR); +} + +/********************************************************************* + * @fn FLASH_GetReadOutProtectionStatus + * + * @brief Checks whether the FLASH Read Out Protection Status is set or not. + * + * @return FLASH ReadOut Protection Status(SET or RESET) + */ +FlagStatus FLASH_GetReadOutProtectionStatus(void) +{ + FlagStatus readoutstatus = RESET; + if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + readoutstatus = SET; + } + else + { + readoutstatus = RESET; + } + return readoutstatus; +} + +/********************************************************************* + * @fn FLASH_ITConfig + * + * @brief Enables or disables the specified FLASH interrupts. + * + * @param FLASH_IT - specifies the FLASH interrupt sources to be enabled or disabled. + * FLASH_IT_ERROR - FLASH Error Interrupt + * FLASH_IT_EOP - FLASH end of operation Interrupt + * NewState - new state of the specified Flash interrupts(ENABLE or DISABLE). + * + * @return FLASH Prefetch Buffer Status (SET or RESET). + */ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + FLASH->CTLR |= FLASH_IT; + } + else + { + FLASH->CTLR &= ~(uint32_t)FLASH_IT; + } +} + +/********************************************************************* + * @fn FLASH_GetFlagStatus + * + * @brief Checks whether the specified FLASH flag is set or not. + * + * @param FLASH_FLAG - specifies the FLASH flag to check. + * FLASH_FLAG_BSY - FLASH Busy flag + * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag + * FLASH_FLAG_EOP - FLASH End of Operation flag + * FLASH_FLAG_OPTERR - FLASH Option Byte error flag + * + * @return The new state of FLASH_FLAG (SET or RESET). + */ +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + + if(FLASH_FLAG == FLASH_FLAG_OPTERR) + { + if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH->STATR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + return bitstatus; +} + +/********************************************************************* + * @fn FLASH_ClearFlag + * + * @brief Clears the FLASH's pending flags. + * + * @param FLASH_FLAG - specifies the FLASH flags to clear. + * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag + * FLASH_FLAG_EOP - FLASH End of Operation flag + * + * @return none + */ +void FLASH_ClearFlag(uint32_t FLASH_FLAG) +{ + FLASH->STATR = FLASH_FLAG; +} + +/********************************************************************* + * @fn FLASH_GetStatus + * + * @brief Returns the FLASH Status. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetStatus(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->STATR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->STATR & FLASH_FLAG_WRPRTERR) != 0) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + return flashstatus; +} + +/********************************************************************* + * @fn FLASH_GetBank1Status + * + * @brief Returns the FLASH Bank1 Status. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetBank1Status(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->STATR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->STATR & FLASH_FLAG_BANK1_WRPRTERR) != 0) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + return flashstatus; +} + +/********************************************************************* + * @fn FLASH_WaitForLastOperation + * + * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. + * + * @param Timeout - FLASH programming Timeout + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_GetBank1Status(); + while((status == FLASH_BUSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + return status; +} + +/********************************************************************* + * @fn FLASH_WaitForLastBank1Operation + * + * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur. + * + * @param Timeout - FLASH programming Timeout + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_GetBank1Status(); + while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + return status; +} + +/********************************************************************* + * @fn FLASH_Unlock_Fast + * + * @brief Unlocks the Fast Program Erase Mode. + * + * @return none + */ +void FLASH_Unlock_Fast(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast program mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; +} + +/********************************************************************* + * @fn FLASH_Lock_Fast + * + * @brief Locks the Fast Program Erase Mode. + * + * @return none + */ +void FLASH_Lock_Fast(void) +{ + FLASH->CTLR |= CR_FLOCK_Set; +} + +/********************************************************************* + * @fn FLASH_BufReset + * + * @brief Flash Buffer reset. + * + * @return none + */ +void FLASH_BufReset(void) +{ + FLASH->CTLR |= CR_PAGE_PG; + FLASH->CTLR |= CR_BUF_RST; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; +} + +/********************************************************************* + * @fn FLASH_BufLoad + * + * @brief Flash Buffer load(4Byte). + * + * @param Address - specifies the address to be programmed. + * Data0 - specifies the data0 to be programmed. + * + * @return none + */ +void FLASH_BufLoad(uint32_t Address, uint32_t Data0) +{ + FLASH->CTLR |= CR_PAGE_PG; + *(__IO uint32_t *)(Address) = Data0; + FLASH->CTLR |= CR_BUF_LOAD; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; +} + +/********************************************************************* + * @fn FLASH_ErasePage_Fast + * + * @brief Erases a specified FLASH page (1page = 256Byte). + * + * @param Page_Address - The page address to be erased. + * + * @return none + */ +void FLASH_ErasePage_Fast(uint32_t Page_Address) +{ + FLASH->CTLR |= CR_PAGE_ER; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_ER; +} + +/********************************************************************* + * @fn FLASH_EraseBlock_32K_Fast + * + * @brief Erases a specified FLASH Block (1Block = 32KByte). + * + * @param Block_Address - The block address to be erased. + * + * @return none + */ +void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address) +{ + Block_Address &= 0xFFFF8000; + + FLASH->CTLR |= CR_BER32; + FLASH->ADDR = Block_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_BER32; +} + +/********************************************************************* + * @fn FLASH_ProgramPage_Fast + * + * @brief Program a specified FLASH page (1page = 256Byte). + * + * @param Page_Address - The page address to be programed. + * + * @return none + */ +void FLASH_ProgramPage_Fast(uint32_t Page_Address) +{ + FLASH->CTLR |= CR_PAGE_PG; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; +} + +/********************************************************************* + * @fn SystemReset_StartMode + * + * @brief Start mode after system reset. + * + * @param Mode - Start mode. + * Start_Mode_USER - USER start after system reset + * Start_Mode_BOOT - Boot start after system reset + * @return none + */ +void SystemReset_StartMode(uint32_t Mode) +{ + FLASH_Unlock(); + + FLASH->BOOT_MODEKEYR = FLASH_KEY1; + FLASH->BOOT_MODEKEYR = FLASH_KEY2; + + FLASH->STATR &= ~(1<<14); + if(Mode == Start_Mode_BOOT){ + FLASH->STATR |= (1<<14); + } + + FLASH_Lock(); +} + +/********************************************************************* + * @fn ROM_ERASE + * + * @brief Select erases a specified FLASH . + * + * @param StartAddr - Erases Flash start address(StartAddr%256 == 0). + * Cnt - Erases count. + * Erase_Size - Erases size select.The returned value can be: + * Size_32KB, Size_1KB, Size_256B. + * + * @return none. + */ +static void ROM_ERASE(uint32_t StartAddr, uint32_t Cnt, uint32_t Erase_Size) +{ + do{ + if(Erase_Size == Size_32KB) + { + FLASH->CTLR |= CR_BER32; + } + else if(Erase_Size == Size_1KB) + { + FLASH->CTLR |= CR_PER_Set; + } + else if(Erase_Size == Size_256B) + { + FLASH->CTLR |= CR_PAGE_ER; + } + + FLASH->ADDR = StartAddr; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + + if(Erase_Size == Size_32KB) + { + FLASH->CTLR &= ~CR_BER32; + StartAddr += Size_32KB; + } + else if(Erase_Size == Size_1KB) + { + FLASH->CTLR &= ~CR_PER_Set; + StartAddr += Size_1KB; + } + else if(Erase_Size == Size_256B) + { + FLASH->CTLR &= ~CR_PAGE_ER; + StartAddr += Size_256B; + } + }while(--Cnt); +} + +/********************************************************************* + * @fn FLASH_ROM_ERASE + * + * @brief Erases a specified FLASH . + * + * @param StartAddr - Erases Flash start address(StartAddr%256 == 0). + * Length - Erases Flash start Length(Length%256 == 0). + * + * @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR, + * FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length) +{ + uint32_t Addr0 = 0, Addr1 = 0, Length0 = 0, Length1 = 0; + + FLASH_Status status = FLASH_COMPLETE; + + if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd)) + { + return FLASH_ADR_RANGE_ERROR; + } + + if((StartAddr + Length) > ValidAddrEnd) + { + return FLASH_OP_RANGE_ERROR; + } + + if((StartAddr & (Size_256B-1)) || (Length & (Size_256B-1)) || (Length == 0)) + { + return FLASH_ALIGN_ERROR; + } + + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; + + Addr0 = StartAddr; + + if(Length >= Size_32KB) + { + Length0 = Size_32KB - (Addr0 & (Size_32KB - 1)); + Addr1 = StartAddr + Length0; + Length1 = Length - Length0; + } + else if(Length >= Size_1KB) + { + Length0 = Size_1KB - (Addr0 & (Size_1KB - 1)); + Addr1 = StartAddr + Length0; + Length1 = Length - Length0; + } + else if(Length >= Size_256B) + { + Length0 = Length; + } + + /* Erase 32KB */ + if(Length0 >= Size_32KB)//front + { + Length = Length0; + if(Addr0 & (Size_32KB - 1)) + { + Length0 = Size_32KB - (Addr0 & (Size_32KB - 1)); + } + else + { + Length0 = 0; + } + + ROM_ERASE((Addr0 + Length0), ((Length - Length0) >> 15), Size_32KB); + } + + if(Length1 >= Size_32KB)//back + { + StartAddr = Addr1; + Length = Length1; + + if((Addr1 + Length1) & (Size_32KB - 1)) + { + Addr1 = ((StartAddr + Length1) & (~(Size_32KB - 1))); + Length1 = (StartAddr + Length1) & (Size_32KB - 1); + } + else + { + Length1 = 0; + } + + ROM_ERASE(StartAddr, ((Length - Length1) >> 15), Size_32KB); + } + + /* Erase 1KB */ + if(Length0 >= Size_1KB) //front + { + Length = Length0; + if(Addr0 & (Size_1KB - 1)) + { + Length0 = Size_1KB - (Addr0 & (Size_1KB - 1)); + } + else + { + Length0 = 0; + } + + ROM_ERASE((Addr0 + Length0), ((Length - Length0) >> 10), Size_1KB); + } + + if(Length1 >= Size_1KB) //back + { + StartAddr = Addr1; + Length = Length1; + + if((Addr1 + Length1) & (Size_1KB - 1)) + { + Addr1 = ((StartAddr + Length1) & (~(Size_1KB - 1))); + Length1 = (StartAddr + Length1) & (Size_1KB - 1); + } + else + { + Length1 = 0; + } + + ROM_ERASE(StartAddr, ((Length - Length1) >> 10), Size_1KB); + } + + /* Erase 256B */ + if(Length0)//front + { + ROM_ERASE(Addr0, (Length0 >> 8), Size_256B); + } + + if(Length1)//back + { + ROM_ERASE(Addr1, (Length1 >> 8), Size_256B); + } + + FLASH->CTLR |= CR_FLOCK_Set; + FLASH->CTLR |= CR_LOCK_Set; + + return status; +} + +/********************************************************************* + * @fn FLASH_ROM_WRITE + * + * @brief Writes a specified FLASH . + * + * @param StartAddr - Writes Flash start address(StartAddr%256 == 0). + * Length - Writes Flash start Length(Length%256 == 0). + * pbuf - Writes Flash value buffer. + * + * @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR, + * FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length) +{ + uint32_t i, adr; + uint8_t size; + + FLASH_Status status = FLASH_COMPLETE; + + if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd)) + { + return FLASH_ADR_RANGE_ERROR; + } + + if((StartAddr + Length) > ValidAddrEnd) + { + return FLASH_OP_RANGE_ERROR; + } + + if((StartAddr & (Size_256B-1)) || (Length & (Size_256B-1)) || (Length == 0)) + { + return FLASH_ALIGN_ERROR; + } + adr = StartAddr; + i = Length >> 8; + + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast program mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; + + do{ + FLASH->CTLR |= CR_PAGE_PG; + FLASH->CTLR |= CR_BUF_RST; + while(FLASH->STATR & SR_BSY) + ; + size = 64; + while(size) + { + *(uint32_t *)StartAddr = *(uint32_t *)pbuf; + FLASH->CTLR |= CR_BUF_LOAD; + while(FLASH->STATR & SR_BSY) + ; + StartAddr += 4; + pbuf += 1; + size -= 1; + } + + FLASH->ADDR = adr; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; + adr += 256; + }while(--i); + + FLASH->CTLR |= CR_FLOCK_Set; + FLASH->CTLR |= CR_LOCK_Set; + + return status; +} diff --git a/Code/DAP_X033/Peripheral/src/ch32x035_gpio.c b/Code/DAP_X033/Peripheral/src/ch32x035_gpio.c new file mode 100644 index 0000000..838db22 --- /dev/null +++ b/Code/DAP_X033/Peripheral/src/ch32x035_gpio.c @@ -0,0 +1,751 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_gpio.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file provides all the GPIO firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_gpio.h" +#include "ch32x035_rcc.h" + +/* MASK */ +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) +#define DBGAFR_TIM1RP_MASK ((uint32_t)0x00400000) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) + +volatile uint32_t CFGHR_tmpA = 0x44444444; +volatile uint32_t CFGHR_tmpB = 0x44444444; +volatile uint32_t CFGHR_tmpC = 0x44444444; + +/********************************************************************* + * @fn GPIO_DeInit + * + * @brief Deinitializes the GPIOx peripheral registers to their default + * reset values. + * + * @param GPIOx - where x can be (A..C) to select the GPIO peripheral. + * + * @return none + */ +void GPIO_DeInit(GPIO_TypeDef *GPIOx) +{ + if(GPIOx == GPIOA) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); + } + else if(GPIOx == GPIOB) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); + } + else if(GPIOx == GPIOC) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); + } +} + +/********************************************************************* + * @fn GPIO_AFIODeInit + * + * @brief Deinitializes the Alternate Functions (remap, event control + * and EXTI configuration) registers to their default reset values. + * + * @return none + */ +void GPIO_AFIODeInit(void) +{ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); +} + +/********************************************************************* + * @fn GPIO_Init + * + * @brief GPIOx - where x can be (A..C) to select the GPIO peripheral. + * Note - Only PA0--PA15 and PC16--PC17 support input pull-down + * + * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that + * contains the configuration information for the specified GPIO peripheral. + * + * @return none + */ +void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct) +{ + uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; + uint32_t tmpreg = 0x00, pinmask = 0x00; + + currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); + + if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) + { + currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; + } + + if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x0000FF)) != 0x00) + { + tmpreg = GPIOx->CFGLR; + + for(pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + + if(currentpin == pos) + { + pos = pinpos << 2; + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + tmpreg |= (currentmode << pos); + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BCR = (((uint32_t)0x01) << pinpos); + } + else + { + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSHR = (((uint32_t)0x01) << pinpos); + } + } + } + } + GPIOx->CFGLR = tmpreg; + } + + if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF00)) != 0x00) + { + if(GPIOx == GPIOA) + { + tmpreg = CFGHR_tmpA; + } + else if(GPIOx == GPIOB) + { + tmpreg = CFGHR_tmpB; + } + else if(GPIOx == GPIOC) + { + tmpreg = CFGHR_tmpC; + } + + for(pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = (((uint32_t)0x01) << (pinpos + 0x08)); + currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); + + if(currentpin == pos) + { + pos = pinpos << 2; + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + tmpreg |= (currentmode << pos); + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + } + } + GPIOx->CFGHR = tmpreg; + + if(GPIOx == GPIOA) + { + CFGHR_tmpA = tmpreg; + } + else if(GPIOx == GPIOB) + { + CFGHR_tmpB = tmpreg; + } + else if(GPIOx == GPIOC) + { + CFGHR_tmpC = tmpreg; + } + } + + if(GPIO_InitStruct->GPIO_Pin > 0x00FFFF) + { + tmpreg = GPIOx->CFGXR; + + for(pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = (((uint32_t)0x01) << (pinpos + 0x10)); + currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); + + if(currentpin == pos) + { + pos = pinpos << 2; + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + tmpreg |= (currentmode << pos); + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x10)); + } + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSXR = (((uint32_t)0x01) << (pinpos)); + } + } + } + GPIOx->CFGXR = tmpreg; + } +} + +/********************************************************************* + * @fn GPIO_StructInit + * + * @brief Fills each GPIO_InitStruct member with its default + * + * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct) +{ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +/********************************************************************* + * @fn GPIO_ReadInputDataBit + * + * @brief GPIOx - where x can be (A..C) to select the GPIO peripheral. + * + * @param GPIO_Pin - specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..23). + * + * @return The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn GPIO_ReadInputData + * + * @brief Reads the specified GPIO input data port. + * + * @param GPIOx - where x can be (A..C) to select the GPIO peripheral. + * + * @return The output port pin value. + */ +uint32_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx) +{ + uint32_t val; + + val = ( uint32_t )GPIOx->INDR; + + return ( val ); +} + +/********************************************************************* + * @fn GPIO_ReadOutputDataBit + * + * @brief Reads the specified output data port bit. + * + * @param GPIOx - where x can be (A..C) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..23). + * + * @return none + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn GPIO_ReadOutputData + * + * @brief Reads the specified GPIO output data port. + * + * @param GPIOx - where x can be (A..C) to select the GPIO peripheral. + * + * @return GPIO output port pin value. + */ +uint32_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx) +{ + uint32_t val; + + val = ( uint32_t )GPIOx->OUTDR; + + return ( val ); +} + +/********************************************************************* + * @fn GPIO_SetBits + * + * @brief Sets the selected data port bits. + * + * @param GPIOx - where x can be (A..C) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..23). + * + * @return none + */ +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + if((GPIO_Pin & ((uint32_t)0x00FFFF)) != 0x00) + { + GPIOx->BSHR = GPIO_Pin; + } + + if(GPIO_Pin > 0x00FFFF) + { + GPIOx->BSXR = (GPIO_Pin>>0x10); + } +} + +/********************************************************************* + * @fn GPIO_ResetBits + * + * @brief Clears the selected data port bits. + * + * @param GPIOx - where x can be (A..C) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..23). + * + * @return none + */ +void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + GPIOx->BCR = GPIO_Pin; +} + +/********************************************************************* + * @fn GPIO_WriteBit + * + * @brief Sets or clears the selected data port bit. + * + * @param GPIO_Pin - specifies the port bit to be written. + * This parameter can be one of GPIO_Pin_x where x can be (0..23). + * BitVal - specifies the value to be written to the selected bit. + * Bit_RESET - to clear the port pin. + * Bit_SET - to set the port pin. + * + * @return none + */ +void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, BitAction BitVal) +{ + if(BitVal != Bit_RESET) + { + if((GPIO_Pin & ((uint32_t)0x00FFFF)) != 0x00) + { + GPIOx->BSHR = GPIO_Pin; + } + + if(GPIO_Pin > 0x00FFFF) + { + GPIOx->BSXR = (GPIO_Pin>>0x10); + } + } + else + { + GPIOx->BCR = GPIO_Pin; + } +} + +/********************************************************************* + * @fn GPIO_Write + * + * @brief Writes data to the specified GPIO data port. + * + * @param GPIOx - where x can be (A..C) to select the GPIO peripheral. + * PortVal - specifies the value to be written to the port output data register. + * + * @return none + */ +void GPIO_Write(GPIO_TypeDef *GPIOx, uint32_t PortVal) +{ + GPIOx->OUTDR = PortVal; +} + +/********************************************************************* + * @fn GPIO_PinLockConfig + * + * @brief Locks GPIO Pins configuration registers. + * + * @param GPIOx - where x can be (A..C) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..23). + * + * @return none + */ +void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint32_t tmp = 0x01000000; + + tmp |= GPIO_Pin; + GPIOx->LCKR = tmp; + GPIOx->LCKR = GPIO_Pin; + GPIOx->LCKR = tmp; + tmp = GPIOx->LCKR; + tmp = GPIOx->LCKR; +} + +/********************************************************************* + * @fn GPIO_PinRemapConfig + * + * @brief Changes the mapping of the specified pin. + * + * @param GPIO_Remap - selects the pin to remap. + * GPIO_Remap_SPI1 - SPI1 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_SPI1 - SPI1 Partial2 Alternate Function mapping + * GPIO_FullRemap_SPI1 - SPI1 Full Alternate Function mapping + * GPIO_PartialRemap1_I2C1 - I2C1 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_I2C1 - I2C1 Partial2 Alternate Function mapping + * GPIO_PartialRemap3_I2C1 - I2C1 Partial3 Alternate Function mapping + * GPIO_PartialRemap4_I2C1 - I2C1 Partial4 Alternate Function mapping + * GPIO_FullRemap_I2C1 - I2C1 Full Alternate Function mapping + * GPIO_PartialRemap1_USART1 - USART1 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_USART1 - USART1 Partial2 Alternate Function mapping + * GPIO_FullRemap_USART1 - USART1 Full Alternate Function mapping + * GPIO_PartialRemap1_USART2 - USART2 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_USART2 - USART2 Partial2 Alternate Function mapping + * GPIO_PartialRemap3_USART2 - USART2 Partial3 Alternate Function mapping + * GPIO_FullRemap_USART2 - USART2 Full Alternate Function mapping + * GPIO_PartialRemap1_USART3 - USART3 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_USART3 - USART3 Partial2 Alternate Function mapping + * GPIO_FullRemap_USART3 - USART3 Full Alternate Function mapping + * GPIO_PartialRemap1_USART4 - USART4 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_USART4 - USART4 Partial2 Alternate Function mapping + * GPIO_PartialRemap3_USART4 - USART4 Partial3 Alternate Function mapping + * GPIO_PartialRemap4_USART4 - USART4 Partial4 Alternate Function mapping + * GPIO_PartialRemap5_USART4 - USART4 Partial5 Alternate Function mapping + * GPIO_PartialRemap6_USART4 - USART4 Partial6 Alternate Function mapping + * GPIO_FullRemap_USART4 - USART4 Full Alternate Function mapping + * GPIO_PartialRemap1_TIM1 - TIM1 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_TIM1 - TIM1 Partial2 Alternate Function mapping + * GPIO_PartialRemap3_TIM1 - TIM1 Partial3 Alternate Function mapping + * GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping + * GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping + * GPIO_PartialRemap3_TIM2 - TIM2 Partial3 Alternate Function mapping + * GPIO_PartialRemap4_TIM2 - TIM2 Partial4 Alternate Function mapping + * GPIO_PartialRemap5_TIM2 - TIM2 Partial5 Alternate Function mapping + * GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping + * GPIO_PartialRemap1_TIM3 - TIM3 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_TIM3 - TIM3 Partial2 Alternate Function mapping + * GPIO_FullRemap_TIM3 - TIM3 Full Alternate Function mapping + * GPIO_Remap_PIOC - PIOC Alternate Function mapping + * GPIO_Remap_SWJ_Disable - SDI Disabled (SDI) + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) +{ + uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; + + tmpreg = AFIO->PCFR1; + + tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; + tmp = GPIO_Remap & LSB_MASK; + + /* Clear bit */ + if((GPIO_Remap & 0x08000000) == 0x08000000) /* 3bit */ + { + if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [26:24] SDI */ + { + tmpreg &= DBGAFR_SWJCFG_MASK; + AFIO->PCFR1 &= DBGAFR_SWJCFG_MASK; + } + else if((GPIO_Remap & DBGAFR_TIM1RP_MASK) == DBGAFR_TIM1RP_MASK) /* [31:16] 3bit */ + { + tmp1 = ((uint32_t)0x07) << 15; + tmpreg &= ~tmp1; + + if(NewState != DISABLE) + { + tmpreg |= (tmp << 15); + } + + AFIO->PCFR1 = tmpreg; + return; + } + else if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == DBGAFR_LOCATION_MASK) /* [31:16] 3bit */ + { + tmp1 = ((uint32_t)0x07) << (tmpmask + 0x10); + tmpreg &= ~tmp1; + } + else /* [15:0] 3bit */ + { + tmp1 = ((uint32_t)0x07) << tmpmask; + tmpreg &= ~tmp1; + } + } + else + { + if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [31:16] 2bit */ + { + tmp1 = ((uint32_t)0x03) << (tmpmask + 0x10); + tmpreg &= ~tmp1; + } + else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */ + { + tmp1 = ((uint32_t)0x03) << tmpmask; + tmpreg &= ~tmp1; + } + else /* [31:0] 1bit */ + { + tmpreg &= ~(tmp << (((GPIO_Remap & 0x00FFFFFF ) >> 0x15) * 0x10)); + } + } + + /* Set bit */ + if(NewState != DISABLE) + { + tmpreg |= (tmp << (((GPIO_Remap & 0x00FFFFFF )>> 0x15) * 0x10)); + } + + AFIO->PCFR1 = tmpreg; +} + +/********************************************************************* + * @fn GPIO_EXTILineConfig + * + * @brief Selects the GPIO pin used as EXTI Line. + * + * @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..C). + * GPIO_PinSource - specifies the EXTI line to be configured. + * This parameter can be GPIO_PinSourcex where x can be (0..23). + * + * @return none + */ +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint16_t GPIO_PinSource) +{ + uint32_t tmp = 0x00; + + tmp = ((uint32_t)0x03) << (0x02 * (GPIO_PinSource & (uint8_t)0x0F)); + AFIO->EXTICR[GPIO_PinSource >> 0x04] &= ~tmp; + AFIO->EXTICR[GPIO_PinSource >> 0x04] |= (((uint32_t)GPIO_PortSource) << (0x02 * (GPIO_PinSource & (uint8_t)0x0F))); +} + +/********************************************************************* + * @fn GPIO_IPD_Unused + * + * @brief Configure unused GPIO as input pull-up. + * + * @param none + * + * @return none + */ +void GPIO_IPD_Unused(void) +{ + GPIO_InitTypeDef GPIO_InitStructure = {0}; + uint32_t chip = 0; + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC, ENABLE); + chip = *( uint32_t * )0x1FFFF704 & (~0x000000F1); + switch(chip) + { + case 0x03510600: //CH32X035C8T6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14|GPIO_Pin_15\ + |GPIO_Pin_16|GPIO_Pin_17\ + |GPIO_Pin_18|GPIO_Pin_19\ + |GPIO_Pin_20|GPIO_Pin_21; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + break; + } + case 0x03560600: //CH32X035G8U6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_16|GPIO_Pin_15\ + |GPIO_Pin_17|GPIO_Pin_18\ + |GPIO_Pin_19|GPIO_Pin_20\ + |GPIO_Pin_21|GPIO_Pin_22\ + |GPIO_Pin_23|GPIO_Pin_14\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15\ + |GPIO_Pin_16|GPIO_Pin_17\ + |GPIO_Pin_18|GPIO_Pin_19\ + |GPIO_Pin_20|GPIO_Pin_21; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1|GPIO_Pin_2\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + break; + } + case 0x035B0600: //CH32X035G8R6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_16|GPIO_Pin_15\ + |GPIO_Pin_17|GPIO_Pin_18\ + |GPIO_Pin_19|GPIO_Pin_20\ + |GPIO_Pin_21|GPIO_Pin_22\ + |GPIO_Pin_23|GPIO_Pin_14\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15\ + |GPIO_Pin_16|GPIO_Pin_17\ + |GPIO_Pin_18|GPIO_Pin_19\ + |GPIO_Pin_20|GPIO_Pin_21; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2|GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + break; + } + case 0x035E0600: //CH32X035F8U6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_16|GPIO_Pin_15\ + |GPIO_Pin_17|GPIO_Pin_18\ + |GPIO_Pin_19|GPIO_Pin_20\ + |GPIO_Pin_21|GPIO_Pin_22|GPIO_Pin_23\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13|GPIO_Pin_14; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_9\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_10\ + |GPIO_Pin_16|GPIO_Pin_15\ + |GPIO_Pin_14|GPIO_Pin_13\ + |GPIO_Pin_17|GPIO_Pin_18\ + |GPIO_Pin_19|GPIO_Pin_20|GPIO_Pin_21; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + break; + } + case 0x03570600: //CH32X035F7P6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15\ + |GPIO_Pin_16|GPIO_Pin_17\ + |GPIO_Pin_18|GPIO_Pin_19\ + |GPIO_Pin_20|GPIO_Pin_21\ + |GPIO_Pin_22|GPIO_Pin_23; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_2\ + |GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_5|GPIO_Pin_6\ + |GPIO_Pin_7|GPIO_Pin_8\ + |GPIO_Pin_9|GPIO_Pin_10\ + |GPIO_Pin_11|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15\ + |GPIO_Pin_16|GPIO_Pin_17\ + |GPIO_Pin_18|GPIO_Pin_19\ + |GPIO_Pin_20|GPIO_Pin_21; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + break; + } + case 0x03117000: //CH32X033F8P6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_16|GPIO_Pin_15\ + |GPIO_Pin_17|GPIO_Pin_18\ + |GPIO_Pin_19|GPIO_Pin_20\ + |GPIO_Pin_21|GPIO_Pin_22|GPIO_Pin_23\ + |GPIO_Pin_8|GPIO_Pin_12\ + |GPIO_Pin_13|GPIO_Pin_14; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5|GPIO_Pin_6\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15\ + |GPIO_Pin_16|GPIO_Pin_17\ + |GPIO_Pin_18|GPIO_Pin_19\ + |GPIO_Pin_20|GPIO_Pin_21\ + |GPIO_Pin_22|GPIO_Pin_23; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15\ + |GPIO_Pin_20|GPIO_Pin_21\ + |GPIO_Pin_22|GPIO_Pin_23; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + break; + } + default: + { + break; + } + + } + +} + diff --git a/Code/DAP_X033/Peripheral/src/ch32x035_i2c.c b/Code/DAP_X033/Peripheral/src/ch32x035_i2c.c new file mode 100644 index 0000000..77e7dbb --- /dev/null +++ b/Code/DAP_X033/Peripheral/src/ch32x035_i2c.c @@ -0,0 +1,967 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_i2c.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file provides all the I2C firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_i2c.h" +#include "ch32x035_rcc.h" + +/* I2C SPE mask */ +#define CTLR1_PE_Set ((uint16_t)0x0001) +#define CTLR1_PE_Reset ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CTLR1_START_Set ((uint16_t)0x0100) +#define CTLR1_START_Reset ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CTLR1_STOP_Set ((uint16_t)0x0200) +#define CTLR1_STOP_Reset ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CTLR1_ACK_Set ((uint16_t)0x0400) +#define CTLR1_ACK_Reset ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CTLR1_ENGC_Set ((uint16_t)0x0040) +#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CTLR1_SWRST_Set ((uint16_t)0x8000) +#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CTLR1_PEC_Set ((uint16_t)0x1000) +#define CTLR1_PEC_Reset ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CTLR1_ENPEC_Set ((uint16_t)0x0020) +#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CTLR1_ENARP_Set ((uint16_t)0x0010) +#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080) +#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) + +/* I2C registers Masks */ +#define CTLR1_CLEAR_Mask ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CTLR2_DMAEN_Set ((uint16_t)0x0800) +#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CTLR2_LAST_Set ((uint16_t)0x1000) +#define CTLR2_LAST_Reset ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OADDR1_ADD0_Set ((uint16_t)0x0001) +#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OADDR2_ENDUAL_Set ((uint16_t)0x0001) +#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OADDR2_ADD2_Reset ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CKCFGR_FS_Set ((uint16_t)0x8000) + +/* I2C CCR mask */ +#define CKCFGR_CCR_Set ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +#define FLAG_Mask ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define ITEN_Mask ((uint32_t)0x07000000) + +/********************************************************************* + * @fn I2C_DeInit + * + * @brief Deinitializes the I2Cx peripheral registers to their default + * reset values. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * + * @return none + */ +void I2C_DeInit(I2C_TypeDef *I2Cx) +{ + if(I2Cx == I2C1) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); + } +} + +/********************************************************************* + * @fn I2C_Init + * + * @brief Initializes the I2Cx peripheral according to the specified + * parameters in the I2C_InitStruct. + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_InitStruct - pointer to a I2C_InitTypeDef structure that + * contains the configuration information for the specified I2C peripheral. + * + * @return none + */ +void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct) +{ + uint16_t tmpreg = 0, freqrange = 0; + uint16_t result = 0x04; + uint32_t pclk1 = 8000000; + + RCC_ClocksTypeDef rcc_clocks; + + tmpreg = I2Cx->CTLR2; + tmpreg &= CTLR2_FREQ_Reset; + RCC_GetClocksFreq(&rcc_clocks); + pclk1 = rcc_clocks.PCLK1_Frequency; + freqrange = (uint16_t)(pclk1 / 1000000); + tmpreg |= freqrange; + I2Cx->CTLR2 = tmpreg; + + I2Cx->CTLR1 &= CTLR1_PE_Reset; + tmpreg = 0; + + if(I2C_InitStruct->I2C_ClockSpeed <= 100000) + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); + + if(result < 0x04) + { + result = 0x04; + } + + tmpreg |= result; + } + else + { + if(I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); + } + else + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); + result |= I2C_DutyCycle_16_9; + } + + if((result & CKCFGR_CCR_Set) == 0) + { + result |= (uint16_t)0x0001; + } + + tmpreg |= (uint16_t)(result | CKCFGR_FS_Set); + } + + I2Cx->CKCFGR = tmpreg; + I2Cx->CTLR1 |= CTLR1_PE_Set; + + tmpreg = I2Cx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); + I2Cx->CTLR1 = tmpreg; + + I2Cx->OADDR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); +} + +/********************************************************************* + * @fn I2C_StructInit + * + * @brief Fills each I2C_InitStruct member with its default value. + * + * @param I2C_InitStruct - pointer to an I2C_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct) +{ + I2C_InitStruct->I2C_ClockSpeed = 5000; + I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; + I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; + I2C_InitStruct->I2C_OwnAddress1 = 0; + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; + I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +} + +/********************************************************************* + * @fn I2C_Cmd + * + * @brief Enables or disables the specified I2C peripheral. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_PE_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_PE_Reset; + } +} + +/********************************************************************* + * @fn I2C_DMACmd + * + * @brief Enables or disables the specified I2C DMA requests. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= CTLR2_DMAEN_Set; + } + else + { + I2Cx->CTLR2 &= CTLR2_DMAEN_Reset; + } +} + +/********************************************************************* + * @fn I2C_DMALastTransferCmd + * + * @brief Specifies if the next DMA transfer will be the last one. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= CTLR2_LAST_Set; + } + else + { + I2Cx->CTLR2 &= CTLR2_LAST_Reset; + } +} + +/********************************************************************* + * @fn I2C_GenerateSTART + * + * @brief Generates I2Cx communication START condition. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_START_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_START_Reset; + } +} + +/********************************************************************* + * @fn I2C_GenerateSTOP + * + * @brief Generates I2Cx communication STOP condition. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_STOP_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_STOP_Reset; + } +} + +/********************************************************************* + * @fn I2C_AcknowledgeConfig + * + * @brief Enables or disables the specified I2C acknowledge feature. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ACK_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ACK_Reset; + } +} + +/********************************************************************* + * @fn I2C_OwnAddress2Config + * + * @brief Configures the specified I2C own address2. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * Address - specifies the 7bit I2C own address2. + * + * @return none + */ +void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address) +{ + uint16_t tmpreg = 0; + + tmpreg = I2Cx->OADDR2; + tmpreg &= OADDR2_ADD2_Reset; + tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); + I2Cx->OADDR2 = tmpreg; +} + +/********************************************************************* + * @fn I2C_DualAddressCmd + * + * @brief Enables or disables the specified I2C dual addressing mode. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->OADDR2 |= OADDR2_ENDUAL_Set; + } + else + { + I2Cx->OADDR2 &= OADDR2_ENDUAL_Reset; + } +} + +/********************************************************************* + * @fn I2C_GeneralCallCmd + * + * @brief Enables or disables the specified I2C general call feature. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENGC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENGC_Reset; + } +} + +/********************************************************************* + * @fn I2C_ITConfig + * + * @brief Enables or disables the specified I2C interrupts. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_IT - specifies the I2C interrupts sources to be enabled or disabled. + * I2C_IT_BUF - Buffer interrupt mask. + * I2C_IT_EVT - Event interrupt mask. + * I2C_IT_ERR - Error interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= I2C_IT; + } + else + { + I2Cx->CTLR2 &= (uint16_t)~I2C_IT; + } +} + +/********************************************************************* + * @fn I2C_SendData + * + * @brief Sends a data byte through the I2Cx peripheral. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * Data - Byte to be transmitted. + * + * @return none + */ +void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data) +{ + I2Cx->DATAR = Data; +} + +/********************************************************************* + * @fn I2C_ReceiveData + * + * @brief Returns the most recent received data by the I2Cx peripheral. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * + * @return The value of the received data. + */ +uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx) +{ + return (uint8_t)I2Cx->DATAR; +} + +/********************************************************************* + * @fn I2C_Send7bitAddress + * + * @brief Transmits the address byte to select the slave device. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * Address - specifies the slave address which will be transmitted. + * I2C_Direction - specifies whether the I2C device will be a + * Transmitter or a Receiver. + * I2C_Direction_Transmitter - Transmitter mode. + * I2C_Direction_Receiver - Receiver mode. + * + * @return none + */ +void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + if(I2C_Direction != I2C_Direction_Transmitter) + { + Address |= OADDR1_ADD0_Set; + } + else + { + Address &= OADDR1_ADD0_Reset; + } + + I2Cx->DATAR = Address; +} + +/********************************************************************* + * @fn I2C_ReadRegister + * + * @brief Reads the specified I2C register and returns its value. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_Register - specifies the register to read. + * I2C_Register_CTLR1. + * I2C_Register_CTLR2. + * I2C_Register_OADDR1. + * I2C_Register_OADDR2. + * I2C_Register_DATAR. + * I2C_Register_STAR1. + * I2C_Register_STAR2. + * I2C_Register_CKCFGR. + * I2C_Register_RTR. + * + * @return none + */ +uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)I2Cx; + tmp += I2C_Register; + + return (*(__IO uint16_t *)tmp); +} + +/********************************************************************* + * @fn I2C_SoftwareResetCmd + * + * @brief Enables or disables the specified I2C software reset. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_SWRST_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_SWRST_Reset; + } +} + +/********************************************************************* + * @fn I2C_NACKPositionConfig + * + * @brief Selects the specified I2C NACK position in master receiver mode. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_NACKPosition - specifies the NACK position. + * I2C_NACKPosition_Next - indicates that the next byte will be + * the last received byte. + * I2C_NACKPosition_Current - indicates that current byte is the + * last received byte. + * Note- + * This function configures the same bit (POS) as I2C_PECPositionConfig() + * but is intended to be used in I2C mode while I2C_PECPositionConfig() + * is intended to used in SMBUS mode. + * @return none + */ +void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition) +{ + if(I2C_NACKPosition == I2C_NACKPosition_Next) + { + I2Cx->CTLR1 |= I2C_NACKPosition_Next; + } + else + { + I2Cx->CTLR1 &= I2C_NACKPosition_Current; + } +} + +/********************************************************************* + * @fn I2C_TransmitPEC + * + * @brief Enables or disables the specified I2C PEC transfer. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_PEC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_PEC_Reset; + } +} + +/********************************************************************* + * @fn I2C_PECPositionConfig + * + * @brief Selects the specified I2C PEC position. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_PECPosition - specifies the PEC position. + * I2C_PECPosition_Next - indicates that the next byte is PEC. + * I2C_PECPosition_Current - indicates that current byte is PEC. + * + * @return none + */ +void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition) +{ + if(I2C_PECPosition == I2C_PECPosition_Next) + { + I2Cx->CTLR1 |= I2C_PECPosition_Next; + } + else + { + I2Cx->CTLR1 &= I2C_PECPosition_Current; + } +} + +/********************************************************************* + * @fn I2C_CalculatePEC + * + * @brief Enables or disables the PEC value calculation of the transferred bytes. + * + * @param I2Cx- where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENPEC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENPEC_Reset; + } +} + +/********************************************************************* + * @fn I2C_GetPEC + * + * @brief Returns the PEC value for the specified I2C. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * + * @return The PEC value. + */ +uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx) +{ + return ((I2Cx->STAR2) >> 8); +} + +/********************************************************************* + * @fn I2C_ARPCmd + * + * @brief Enables or disables the specified I2C ARP. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return The PEC value. + */ +void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENARP_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENARP_Reset; + } +} + +/********************************************************************* + * @fn I2C_StretchClockCmd + * + * @brief Enables or disables the specified I2C Clock stretching. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState == DISABLE) + { + I2Cx->CTLR1 |= CTLR1_NOSTRETCH_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_NOSTRETCH_Reset; + } +} + +/********************************************************************* + * @fn I2C_FastModeDutyCycleConfig + * + * @brief Selects the specified I2C fast mode duty cycle. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_DutyCycle - specifies the fast mode duty cycle. + * I2C_DutyCycle_2 - I2C fast mode Tlow/Thigh = 2. + * I2C_DutyCycle_16_9 - I2C fast mode Tlow/Thigh = 16/9. + * + * @return none + */ +void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle) +{ + if(I2C_DutyCycle != I2C_DutyCycle_16_9) + { + I2Cx->CKCFGR &= I2C_DutyCycle_2; + } + else + { + I2Cx->CKCFGR |= I2C_DutyCycle_16_9; + } +} + +/********************************************************************* + * @fn I2C_CheckEvent + * + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * + * @param I2Cx- where x can be 1 to select the I2C peripheral. + * I2C_EVENT: specifies the event to be checked. + * I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_BYTE_RECEIVED - EVT2. + * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) - EVT2. + * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) - EVT2. + * I2C_EVENT_SLAVE_BYTE_TRANSMITTED - EVT3. + * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) - EVT3. + * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) - EVT3. + * I2C_EVENT_SLAVE_ACK_FAILURE - EVT3_2. + * I2C_EVENT_SLAVE_STOP_DETECTED - EVT4. + * I2C_EVENT_MASTER_MODE_SELECT - EVT5. + * I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - EVT6. + * I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - EVT6. + * I2C_EVENT_MASTER_BYTE_RECEIVED - EVT7. + * I2C_EVENT_MASTER_BYTE_TRANSMITTING - EVT8. + * I2C_EVENT_MASTER_BYTE_TRANSMITTED - EVT8_2. + * I2C_EVENT_MASTER_MODE_ADDRESS10 - EVT9. + * + * @return ErrorStatus - READY or NoREADY. + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + ErrorStatus status = NoREADY; + + flag1 = I2Cx->STAR1; + flag2 = I2Cx->STAR2; + flag2 = flag2 << 16; + + lastevent = (flag1 | flag2) & FLAG_Mask; + + if((lastevent & I2C_EVENT) == I2C_EVENT) + { + status = READY; + } + else + { + status = NoREADY; + } + + return status; +} + +/********************************************************************* + * @fn I2C_GetLastEvent + * + * @brief Returns the last I2Cx Event. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * + * @return none + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + flag1 = I2Cx->STAR1; + flag2 = I2Cx->STAR2; + flag2 = flag2 << 16; + lastevent = (flag1 | flag2) & FLAG_Mask; + + return lastevent; +} + +/********************************************************************* + * @fn I2C_GetFlagStatus + * + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_FLAG - specifies the flag to check. + * I2C_FLAG_DUALF - Dual flag (Slave mode). + * I2C_FLAG_GENCALL - General call header flag (Slave mode). + * I2C_FLAG_TRA - Transmitter/Receiver flag. + * I2C_FLAG_BUSY - Bus busy flag. + * I2C_FLAG_MSL - Master/Slave flag. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * I2C_FLAG_TXE - Data register empty flag (Transmitter). + * I2C_FLAG_RXNE- Data register not empty (Receiver) flag. + * I2C_FLAG_STOPF - Stop detection flag (Slave mode). + * I2C_FLAG_ADD10 - 10-bit header sent flag (Master mode). + * I2C_FLAG_BTF - Byte transfer finished flag. + * I2C_FLAG_ADDR - Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDA". + * I2C_FLAG_SB - Start bit flag (Master mode). + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + __IO uint32_t i2creg = 0, i2cxbase = 0; + + i2cxbase = (uint32_t)I2Cx; + i2creg = I2C_FLAG >> 28; + I2C_FLAG &= FLAG_Mask; + + if(i2creg != 0) + { + i2cxbase += 0x14; + } + else + { + I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); + i2cxbase += 0x18; + } + + if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn I2C_ClearFlag + * + * @brief Clears the I2Cx's pending flags. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_FLAG - specifies the flag to clear. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * Note- + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_STAR1 register (I2C_GetFlagStatus()) followed by a write operation + * to I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_SATR1 (I2C_GetFlagStatus()) followed by writing the + * second byte of the address in DATAR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_SATR1 register (I2C_GetFlagStatus()) followed by a + * read/write to I2C_DATAR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_SATR1 register (I2C_GetFlagStatus()) followed by a read operation to + * I2C_SATR2 register ((void)(I2Cx->SR2)). + * - SB (Start Bit) is cleared software sequence: a read operation to I2C_STAR1 + * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DATAR + * register (I2C_SendData()). + * @return none + */ +void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + uint32_t flagpos = 0; + + flagpos = I2C_FLAG & FLAG_Mask; + I2Cx->STAR1 = (uint16_t)~flagpos; +} + +/********************************************************************* + * @fn I2C_GetITStatus + * + * @brief Checks whether the specified I2C interrupt has occurred or not. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * II2C_IT - specifies the interrupt source to check. + * I2C_IT_PECERR - PEC error in reception flag. + * I2C_IT_OVR - Overrun/Underrun flag (Slave mode). + * I2C_IT_AF - Acknowledge failure flag. + * I2C_IT_ARLO - Arbitration lost flag (Master mode). + * I2C_IT_BERR - Bus error flag. + * I2C_IT_TXE - Data register empty flag (Transmitter). + * I2C_IT_RXNE - Data register not empty (Receiver) flag. + * I2C_IT_STOPF - Stop detection flag (Slave mode). + * I2C_IT_ADD10 - 10-bit header sent flag (Master mode). + * I2C_IT_BTF - Byte transfer finished flag. + * I2C_IT_ADDR - Address sent flag (Master mode) "ADSL" Address matched + * flag (Slave mode)"ENDAD". + * I2C_IT_SB - Start bit flag (Master mode). + * + * @return none + */ +ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CTLR2)); + I2C_IT &= FLAG_Mask; + + if(((I2Cx->STAR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn I2C_ClearITPendingBit + * + * @brief Clears the I2Cx interrupt pending bits. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_IT - specifies the interrupt pending bit to clear. + * I2C_IT_PECERR - PEC error in reception interrupt. + * I2C_IT_OVR - Overrun/Underrun interrupt (Slave mode). + * I2C_IT_AF - Acknowledge failure interrupt. + * I2C_IT_ARLO - Arbitration lost interrupt (Master mode). + * I2C_IT_BERR - Bus error interrupt. + * Note- + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_STAR1 (I2C_GetITStatus()) followed by writing the second + * byte of the address in I2C_DATAR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_STAR1 register (I2C_GetITStatus()) followed by a + * read/write to I2C_DATAR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_STAR1 register (I2C_GetITStatus()) followed by a read operation to + * I2C_STAR2 register ((void)(I2Cx->SR2)). + * - SB (Start Bit) is cleared by software sequence: a read operation to + * I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_DATAR register (I2C_SendData()). + * + * @return none + */ +void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT) +{ + uint32_t flagpos = 0; + + flagpos = I2C_IT & FLAG_Mask; + I2Cx->STAR1 = (uint16_t)~flagpos; +} diff --git a/Code/DAP_X033/Peripheral/src/ch32x035_iwdg.c b/Code/DAP_X033/Peripheral/src/ch32x035_iwdg.c new file mode 100644 index 0000000..b519a12 --- /dev/null +++ b/Code/DAP_X033/Peripheral/src/ch32x035_iwdg.c @@ -0,0 +1,122 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_iwdg.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file provides all the IWDG firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_iwdg.h" + +/* CTLR register bit mask */ +#define CTLR_KEY_Reload ((uint16_t)0xAAAA) +#define CTLR_KEY_Enable ((uint16_t)0xCCCC) + +/********************************************************************* + * @fn IWDG_WriteAccessCmd + * + * @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers. + * + * @param WDG_WriteAccess - new state of write access to IWDG_PSCR and + * IWDG_RLDR registers. + * IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and + * IWDG_RLDR registers. + * IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR + * and IWDG_RLDR registers. + * + * @return none + */ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) +{ + IWDG->CTLR = IWDG_WriteAccess; +} + +/********************************************************************* + * @fn IWDG_SetPrescaler + * + * @brief Sets IWDG Prescaler value. + * + * @param IWDG_Prescaler - specifies the IWDG Prescaler value. + * IWDG_Prescaler_4 - IWDG prescaler set to 4. + * IWDG_Prescaler_8 - IWDG prescaler set to 8. + * IWDG_Prescaler_16 - IWDG prescaler set to 16. + * IWDG_Prescaler_32 - IWDG prescaler set to 32. + * IWDG_Prescaler_64 - IWDG prescaler set to 64. + * IWDG_Prescaler_128 - IWDG prescaler set to 128. + * IWDG_Prescaler_256 - IWDG prescaler set to 256. + * + * @return none + */ +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) +{ + IWDG->PSCR = IWDG_Prescaler; +} + +/********************************************************************* + * @fn IWDG_SetReload + * + * @brief Sets IWDG Reload value. + * + * @param Reload - specifies the IWDG Reload value. + * This parameter must be a number between 0 and 0x0FFF. + * + * @return none + */ +void IWDG_SetReload(uint16_t Reload) +{ + IWDG->RLDR = Reload; +} + +/********************************************************************* + * @fn IWDG_ReloadCounter + * + * @brief Reloads IWDG counter with value defined in the reload register. + * + * @return none + */ +void IWDG_ReloadCounter(void) +{ + IWDG->CTLR = CTLR_KEY_Reload; +} + +/********************************************************************* + * @fn IWDG_Enable + * + * @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled). + * + * @return none + */ +void IWDG_Enable(void) +{ + IWDG->CTLR = CTLR_KEY_Enable; +} + +/********************************************************************* + * @fn IWDG_GetFlagStatus + * + * @brief Checks whether the specified IWDG flag is set or not. + * + * @param IWDG_FLAG - specifies the flag to check. + * IWDG_FLAG_PVU - Prescaler Value Update on going. + * IWDG_FLAG_RVU - Reload Value Update on going. + * + * @return none + */ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} diff --git a/Code/DAP_X033/Peripheral/src/ch32x035_misc.c b/Code/DAP_X033/Peripheral/src/ch32x035_misc.c new file mode 100644 index 0000000..bb5330b --- /dev/null +++ b/Code/DAP_X033/Peripheral/src/ch32x035_misc.c @@ -0,0 +1,109 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_misc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file provides all the miscellaneous firmware functions . +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_misc.h" + +__IO uint32_t NVIC_Priority_Group = 0; + +/********************************************************************* + * @fn NVIC_PriorityGroupConfig + * + * @brief Configures the priority grouping - pre-emption priority and subpriority. + * + * @param NVIC_PriorityGroup - specifies the priority grouping bits length. + * NVIC_PriorityGroup_0 - 0 bits for pre-emption priority + * 4 bits for subpriority + * NVIC_PriorityGroup_1 - 1 bits for pre-emption priority + * 3 bits for subpriority + * NVIC_PriorityGroup_2 - 2 bits for pre-emption priority + * 2 bits for subpriority + * NVIC_PriorityGroup_3 - 3 bits for pre-emption priority + * 1 bits for subpriority + * NVIC_PriorityGroup_4 - 4 bits for pre-emption priority + * 0 bits for subpriority + * + * @return none + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + NVIC_Priority_Group = NVIC_PriorityGroup; +} + +/********************************************************************* + * @fn NVIC_Init + * + * @brief Initializes the NVIC peripheral according to the specified parameters in + * the NVIC_InitStruct. + * + * @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the + * configuration information for the specified NVIC peripheral. + * + * @return none + */ +void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct) +{ + uint8_t tmppre = 0; + + if(NVIC_Priority_Group == NVIC_PriorityGroup_0) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4); + } + else if(NVIC_Priority_Group == NVIC_PriorityGroup_1) + { + if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4)); + } + else + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4)); + } + } + else if(NVIC_Priority_Group == NVIC_PriorityGroup_2) + { + if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 1) + { + tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority); + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4)); + } + else + { + tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 2)); + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4)); + } + } + else if(NVIC_Priority_Group == NVIC_PriorityGroup_3) + { + if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 3) + { + tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority); + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4)); + } + else + { + tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 4)); + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4)); + } + } + else if(NVIC_Priority_Group == NVIC_PriorityGroup_4) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 4); + } + + if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel); + } + else + { + NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel); + } +} diff --git a/Code/DAP_X033/Peripheral/src/ch32x035_opa.c b/Code/DAP_X033/Peripheral/src/ch32x035_opa.c new file mode 100644 index 0000000..ef6804f --- /dev/null +++ b/Code/DAP_X033/Peripheral/src/ch32x035_opa.c @@ -0,0 +1,320 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_opa.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file provides all the OPA firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_opa.h" + + +/* FLASH Keys */ +#define OPA_KEY1 ((uint32_t)0x45670123) +#define OPA_KEY2 ((uint32_t)0xCDEF89AB) + +volatile uint32_t CTLR2_tmp = 0; + +/******************************************************************************** + * @fn OPA_Unlock + * + * @brief Unlocks the OPA Controller. + * + * @return None + */ +void OPA_Unlock(void) +{ + OPA->OPAKEY = OPA_KEY1; + OPA->OPAKEY = OPA_KEY2; +} + +/******************************************************************************** + * @fn OPA_Lock + * + * @brief Locks the OPA Controller. + * + * @return None + */ +void OPA_Lock(void) +{ + OPA->CTLR1 |= (1<<31); +} + +/******************************************************************************** + * @fn OPA_POLL_Unlock + * + * @brief Unlocks the OPA POLL Controller. + * + * @return None + */ +void OPA_POLL_Unlock(void) +{ + OPA->POLLKEY = OPA_KEY1; + OPA->POLLKEY = OPA_KEY2; +} + +/******************************************************************************** + * @fn OPA_POLL_Lock + * + * @brief Locks the OPA POLL Controller. + * + * @return None + */ +void OPA_POLL_Lock(void) +{ + OPA->CFGR1 |= (1<<7); +} + +/******************************************************************************** + * @fn OPA_CMP_Unlock + * + * @brief Unlocks the CMP Controller. + * + * @return None + */ +void OPA_CMP_Unlock(void) +{ + OPA->CMPKEY = OPA_KEY1; + OPA->CMPKEY = OPA_KEY2; +} + +/******************************************************************************** + * @fn OPA_CMP_Lock + * + * @brief Locks the CMP Controller. + * + * @return None + */ +void OPA_CMP_Lock(void) +{ + CTLR2_tmp |= (1<<31); + OPA->CTLR2 = CTLR2_tmp; + CTLR2_tmp &= ~(1<<31); +} + +/********************************************************************* + * @fn OPA_Init + * + * @brief Initializes the OPA peripheral according to the specified + * parameters in the OPA_InitStruct. + * + * @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure + * + * @return none + */ +void OPA_Init(OPA_InitTypeDef *OPA_InitStruct) +{ + uint16_t tmp0 = 0, tmp1 = 0; + uint32_t tmp2 = 0; + + tmp0 = OPA->CFGR1; + tmp1 = OPA->CFGR2; + tmp2 = OPA->CTLR1; + + if(OPA_InitStruct->OPA_NUM == OPA1) + { + tmp1 &= 0xFCFF; + tmp2 &= 0xFFFF0001; + + tmp1 |= (OPA_InitStruct->POLL_NUM << 9); + tmp2 |= (OPA_InitStruct->Mode << 1) | (OPA_InitStruct->PSEL << 3) + | (OPA_InitStruct->FB << 5) | (OPA_InitStruct->NSEL << 6); + } + else if(OPA_InitStruct->OPA_NUM == OPA2) + { + tmp1 &= 0xF3FF; + tmp2 &= 0x0001FFFF; + + tmp1 |= (OPA_InitStruct->POLL_NUM << 11); + tmp2 |= (OPA_InitStruct->Mode << 17) | (OPA_InitStruct->PSEL << 19) + | (OPA_InitStruct->FB << 21) | (OPA_InitStruct->NSEL << 22); + } + + tmp0 |= (OPA_InitStruct->PSEL_POLL) | (OPA_InitStruct->BKIN_EN << 2) + | (OPA_InitStruct->RST_EN << 4) | (OPA_InitStruct->BKIN_SEL << 6) + | (OPA_InitStruct->OUT_IE << 8) | (OPA_InitStruct->CNT_IE << 10) + | (OPA_InitStruct->NMI_IE << 11); + tmp1 &= 0xFF00; + tmp1 |= OPA_InitStruct->OPA_POLL_Interval; + + OPA->CFGR1 = tmp0; + OPA->CFGR2 = tmp1; + OPA->CTLR1 = tmp2; +} + +/********************************************************************* + * @fn OPA_StructInit + * + * @brief Fills each OPA_StructInit member with its reset value. + * + * @param OPA_StructInit - pointer to a OPA_InitTypeDef structure + * + * @return none + */ +void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct) +{ + OPA_InitStruct->OPA_POLL_Interval = 0; + OPA_InitStruct->OPA_NUM = OPA1; + OPA_InitStruct->Mode = OUT_IO_OUT0; + OPA_InitStruct->PSEL = CHP0; + OPA_InitStruct->FB = FB_OFF; + OPA_InitStruct->NSEL = CHN0; + OPA_InitStruct->PSEL_POLL = CHP_OPA1_OFF_OPA2_OFF; + OPA_InitStruct->BKIN_EN = BKIN_OPA1_OFF_OPA2_OFF; + OPA_InitStruct->RST_EN = RST_OPA1_OFF_OPA2_OFF; + OPA_InitStruct->BKIN_SEL = BKIN_OPA1_TIM1_OPA2_TIM2; + OPA_InitStruct->OUT_IE = OUT_IE_OPA1_OFF_OPA2_OFF; + OPA_InitStruct->CNT_IE = CNT_IE_OFF; + OPA_InitStruct->NMI_IE = NMI_IE_OFF; + OPA_InitStruct->POLL_NUM = CHP_POLL_NUM_1; +} + +/********************************************************************* + * @fn OPA_Cmd + * + * @brief Enables or disables the specified OPA peripheral. + * + * @param OPA_NUM - Select OPA + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + OPA->CTLR1 |= (uint32_t)(1 << (OPA_NUM*16)); + } + else + { + OPA->CTLR1 &= ~(uint32_t)(1 << (OPA_NUM*16)); + } +} + +/********************************************************************* + * @fn OPA_CMP_Init + * + * @brief Initializes the CMP peripheral according to the specified + * parameters in the CMP_InitTypeDef. + * + * @param CMP_InitStruct - pointer to a CMP_InitTypeDef structure + * + * @return none + */ +void OPA_CMP_Init(CMP_InitTypeDef *CMP_InitStruct) +{ + uint32_t tmp1 = 0; + + tmp1 = CTLR2_tmp; + + if(CMP_InitStruct->CMP_NUM == CMP1) + { + tmp1 &= 0xFFFFFFE1; + tmp1 |= (CMP_InitStruct->Mode << 1) | (CMP_InitStruct->NSEL << 2) + | (CMP_InitStruct->PSEL << 3) | (CMP_InitStruct->HYEN << 4); + } + else if(CMP_InitStruct->CMP_NUM == CMP2) + { + tmp1 &= 0xFFFFFC3F; + tmp1 |= (CMP_InitStruct->Mode << 6) | (CMP_InitStruct->NSEL << 7) + | (CMP_InitStruct->PSEL << 8) | (CMP_InitStruct->HYEN << 9); + } + else if(CMP_InitStruct->CMP_NUM == CMP3) + { + tmp1 &= 0xFFFF87FF; + tmp1 |= (CMP_InitStruct->Mode << 11) | (CMP_InitStruct->NSEL << 12) + | (CMP_InitStruct->PSEL << 13) | (CMP_InitStruct->HYEN << 14); + } + + CTLR2_tmp = tmp1; + OPA->CTLR2 = tmp1; +} + +/********************************************************************* + * @fn OPA_CMP_StructInit + * + * @brief Fills each OPA_CMP_StructInit member with its reset value. + * + * @param CMP_StructInit - pointer to a OPA_CMP_StructInit structure + * + * @return none + */ +void OPA_CMP_StructInit(CMP_InitTypeDef *CMP_InitStruct) +{ + CMP_InitStruct->CMP_NUM = CMP1; + CMP_InitStruct->Mode = OUT_IO_TIM2; + CMP_InitStruct->NSEL = CMP_CHN0; + CMP_InitStruct->PSEL = CMP_CHP1; + CMP_InitStruct->HYEN = CMP_HYEN1; +} + +/********************************************************************* + * @fn OPA_CMP_Cmd + * + * @brief Enables or disables the specified CMP peripheral. + * + * @param CMP_NUM - Select CMP + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void OPA_CMP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + CTLR2_tmp |= (uint32_t)(1 << (CMP_NUM*5)); + } + else + { + CTLR2_tmp &= ~(uint32_t)(1 << (CMP_NUM*5)); + } + + OPA->CTLR2 = CTLR2_tmp; +} + +/********************************************************************* + * @fn OPA_GetFlagStatus + * + * @brief Checks whether the OPA flag is set or not. + * + * @param OPA_FLAG - specifies the SPI/I2S flag to check. + * OPA_FLAG_OUT_OPA1 - OPA1 out flag + * OPA_FLAG_OUT_OPA2 - OPA2 out flag + * OPA_FLAG_OUT_CNT - OPA out flag rising edge of sampling data + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus OPA_GetFlagStatus(uint16_t OPA_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((OPA->CFGR1 & OPA_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn OPA_ClearFlag + * + * @brief Clears the OPA flag. + * + * @param OPA_FLAG - specifies the OPA flag to clear. + * OPA_FLAG_OUT_OPA1 - OPA1 out flag + * OPA_FLAG_OUT_OPA2 - OPA2 out flag + * OPA_FLAG_OUT_CNT - OPA out flag rising edge of sampling data + * @return none + */ +void OPA_ClearFlag(uint16_t OPA_FLAG) +{ + OPA->CFGR1 &= (uint16_t)~OPA_FLAG; +} diff --git a/Code/DAP_X033/Peripheral/src/ch32x035_pwr.c b/Code/DAP_X033/Peripheral/src/ch32x035_pwr.c new file mode 100644 index 0000000..b12921b --- /dev/null +++ b/Code/DAP_X033/Peripheral/src/ch32x035_pwr.c @@ -0,0 +1,156 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_pwr.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file provides all the PWR firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_pwr.h" +#include "ch32x035_rcc.h" + +/* PWR registers bit mask */ +/* CTLR register bit mask */ +#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFD) +#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF9F) + +/********************************************************************* + * @fn PWR_DeInit + * + * @brief Deinitializes the PWR peripheral registers to their default + * reset values. + * + * @return none + */ +void PWR_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); +} + +/********************************************************************* + * @fn PWR_PVDLevelConfig + * + * @brief Configures the voltage threshold detected by the Power Voltage + * Detector(PVD). + * + * @param PWR_PVDLevel - specifies the PVD detection level + * PWR_PVDLevel_2V1 - PVD detection level set to 2.1V + * PWR_PVDLevel_2V3 - PVD detection level set to 2.3V + * PWR_PVDLevel_3V0 - PVD detection level set to 3.0V + * PWR_PVDLevel_4V0 - PVD detection level set to 4.0V + * + * @return none + */ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + tmpreg &= CTLR_PLS_MASK; + tmpreg |= PWR_PVDLevel; + PWR->CTLR = tmpreg; +} + +/********************************************************************* + * @fn PWR_EnterSTOPMode + * + * @brief Enters STOP mode. + * + * @param PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction. + * PWR_STOPEntry_WFI - enter STOP mode with WFI instruction + * PWR_STOPEntry_WFE - enter STOP mode with WFE instruction + * + * @return none + */ +void PWR_EnterSTOPMode(uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + tmpreg &= CTLR_DS_MASK; + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + __WFI(); + } + else + { + __WFE(); + } + + NVIC->SCTLR &= ~(1 << 2); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode + * + * @brief Enters STANDBY mode. + * + * @return none + */ +void PWR_EnterSTANDBYMode(void) +{ + PWR->CTLR |= PWR_CTLR_PDDS; + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_GetFlagStatus + * + * @brief Checks whether the specified PWR flag is set or not. + * + * @param PWR_FLAG - specifies the flag to check. + * PWR_FLAG_PVDO - PVD Output + * PWR_FLAG_FLASH - Flash low power flag + * + * @return The new state of PWR_FLAG (SET or RESET). + */ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn PWR_VDD_SupplyVoltage + * + * @brief Checks VDD Supply Voltage. + * + * @param none + * + * @return PWR_VDD - VDD Supply Voltage. + * PWR_VDD_5V - VDD = 5V + * PWR_VDD_3V3 - VDD = 3.3V + */ +PWR_VDD PWR_VDD_SupplyVoltage(void) +{ + PWR_VDD VDD_Voltage = PWR_VDD_3V3; + RCC_APB1PeriphClockCmd( RCC_APB1Periph_PWR, ENABLE); + PWR_PVDLevelConfig(PWR_PVDLevel_4V0); + for(volatile uint32_t i = 0;i < SystemCoreClock/100000;i++)//delay 10us + __NOP(); + if( PWR_GetFlagStatus(PWR_FLAG_PVDO) == (uint32_t)RESET) + { + VDD_Voltage = PWR_VDD_5V; + } + PWR_PVDLevelConfig(PWR_PVDLevel_2V1); + + return VDD_Voltage; +} + diff --git a/Code/DAP_X033/Peripheral/src/ch32x035_rcc.c b/Code/DAP_X033/Peripheral/src/ch32x035_rcc.c new file mode 100644 index 0000000..565d2a6 --- /dev/null +++ b/Code/DAP_X033/Peripheral/src/ch32x035_rcc.c @@ -0,0 +1,411 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_rcc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file provides all the RCC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_rcc.h" + +/* RCC registers bit mask */ + +/* CTLR register bit mask */ +#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) + +/* CFGR0 register bit mask */ +#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) +#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) + +/* RSTSCKR register bit mask */ +#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) + +/* RCC Flag Mask */ +#define FLAG_Mask ((uint8_t)0x1F) + +/* CFGR0 register byte 4 (Bits[31:24]) base address */ +#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007) + + +static __I uint8_t APBAHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8}; + +/********************************************************************* + * @fn RCC_DeInit + * + * @brief Resets the RCC clock configuration to the default reset state. + * Note- + * HSE can not be stopped if it is used directly or through the PLL as system clock. + * @return none + */ +void RCC_DeInit(void) +{ + RCC->CTLR |= (uint32_t)0x00000001; + RCC->CFGR0 |= (uint32_t)0x00000050; + RCC->CFGR0 &= (uint32_t)0xF8FFFF5F; +} + +/********************************************************************* + * @fn RCC_AdjustHSICalibrationValue + * + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * + * @param HSICalibrationValue - specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * + * @return none + */ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CTLR; + tmpreg &= CTLR_HSITRIM_Mask; + tmpreg |= (uint32_t)HSICalibrationValue << 3; + RCC->CTLR = tmpreg; +} + +/********************************************************************* + * @fn RCC_HSICmd + * + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_HSICmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1<<0); + } + else{ + RCC->CTLR &= ~(1<<0); + } +} + +/********************************************************************* + * @fn RCC_HCLKConfig + * + * @brief Configures the AHB clock (HCLK). + * + * @param RCC_SYSCLK - defines the AHB clock divider. This clock is derived from + * the system clock (SYSCLK). + * RCC_SYSCLK_Div1 - AHB clock = SYSCLK. + * RCC_SYSCLK_Div2 - AHB clock = SYSCLK/2. + * RCC_SYSCLK_Div3 - AHB clock = SYSCLK/3. + * RCC_SYSCLK_Div4 - AHB clock = SYSCLK/4. + * RCC_SYSCLK_Div5 - AHB clock = SYSCLK/5. + * RCC_SYSCLK_Div6 - AHB clock = SYSCLK/6. + * RCC_SYSCLK_Div7 - AHB clock = SYSCLK/7. + * RCC_SYSCLK_Div8 - AHB clock = SYSCLK/8. + * RCC_SYSCLK_Div16 - AHB clock = SYSCLK/16. + * RCC_SYSCLK_Div32 - AHB clock = SYSCLK/32. + * RCC_SYSCLK_Div64 - AHB clock = SYSCLK/64. + * RCC_SYSCLK_Div128 - AHB clock = SYSCLK/128. + * RCC_SYSCLK_Div256 - AHB clock = SYSCLK/256. + * + * @return none + */ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_HPRE_Reset_Mask; + tmpreg |= RCC_SYSCLK; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_GetClocksFreq + * + * @brief The result of this function could be not correct when using + * fractional value for HSE crystal. + * + * @param RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold + * the clocks frequencies. + * + * @return none + */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) +{ + uint32_t tmp = 0, presc = 0; + + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + + tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask; + tmp = tmp >> 4; + presc = APBAHBPrescTable[tmp]; + + if(((RCC->CFGR0 & CFGR0_HPRE_Set_Mask) >> 4) < 8) + { + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency / presc; + } + else + { + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + } + + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency; + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency; +} + +/********************************************************************* + * @fn RCC_AHBPeriphClockCmd + * + * @brief Enables or disables the AHB peripheral clock. + * + * @param RCC_AHBPeriph - specifies the AHB peripheral to gates its clock. + * RCC_AHBPeriph_DMA1. + * RCC_AHBPeriph_SRAM. + * RCC_AHBPeriph_USBFS. + * RCC_AHBPeriph_USBPD + * Note- + * SRAM clock can be disabled only during sleep mode. + * NewState: ENABLE or DISABLE. + * + * @return none + */ +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->AHBPCENR |= RCC_AHBPeriph; + } + else + { + RCC->AHBPCENR &= ~RCC_AHBPeriph; + } +} + +/********************************************************************* + * @fn RCC_APB2PeriphClockCmd + * + * @brief Enables or disables the High Speed APB (APB2) peripheral clock. + * + * @param RCC_APB2Periph - specifies the APB2 peripheral to gates its clock. + * RCC_APB2Periph_AFIO. + * RCC_APB2Periph_GPIOA. + * RCC_APB2Periph_GPIOB. + * RCC_APB2Periph_GPIOC. + * RCC_APB2Periph_ADC1. + * RCC_APB2Periph_TIM1. + * RCC_APB2Periph_SPI1. + * RCC_APB2Periph_USART1. + * NewState - ENABLE or DISABLE + * + * @return none + */ +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->APB2PCENR |= RCC_APB2Periph; + } + else + { + RCC->APB2PCENR &= ~RCC_APB2Periph; + } +} + +/********************************************************************* + * @fn RCC_APB1PeriphClockCmd + * + * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. + * + * @param RCC_APB1Periph - specifies the APB1 peripheral to gates its clock. + * RCC_APB1Periph_TIM2. + * RCC_APB1Periph_TIM3. + * RCC_APB1Periph_WWDG. + * RCC_APB1Periph_USART2. + * RCC_APB1Periph_USART3. + * RCC_APB1Periph_USART4 + * RCC_APB1Periph_I2C1. + * RCC_APB1Periph_PWR. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->APB1PCENR |= RCC_APB1Periph; + } + else + { + RCC->APB1PCENR &= ~RCC_APB1Periph; + } +} + +/********************************************************************* + * @fn RCC_AHBPeriphResetCmd + * + * @brief Forces or releases AHB peripheral reset. + * + * @param RCC_AHBPeriph - specifies the AHB peripheral to reset. + * RCC_AHBPeriph_USBFS. + * RCC_AHBPeriph_IO2W. + * RCC_AHBPeriph_USBPD. + * NewState: ENABLE or DISABLE. + * + * @return none + */ +void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->AHBPCENR |= RCC_AHBPeriph; + } + else + { + RCC->AHBPCENR &= ~RCC_AHBPeriph; + } +} + +/********************************************************************* + * @fn RCC_APB2PeriphResetCmd + * + * @brief Forces or releases APB (APB2) peripheral reset. + * + * @param RCC_APB2Periph - specifies the APB2 peripheral to reset. + * RCC_APB2Periph_AFIO. + * RCC_APB2Periph_GPIOA. + * RCC_APB2Periph_GPIOB. + * RCC_APB2Periph_GPIOC. + * RCC_APB2Periph_ADC1. + * RCC_APB2Periph_TIM1. + * RCC_APB2Periph_SPI1. + * RCC_APB2Periph_USART1. + * NewState - ENABLE or DISABLE + * + * @return none + */ +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->APB2PRSTR |= RCC_APB2Periph; + } + else + { + RCC->APB2PRSTR &= ~RCC_APB2Periph; + } +} + +/********************************************************************* + * @fn RCC_APB1PeriphResetCmd + * + * @brief Forces or releases APB (APB1) peripheral reset. + * + * @param RCC_APB1Periph - specifies the APB1 peripheral to reset. + * RCC_APB1Periph_TIM2. + * RCC_APB1Periph_TIM3. + * RCC_APB1Periph_WWDG. + * RCC_APB1Periph_USART2. + * RCC_APB1Periph_USART3. + * RCC_APB1Periph_USART4 + * RCC_APB1Periph_I2C1. + * RCC_APB1Periph_PWR. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + RCC->APB1PRSTR |= RCC_APB1Periph; + } + else + { + RCC->APB1PRSTR &= ~RCC_APB1Periph; + } +} + +/********************************************************************* + * @fn RCC_MCOConfig + * + * @brief Selects the clock source to output on MCO pin. + * + * @param RCC_MCO - specifies the clock source to output. + * RCC_MCO_NoClock - No clock selected. + * RCC_MCO_SYSCLK - System clock selected. + * RCC_MCO_HSI - HSI oscillator clock selected. + * + * @return none + */ +void RCC_MCOConfig(uint8_t RCC_MCO) +{ + *(__IO uint8_t *) CFGR0_BYTE4_ADDRESS = RCC_MCO; +} + +/********************************************************************* + * @fn RCC_GetFlagStatus + * + * @brief Checks whether the specified RCC flag is set or not. + * + * @param RCC_FLAG - specifies the flag to check. + * RCC_FLAG_HSIRDY - HSI oscillator clock ready. + * RCC_FLAG_OPARST - OPA reset. + * RCC_FLAG_PINRST - Pin reset. + * RCC_FLAG_PORRST - POR/PDR reset. + * RCC_FLAG_SFTRST - Software reset. + * RCC_FLAG_IWDGRST - Independent Watchdog reset. + * RCC_FLAG_WWDGRST - Window Watchdog reset. + * RCC_FLAG_LPWRRST - Low Power reset. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + + FlagStatus bitstatus = RESET; + tmp = RCC_FLAG >> 5; + + if (tmp == 1) + { + statusreg = RCC->CTLR; + } + else + { + statusreg = RCC->RSTSCKR; + } + + tmp = RCC_FLAG & FLAG_Mask; + + if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RCC_ClearFlag + * + * @brief Clears the RCC reset flags. + * Note- + * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + * @return none + */ +void RCC_ClearFlag(void) +{ + RCC->RSTSCKR |= RSTSCKR_RMVF_Set; +} + + + + diff --git a/Code/DAP_X033/Peripheral/src/ch32x035_spi.c b/Code/DAP_X033/Peripheral/src/ch32x035_spi.c new file mode 100644 index 0000000..7a79142 --- /dev/null +++ b/Code/DAP_X033/Peripheral/src/ch32x035_spi.c @@ -0,0 +1,506 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_spi.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file provides all the SPI firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_spi.h" +#include "ch32x035_rcc.h" + +/* SPI SPE mask */ +#define CTLR1_SPE_Set ((uint16_t)0x0040) +#define CTLR1_SPE_Reset ((uint16_t)0xFFBF) + +/* SPI CRCNext mask */ +#define CTLR1_CRCNext_Set ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CTLR1_CRCEN_Set ((uint16_t)0x2000) +#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CTLR2_SSOE_Set ((uint16_t)0x0004) +#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +#define CTLR1_CLEAR_Mask ((uint16_t)0x3040) + +/********************************************************************* + * @fn SPI_I2S_DeInit + * + * @brief Deinitializes the SPIx peripheral registers to their default + * reset values (Affects also the I2Ss). + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * + * @return none + */ +void SPI_I2S_DeInit(SPI_TypeDef *SPIx) +{ + if(SPIx == SPI1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); + } +} + +/********************************************************************* + * @fn SPI_Init + * + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * SPI_InitStruct - pointer to a SPI_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral. + * + * @return none + */ +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct) +{ + uint16_t tmpreg = 0; + + tmpreg = SPIx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | + SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | + SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | + SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); + + SPIx->CTLR1 = tmpreg; + SPIx->CRCR = SPI_InitStruct->SPI_CRCPolynomial; +} + +/********************************************************************* + * @fn SPI_StructInit + * + * @brief Fills each SPI_InitStruct member with its default value. + * + * @param SPI_InitStruct - pointer to a SPI_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct) +{ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + /*"SPI_FirstBit_LSB" not support SPI slave mode*/ + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + SPI_InitStruct->SPI_CRCPolynomial = 7; +} + +/********************************************************************* + * @fn SPI_Cmd + * + * @brief Enables or disables the specified SPI peripheral. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR1 |= CTLR1_SPE_Set; + } + else + { + SPIx->CTLR1 &= CTLR1_SPE_Reset; + } +} + +/********************************************************************* + * @fn SPI_I2S_ITConfig + * + * @brief Enables or disables the specified SPI interrupts. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * SPI_I2S_IT - specifies the SPI interrupt source to be + * enabled or disabled. + * SPI_I2S_IT_TXE - Tx buffer empty interrupt mask. + * SPI_I2S_IT_RXNE - Rx buffer not empty interrupt mask. + * SPI_I2S_IT_ERR - Error interrupt mask. + * NewState: ENABLE or DISABLE. + * @return none + */ +void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) +{ + uint16_t itpos = 0, itmask = 0; + + itpos = SPI_I2S_IT >> 4; + itmask = (uint16_t)1 << (uint16_t)itpos; + + if(NewState != DISABLE) + { + SPIx->CTLR2 |= itmask; + } + else + { + SPIx->CTLR2 &= (uint16_t)~itmask; + } +} + +/********************************************************************* + * @fn SPI_I2S_DMACmd + * + * @brief Enables or disables the SPIxDMA interface. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * SPI_I2S_DMAReq - specifies the SPI DMA transfer request to + * be enabled or disabled. + * SPI_I2S_DMAReq_Tx - Tx buffer DMA transfer request. + * SPI_I2S_DMAReq_Rx - Rx buffer DMA transfer request. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR2 |= SPI_I2S_DMAReq; + } + else + { + SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + +/********************************************************************* + * @fn SPI_I2S_SendData + * + * @brief Transmits a Data through the SPIx peripheral. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * Data - Data to be transmitted. + * + * @return none + */ +void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data) +{ + SPIx->DATAR = Data; +} + +/********************************************************************* + * @fn SPI_I2S_ReceiveData + * + * @brief Returns the most recent received data by the SPIx peripheral. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * Data - Data to be transmitted. + * + * @return SPIx->DATAR - The value of the received data. + */ +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx) +{ + return SPIx->DATAR; +} + +/********************************************************************* + * @fn SPI_NSSInternalSoftwareConfig + * + * @brief Configures internally by software the NSS pin for the selected SPI. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * SPI_NSSInternalSoft - + * SPI_NSSInternalSoft_Set - Set NSS pin internally. + * SPI_NSSInternalSoft_Reset - Reset NSS pin internally. + * + * @return none + */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft) +{ + if(SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) + { + SPIx->CTLR1 |= SPI_NSSInternalSoft_Set; + } + else + { + SPIx->CTLR1 &= SPI_NSSInternalSoft_Reset; + } +} + +/********************************************************************* + * @fn SPI_SSOutputCmd + * + * @brief Enables or disables the SS output for the selected SPI. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * NewState - new state of the SPIx SS output. + * + * @return none + */ +void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR2 |= CTLR2_SSOE_Set; + } + else + { + SPIx->CTLR2 &= CTLR2_SSOE_Reset; + } +} + +/********************************************************************* + * @fn SPI_DataSizeConfig + * + * @brief Configures the data size for the selected SPI. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * SPI_DataSize - specifies the SPI data size. + * SPI_DataSize_16b - Set data frame format to 16bit. + * SPI_DataSize_8b - Set data frame format to 8bit. + * + * @return none + */ +void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize) +{ + SPIx->CTLR1 &= (uint16_t)~SPI_DataSize_16b; + SPIx->CTLR1 |= SPI_DataSize; +} + +/********************************************************************* + * @fn SPI_TransmitCRC + * + * @brief Transmit the SPIx CRC value. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * + * @return none + */ +void SPI_TransmitCRC(SPI_TypeDef *SPIx) +{ + SPIx->CTLR1 |= CTLR1_CRCNext_Set; +} + +/********************************************************************* + * @fn SPI_CalculateCRC + * + * @brief Enables or disables the CRC value calculation of the transferred bytes. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * NewState - new state of the SPIx CRC value calculation. + * + * @return none + */ +void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR1 |= CTLR1_CRCEN_Set; + } + else + { + SPIx->CTLR1 &= CTLR1_CRCEN_Reset; + } +} + +/********************************************************************* + * @fn SPI_GetCRC + * + * @brief Returns the transmit or the receive CRC register value for the specified SPI. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * SPI_CRC - specifies the CRC register to be read. + * SPI_CRC_Tx - Selects Tx CRC register. + * SPI_CRC_Rx - Selects Rx CRC register. + * + * @return crcreg: The selected CRC register value. + */ +uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + + if(SPI_CRC != SPI_CRC_Rx) + { + crcreg = SPIx->TCRCR; + } + else + { + crcreg = SPIx->RCRCR; + } + + return crcreg; +} + +/********************************************************************* + * @fn SPI_GetCRCPolynomial + * + * @brief Returns the CRC Polynomial register value for the specified SPI. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * + * @return SPIx->CRCR - The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) +{ + return SPIx->CRCR; +} + +/********************************************************************* + * @fn SPI_BiDirectionalLineConfig + * + * @brief Selects the data transfer direction in bi-directional mode + * for the specified SPI. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * SPI_Direction - specifies the data transfer direction in + * bi-directional mode. + * SPI_Direction_Tx - Selects Tx transmission direction. + * SPI_Direction_Rx - Selects Rx receive direction. + * + * @return none + */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction) +{ + if(SPI_Direction == SPI_Direction_Tx) + { + SPIx->CTLR1 |= SPI_Direction_Tx; + } + else + { + SPIx->CTLR1 &= SPI_Direction_Rx; + } +} + +/********************************************************************* + * @fn SPI_I2S_GetFlagStatus + * + * @brief Checks whether the specified SPI/I2S flag is set or not. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * SPI_I2S_FLAG - specifies the SPI/I2S flag to check. + * SPI_I2S_FLAG_TXE - Transmit buffer empty flag. + * SPI_I2S_FLAG_RXNE - Receive buffer not empty flag. + * SPI_I2S_FLAG_BSY - Busy flag. + * SPI_I2S_FLAG_OVR - Overrun flag. + * SPI_FLAG_MODF - Mode Fault flag. + * SPI_FLAG_CRCERR - CRC Error flag. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((SPIx->STATR & SPI_I2S_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn SPI_I2S_ClearFlag + * + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * SPI_I2S_FLAG - specifies the SPI flag to clear. + * SPI_FLAG_CRCERR - CRC Error flag. + * Note- + * - OVR (OverRun error) flag is cleared by software sequence: a read + * operation to SPI_DATAR register (SPI_I2S_ReceiveData()) followed by a read + * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()). + * - UDR (UnderRun error) flag is cleared by a read operation to + * SPI_STATR register (SPI_I2S_GetFlagStatus()). + * - MODF (Mode Fault) flag is cleared by software sequence: a read/write + * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()) followed by a + * write operation to SPI_CTLR1 register (SPI_Cmd() to enable the SPI). + * @return FlagStatus: SET or RESET. + */ +void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) +{ + SPIx->STATR = (uint16_t)~SPI_I2S_FLAG; +} + +/********************************************************************* + * @fn SPI_I2S_GetITStatus + * + * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * SPI_I2S_IT - specifies the SPI/I2S interrupt source to check.. + * SPI_I2S_IT_TXE - Transmit buffer empty interrupt. + * SPI_I2S_IT_RXNE - Receive buffer not empty interrupt. + * SPI_I2S_IT_OVR - Overrun interrupt. + * SPI_IT_MODF - Mode Fault interrupt. + * SPI_IT_CRCERR - CRC Error interrupt. + * + * @return FlagStatus: SET or RESET. + */ +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + itmask = SPI_I2S_IT >> 4; + itmask = 0x01 << itmask; + enablestatus = (SPIx->CTLR2 & itmask); + + if(((SPIx->STATR & itpos) != (uint16_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn SPI_I2S_ClearITPendingBit + * + * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * SPI_I2S_IT - specifies the SPI interrupt pending bit to clear. + * SPI_IT_CRCERR - CRC Error interrupt. + * Note- + * - OVR (OverRun Error) interrupt pending bit is cleared by software + * sequence: a read operation to SPI_DATAR register (SPI_I2S_ReceiveData()) + * followed by a read operation to SPI_STATR register (SPI_I2S_GetITStatus()). + * - UDR (UnderRun Error) interrupt pending bit is cleared by a read + * operation to SPI_STATR register (SPI_I2S_GetITStatus()). + * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: + * a read/write operation to SPI_STATR register (SPI_I2S_GetITStatus()) + * followed by a write operation to SPI_CTLR1 register (SPI_Cmd() to enable + * the SPI). + * @return none + */ +void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) +{ + uint16_t itpos = 0; + + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + SPIx->STATR = (uint16_t)~itpos; +} diff --git a/Code/DAP_X033/Peripheral/src/ch32x035_tim.c b/Code/DAP_X033/Peripheral/src/ch32x035_tim.c new file mode 100644 index 0000000..b9210d6 --- /dev/null +++ b/Code/DAP_X033/Peripheral/src/ch32x035_tim.c @@ -0,0 +1,2457 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_tim.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file provides all the TIM firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_tim.h" +#include "ch32x035_rcc.h" + +/* TIM registers bit mask */ +#define SMCFGR_ETR_Mask ((uint16_t)0x00FF) +#define CHCTLR_Offset ((uint16_t)0x0018) +#define CCER_CCE_Set ((uint16_t)0x0001) +#define CCER_CCNE_Set ((uint16_t)0x0004) +#define SPEC_OC12_Mask ((uint16_t)0xFFCE) +#define SPEC_OC34_Mask ((uint16_t)0xFF3D) + +static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); + +/********************************************************************* + * @fn TIM_DeInit + * + * @brief Deinitializes the TIMx peripheral registers to their default + * reset values. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * + * @return none + */ +void TIM_DeInit(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); + } + else if(TIMx == TIM2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); + } + else if(TIMx == TIM3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); + } +} + +/********************************************************************* + * @fn TIM_TimeBaseInit + * + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef + * structure. + * + * @return none + */ +void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) +{ + uint16_t tmpcr1 = 0; + + tmpcr1 = TIMx->CTLR1; + + if((TIMx == TIM1) || (TIMx == TIM2)) + { + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; + } + + tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CTLR1_CKD)); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; + + TIMx->CTLR1 = tmpcr1; + TIMx->ATRLR = TIM_TimeBaseInitStruct->TIM_Period; + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + if((TIMx == TIM1) || (TIMx == TIM2)) + { + TIMx->RPTCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; + } + + TIMx->SWEVGR = TIM_PSCReloadMode_Immediate; +} + +/********************************************************************* + * @fn TIM_OC1Init + * + * @brief Initializes the TIMx Channel1 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CC1E); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR1; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC1M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC1S)); + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1P)); + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + tmpccer |= TIM_OCInitStruct->TIM_OutputState; + + if((TIMx == TIM1) || (TIMx == TIM2)) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NP)); + tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; + + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NE)); + tmpccer |= TIM_OCInitStruct->TIM_OutputNState; + + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1N)); + + tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; + tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR1 = tmpccmrx; + TIMx->CH1CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2Init + * + * @brief Initializes the TIMx Channel2 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC2E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR1; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC2M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC2S)); + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); + + if((TIMx == TIM1) || (TIMx == TIM2)) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NP)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NE)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); + + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2N)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR1 = tmpccmrx; + TIMx->CH2CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3Init + * + * @brief Initializes the TIMx Channel3 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC3E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR2; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC3M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC3S)); + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); + + if((TIMx == TIM1) || (TIMx == TIM2)) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NP)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NE)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3N)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR2 = tmpccmrx; + TIMx->CH3CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC4Init + * + * @brief Initializes the TIMx Channel4 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC4E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR2; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC4M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC4S)); + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC4P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); + + if((TIMx == TIM1) || (TIMx == TIM2)) + { + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS4)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR2 = tmpccmrx; + TIMx->CH4CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_ICInit + * + * @brief IInitializes the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct. + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/********************************************************************* + * @fn TIM_PWMIConfig + * + * @brief Configures the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct to measure an external + * PWM signal. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_ICPolarity_Rising; + uint16_t icoppositeselection = TIM_ICSelection_DirectTI; + + if(TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + icoppositepolarity = TIM_ICPolarity_Falling; + } + else + { + icoppositepolarity = TIM_ICPolarity_Rising; + } + + if(TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + icoppositeselection = TIM_ICSelection_IndirectTI; + } + else + { + icoppositeselection = TIM_ICSelection_DirectTI; + } + + if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/********************************************************************* + * @fn TIM_BDTRConfig + * + * @brief Configures the: Break feature, dead time, Lock level, the OSSI, + * the OSSR State and the AOE(automatic output enable). + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. + * + * @return none + */ +void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | + TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | + TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | + TIM_BDTRInitStruct->TIM_AutomaticOutput; +} + +/********************************************************************* + * @fn TIM_TimeBaseStructInit + * + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * + * @param TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef structure. + * + * @return none + */ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) +{ + TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; + TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +} + +/********************************************************************* + * @fn TIM_OCStructInit + * + * @brief Fills each TIM_OCInitStruct member with its default value. + * + * @param TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; + TIM_OCInitStruct->TIM_Pulse = 0x0000; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +/********************************************************************* + * @fn TIM_ICStructInit + * + * @brief Fills each TIM_ICInitStruct member with its default value. + * + * @param TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = 0x00; +} + +/********************************************************************* + * @fn TIM_BDTRStructInit + * + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * + * @param TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. + * + * @return none + */ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; + TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; + TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStruct->TIM_DeadTime = 0x00; + TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +} + +/********************************************************************* + * @fn TIM_Cmd + * + * @brief Enables or disables the specified TIM peripheral. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_CEN; + } + else + { + TIMx->CTLR1 &= (uint16_t)(~((uint16_t)TIM_CEN)); + } +} + +/********************************************************************* + * @fn TIM_CtrlPWMOutputs + * + * @brief Enables or disables the TIM peripheral Main Outputs. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->BDTR |= TIM_MOE; + } + else + { + TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_MOE)); + } +} + +/********************************************************************* + * @fn TIM_ITConfig + * + * @brief Enables or disables the specified TIM interrupts. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_IT - specifies the TIM interrupts sources to be enabled or disabled. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->DMAINTENR |= TIM_IT; + } + else + { + TIMx->DMAINTENR &= (uint16_t)~TIM_IT; + } +} + +/******************************************************************************* + * @fn TIM_GenerateEvent + * + * @brief Configures the TIMx event to be generate by software. + * + * @param TIMx: where x can be 1 to 3 to select the TIM peripheral. + * TIM_EventSource: specifies the event source. + * TIM_EventSource_Update: Timer update Event source. + * TIM_EventSource_CC1: Timer Capture Compare 1 Event source. + * TIM_EventSource_CC2: Timer Capture Compare 2 Event source. + * TIM_EventSource_CC3: Timer Capture Compare 3 Event source. + * TIM_EventSource_CC4: Timer Capture Compare 4 Event source. + * TIM_EventSource_COM: Timer COM event source. + * TIM_EventSource_Trigger: Timer Trigger Event source. + * TIM_EventSource_Break: Timer Break event source. + * + * @return None + */ +void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource) +{ + TIMx->SWEVGR = TIM_EventSource; +} + +/********************************************************************* + * @fn TIM_DMAConfig + * + * @brief Configures the TIMx's DMA interface. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_DMABase: DMA Base address. + * TIM_DMABase_CR. + * TIM_DMABase_CR2. + * TIM_DMABase_SMCR. + * TIM_DMABase_DIER. + * TIM1_DMABase_SR. + * TIM_DMABase_EGR. + * TIM_DMABase_CCMR1. + * TIM_DMABase_CCMR2. + * TIM_DMABase_CCER. + * TIM_DMABase_CNT. + * TIM_DMABase_PSC. + * TIM_DMABase_CCR1. + * TIM_DMABase_CCR2. + * TIM_DMABase_CCR3. + * TIM_DMABase_CCR4. + * TIM_DMABase_BDTR. + * TIM_DMABase_DCR. + * TIM_DMABurstLength - DMA Burst length. + * TIM_DMABurstLength_1Transfer. + * TIM_DMABurstLength_18Transfers. + * + * @return none + */ +void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + TIMx->DMACFGR = TIM_DMABase | TIM_DMABurstLength; +} + +/********************************************************************* + * @fn TIM_DMACmd + * + * @brief Enables or disables the TIMx's DMA Requests. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_DMASource - specifies the DMA Request sources. + * TIM_DMA_Update - TIM update Interrupt source. + * TIM_DMA_CC1 - TIM Capture Compare 1 DMA source. + * TIM_DMA_CC2 - TIM Capture Compare 2 DMA source. + * TIM_DMA_CC3 - TIM Capture Compare 3 DMA source. + * TIM_DMA_CC4 - TIM Capture Compare 4 DMA source. + * TIM_DMA_COM - TIM Commutation DMA source. + * TIM_DMA_Trigger - TIM Trigger DMA source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->DMAINTENR |= TIM_DMASource; + } + else + { + TIMx->DMAINTENR &= (uint16_t)~TIM_DMASource; + } +} + +/********************************************************************* + * @fn TIM_InternalClockConfig + * + * @brief Configures the TIMx internal Clock. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * + * @return none + */ +void TIM_InternalClockConfig(TIM_TypeDef *TIMx) +{ + TIMx->SMCFGR &= (uint16_t)(~((uint16_t)TIM_SMS)); +} + +/********************************************************************* + * @fn TIM_ITRxExternalClockConfig + * + * @brief Configures the TIMx Internal Trigger as External Clock. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_InputTriggerSource: Trigger source. + * TIM_TS_ITR0 - Internal Trigger 0. + * TIM_TS_ITR1 - Internal Trigger 1. + * TIM_TS_ITR2 - Internal Trigger 2. + * TIM_TS_ITR3 - Internal Trigger 3. + * + * @return none + */ +void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) +{ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + TIMx->SMCFGR |= TIM_SlaveMode_External1; +} + +/********************************************************************* + * @fn TIM_TIxExternalClockConfig + * + * @brief Configures the TIMx Trigger as External Clock. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_TIxExternalCLKSource - Trigger source. + * TIM_TIxExternalCLK1Source_TI1ED - TI1 Edge Detector. + * TIM_TIxExternalCLK1Source_TI1 - Filtered Timer Input 1. + * TIM_TIxExternalCLK1Source_TI2 - Filtered Timer Input 2. + * TIM_ICPolarity - specifies the TIx Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_DMA_COM - TIM Commutation DMA source. + * TIM_DMA_Trigger - TIM Trigger DMA source. + * ICFilter - specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter) +{ + if(TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + TIMx->SMCFGR |= TIM_SlaveMode_External1; +} + +/********************************************************************* + * @fn TIM_ETRClockMode1Config + * + * @brief Configures the External clock Mode1. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); + tmpsmcr |= TIM_SlaveMode_External1; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); + tmpsmcr |= TIM_TS_ETRF; + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_ETRClockMode2Config + * + * @brief Configures the External clock Mode2. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + TIMx->SMCFGR |= TIM_ECE; +} + +/********************************************************************* + * @fn TIM_ETRConfig + * + * @brief Configures the TIMx External Trigger (ETR). + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= SMCFGR_ETR_Mask; + tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_PrescalerConfig + * + * @brief Configures the TIMx Prescaler. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * Prescaler - specifies the Prescaler Register value. + * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. + * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. + * TIM_PSCReloadMode_Update - The Prescaler is loaded at the update event. + * TIM_PSCReloadMode_Immediate - The Prescaler is loaded immediately. + * + * @return none + */ +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + TIMx->PSC = Prescaler; + TIMx->SWEVGR = TIM_PSCReloadMode; +} + +/********************************************************************* + * @fn TIM_CounterModeConfig + * + * @brief Specifies the TIMx Counter Mode to be used. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_CounterMode - specifies the Counter Mode to be used. + * TIM_CounterMode_Up - TIM Up Counting Mode. + * TIM_CounterMode_Down - TIM Down Counting Mode. + * TIM_CounterMode_CenterAligned1 - TIM Center Aligned Mode1. + * TIM_CounterMode_CenterAligned2 - TIM Center Aligned Mode2. + * TIM_CounterMode_CenterAligned3 - TIM Center Aligned Mode3. + * + * @return none + */ +void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode) +{ + uint16_t tmpcr1 = 0; + + tmpcr1 = TIMx->CTLR1; + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); + tmpcr1 |= TIM_CounterMode; + TIMx->CTLR1 = tmpcr1; +} + +/********************************************************************* + * @fn TIM_SelectInputTrigger + * + * @brief Selects the Input Trigger source. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_InputTriggerSource - The Input Trigger source. + * TIM_TS_ITR0 - Internal Trigger 0. + * TIM_TS_ITR1 - Internal Trigger 1. + * TIM_TS_ITR2 - Internal Trigger 2. + * TIM_TS_ITR3 - Internal Trigger 3. + * TIM_TS_TI1F_ED - TI1 Edge Detector. + * TIM_TS_TI1FP1 - Filtered Timer Input 1. + * TIM_TS_TI2FP2 - Filtered Timer Input 2. + * TIM_TS_ETRF - External Trigger input. + * + * @return none + */ +void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); + tmpsmcr |= TIM_InputTriggerSource; + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_EncoderInterfaceConfig + * + * @brief Configures the TIMx Encoder Interface. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_EncoderMode - specifies the TIMx Encoder Mode. + * TIM_EncoderMode_TI1 - Counter counts on TI1FP1 edge depending + * on TI2FP2 level. + * TIM_EncoderMode_TI2 - Counter counts on TI2FP2 edge depending + * on TI1FP1 level. + * TIM_EncoderMode_TI12 - Counter counts on both TI1FP1 and + * TI2FP2 edges depending. + * TIM_IC1Polarity - specifies the IC1 Polarity. + * TIM_ICPolarity_Falling - IC Falling edge. + * TTIM_ICPolarity_Rising - IC Rising edge. + * TIM_IC2Polarity - specifies the IC2 Polarity. + * TIM_ICPolarity_Falling - IC Falling edge. + * TIM_ICPolarity_Rising - IC Rising edge. + * + * @return none + */ +void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint16_t tmpccer = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); + tmpsmcr |= TIM_EncoderMode; + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & (uint16_t)(~((uint16_t)TIM_CC2S))); + tmpccmr1 |= TIM_CC1S_0 | TIM_CC2S_0; + tmpccer &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1P)) & ((uint16_t) ~((uint16_t)TIM_CC2P))); + tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + TIMx->SMCFGR = tmpsmcr; + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_ForcedOC1Config + * + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC1REF. + * TIM_ForcedAction_InActive - Force inactive level on OC1REF. + * + * @return none + */ +void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1M); + tmpccmr1 |= TIM_ForcedAction; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ForcedOC2Config + * + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC2REF. + * TIM_ForcedAction_InActive - Force inactive level on OC2REF. + * + * @return none + */ +void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2M); + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ForcedOC3Config + * + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC3REF. + * TIM_ForcedAction_InActive - Force inactive level on OC3REF. + * + * @return none + */ +void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3M); + tmpccmr2 |= TIM_ForcedAction; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ForcedOC4Config + * + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC4REF. + * TIM_ForcedAction_InActive - Force inactive level on OC4REF. + * + * @return none + */ +void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4M); + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ARRPreloadConfig + * + * @brief Enables or disables TIMx peripheral Preload register on ARR. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_ARPE; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_ARPE); + } +} + +/********************************************************************* + * @fn TIM_SelectCOM + * + * @brief Selects the TIM peripheral Commutation event. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCUS; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCUS); + } +} + +/********************************************************************* + * @fn TIM_SelectCCDMA + * + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCDS; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCDS); + } +} + +/********************************************************************* + * @fn TIM_CCPreloadControl + * + * @brief DSets or Resets the TIM peripheral Capture Compare Preload Control bit. + * reset values (Affects also the I2Ss). + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCPC; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCPC); + } +} + +/********************************************************************* + * @fn TIM_OC1PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR1. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1PE); + tmpccmr1 |= TIM_OCPreload; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC2PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR2. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2PE); + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC3PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR3. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3PE); + tmpccmr2 |= TIM_OCPreload; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC4PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR4. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4PE); + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC1FastConfig + * + * @brief Configures the TIMx Output Compare 1 Fast feature. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1FE); + tmpccmr1 |= TIM_OCFast; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC2FastConfig + * + * @brief Configures the TIMx Output Compare 2 Fast feature. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2FE); + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC3FastConfig + * + * @brief Configures the TIMx Output Compare 3 Fast feature. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3FE); + tmpccmr2 |= TIM_OCFast; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC4FastConfig + * + * @brief Configures the TIMx Output Compare 4 Fast feature. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4FE); + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ClearOC1Ref + * + * @brief Clears or safeguards the OCREF1 signal on an external event. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1CE); + tmpccmr1 |= TIM_OCClear; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ClearOC2Ref + * + * @brief Clears or safeguards the OCREF2 signal on an external event. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2CE); + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ClearOC3Ref + * + * @brief Clears or safeguards the OCREF3 signal on an external event. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3CE); + tmpccmr2 |= TIM_OCClear; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ClearOC4Ref + * + * @brief Clears or safeguards the OCREF4 signal on an external event. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4CE); + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC1PolarityConfig + * + * @brief Configures the TIMx channel 1 polarity. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_OCPolarity - specifies the OC1 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1P); + tmpccer |= TIM_OCPolarity; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC1NPolarityConfig + * + * @brief Configures the TIMx channel 1 polarity. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC1N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1NP); + tmpccer |= TIM_OCNPolarity; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2PolarityConfig + * + * @brief Configures the TIMx channel 2 polarity. + * + * @param TIMx - where x can be 1 to 3 to select the TIM peripheral. + * TIM_OCPolarity - specifies the OC2 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 4); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2NPolarityConfig + * + * @brief Configures the TIMx channel 2 polarity. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC1N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3PolarityConfig + * + * @brief Configures the TIMx Channel 3 polarity. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_OCPolarit - specifies the OC3 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 8); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3NPolarityConfig + * + * @brief Configures the TIMx Channel 3N polarity. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC2N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC4PolarityConfig + * + * @brief Configures the TIMx Channel 4 polarity. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_OCPolarit - specifies the OC3 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC4P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 12); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_CCxCmd + * + * @brief Enables or disables the TIM Capture Compare Channel x. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_Channel_4 - TIM Channel 4. + * TIM_CCx - specifies the TIM Channel CCxE bit new state. + * TIM_CCx_Enable. + * TIM_CCx_Disable. + * + * @return none + */ +void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) +{ + uint16_t tmp = 0; + + tmp = CCER_CCE_Set << TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp; + TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); +} + +/********************************************************************* + * @fn TIM_CCxNCmd + * + * @brief Enables or disables the TIM Capture Compare Channel xN. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_CCxN - specifies the TIM Channel CCxNE bit new state. + * TIM_CCxN_Enable. + * TIM_CCxN_Disable. + * + * @return none + */ +void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) +{ + uint16_t tmp = 0; + + tmp = CCER_CCNE_Set << TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp; + TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); +} + +/********************************************************************* + * @fn TIM_SelectOCxM + * + * @brief Selects the TIM Output Compare Mode. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_Channel_4 - TIM Channel 4. + * TIM_OCMode - specifies the TIM Output Compare Mode. + * TIM_OCMode_Timing. + * TIM_OCMode_Active. + * TIM_OCMode_Toggle. + * TIM_OCMode_PWM1. + * TIM_OCMode_PWM2. + * TIM_ForcedAction_Active. + * TIM_ForcedAction_InActive. + * + * @return none + */ +void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + tmp = (uint32_t)TIMx; + tmp += CHCTLR_Offset; + tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp1; + + if((TIM_Channel == TIM_Channel_1) || (TIM_Channel == TIM_Channel_3)) + { + tmp += (TIM_Channel >> 1); + *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC1M); + *(__IO uint32_t *)tmp |= TIM_OCMode; + } + else + { + tmp += (uint16_t)(TIM_Channel - (uint16_t)4) >> (uint16_t)1; + *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC2M); + *(__IO uint32_t *)tmp |= (uint16_t)(TIM_OCMode << 8); + } +} + +/********************************************************************* + * @fn TIM_UpdateDisableConfig + * + * @brief Enables or Disables the TIMx Update event. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_UDIS; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_UDIS); + } +} + +/********************************************************************* + * @fn TIM_UpdateRequestConfig + * + * @brief Configures the TIMx Update Request Interrupt source. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * TIM_UpdateSource - specifies the Update source. + * TIM_UpdateSource_Regular. + * TIM_UpdateSource_Global. + * + * @return none + */ +void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource) +{ + if(TIM_UpdateSource != TIM_UpdateSource_Global) + { + TIMx->CTLR1 |= TIM_URS; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_URS); + } +} + +/********************************************************************* + * @fn TIM_SelectHallSensor + * + * @brief Enables or disables the TIMx's Hall sensor interface. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_TI1S; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_TI1S); + } +} + +/********************************************************************* + * @fn TIM_SelectOnePulseMode + * + * @brief Selects the TIMx's One Pulse Mode. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * TIM_OPMode - specifies the OPM Mode to be used. + * TIM_OPMode_Single. + * TIM_OPMode_Repetitive. + * + * @return none + */ +void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode) +{ + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM); + TIMx->CTLR1 |= TIM_OPMode; +} + +/********************************************************************* + * @fn TIM_SelectOutputTrigger + * + * @brief Selects the TIMx Trigger Output Mode. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * TIM_TRGOSource - specifies the Trigger Output source. + * TIM_TRGOSource_Reset - The UG bit in the TIM_EGR register is + * used as the trigger output (TRGO). + * TIM_TRGOSource_Enable - The Counter Enable CEN is used as the + * trigger output (TRGO). + * TIM_TRGOSource_Update - The update event is selected as the + * trigger output (TRGO). + * TIM_TRGOSource_OC1 - The trigger output sends a positive pulse + * when the CC1IF flag is to be set, as soon as a capture or compare match occurs (TRGO). + * TIM_TRGOSource_OC1Ref - OC1REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC2Ref - OC2REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC3Ref - OC3REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC4Ref - OC4REF signal is used as the trigger output (TRGO). + * + * @return none + */ +void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource) +{ + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_MMS); + TIMx->CTLR2 |= TIM_TRGOSource; +} + +/********************************************************************* + * @fn TIM_SelectSlaveMode + * + * @brief Selects the TIMx Slave Mode. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * TIM_SlaveMode - specifies the Timer Slave Mode. + * TIM_SlaveMode_Reset - Rising edge of the selected trigger + * signal (TRGI) re-initializes. + * TIM_SlaveMode_Gated - The counter clock is enabled when the + * trigger signal (TRGI) is high. + * TIM_SlaveMode_Trigger - The counter starts at a rising edge + * of the trigger TRGI. + * TIM_SlaveMode_External1 - Rising edges of the selected trigger + * (TRGI) clock the counter. + * + * @return none + */ +void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode) +{ + TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_SMS); + TIMx->SMCFGR |= TIM_SlaveMode; +} + +/********************************************************************* + * @fn TIM_SelectMasterSlaveMode + * + * @brief Sets or Resets the TIMx Master/Slave Mode. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * TIM_MasterSlaveMode - specifies the Timer Master Slave Mode. + * TIM_MasterSlaveMode_Enable - synchronization between the current + * timer and its slaves (through TRGO). + * TIM_MasterSlaveMode_Disable - No action. + * + * @return none + */ +void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode) +{ + TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_MSM); + TIMx->SMCFGR |= TIM_MasterSlaveMode; +} + +/********************************************************************* + * @fn TIM_SetCounter + * + * @brief Sets the TIMx Counter Register value. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * Counter - specifies the Counter register new value. + * + * @return none + */ +void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter) +{ + TIMx->CNT = Counter; +} + +/********************************************************************* + * @fn TIM_SetAutoreload + * + * @brief Sets the TIMx Autoreload Register value. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * Autoreload - specifies the Autoreload register new value. + * + * @return none + */ +void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload) +{ + TIMx->ATRLR = Autoreload; +} + +/********************************************************************* + * @fn TIM_SetCompare1 + * + * @brief Sets the TIMx Capture Compare1 Register value. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1) +{ + TIMx->CH1CVR = Compare1; +} + +/********************************************************************* + * @fn TIM_SetCompare2 + * + * @brief Sets the TIMx Capture Compare2 Register value. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2) +{ + TIMx->CH2CVR = Compare2; +} + +/********************************************************************* + * @fn TIM_SetCompare3 + * + * @brief Sets the TIMx Capture Compare3 Register value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3) +{ + TIMx->CH3CVR = Compare3; +} + +/********************************************************************* + * @fn TIM_SetCompare4 + * + * @brief Sets the TIMx Capture Compare4 Register value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4) +{ + TIMx->CH4CVR = Compare4; +} + +/********************************************************************* + * @fn TIM_SetIC1Prescaler + * + * @brief Sets the TIMx Input Capture 1 prescaler. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC1PSC); + TIMx->CHCTLR1 |= TIM_ICPSC; +} + +/********************************************************************* + * @fn TIM_SetIC2Prescaler + * + * @brief Sets the TIMx Input Capture 2 prescaler. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC2PSC); + TIMx->CHCTLR1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/********************************************************************* + * @fn TIM_SetIC3Prescaler + * + * @brief Sets the TIMx Input Capture 3 prescaler. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC3PSC); + TIMx->CHCTLR2 |= TIM_ICPSC; +} + +/********************************************************************* + * @fn TIM_SetIC4Prescaler + * + * @brief Sets the TIMx Input Capture 4 prescaler. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC4PSC); + TIMx->CHCTLR2 |= (uint16_t)(TIM_ICPSC << 8); +} + +/********************************************************************* + * @fn TIM_SetClockDivision + * + * @brief Sets the TIMx Clock Division value. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * TIM_CKD - specifies the clock division value. + * TIM_CKD_DIV1 - TDTS = Tck_tim. + * TIM_CKD_DIV2 - TDTS = 2*Tck_tim. + * TIM_CKD_DIV4 - TDTS = 4*Tck_tim. + * + * @return none + */ +void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD) +{ + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_CTLR1_CKD); + TIMx->CTLR1 |= TIM_CKD; +} + +/********************************************************************* + * @fn TIM_GetCapture1 + * + * @brief Gets the TIMx Input Capture 1 value. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * + * @return TIMx->CH1CVR - Capture Compare 1 Register value. + */ +uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx) +{ + return TIMx->CH1CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture2 + * + * @brief Gets the TIMx Input Capture 2 value. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * + * @return TIMx->CH2CVR - Capture Compare 2 Register value. + */ +uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx) +{ + return TIMx->CH2CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture3 + * + * @brief Gets the TIMx Input Capture 3 value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * + * @return TIMx->CH3CVR - Capture Compare 3 Register value. + */ +uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx) +{ + return TIMx->CH3CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture4 + * + * @brief Gets the TIMx Input Capture 4 value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * + * @return TIMx->CH4CVR - Capture Compare 4 Register value. + */ +uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx) +{ + return TIMx->CH4CVR; +} + +/********************************************************************* + * @fn TIM_GetCounter + * + * @brief Gets the TIMx Counter value. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * + * @return TIMx->CNT - Counter Register value. + */ +uint16_t TIM_GetCounter(TIM_TypeDef *TIMx) +{ + return TIMx->CNT; +} + +/********************************************************************* + * @fn TIM_GetPrescaler + * + * @brief Gets the TIMx Prescaler value. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * + * @return TIMx->PSC - Prescaler Register value. + */ +uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx) +{ + return TIMx->PSC; +} + +/********************************************************************* + * @fn TIM_GetFlagStatus + * + * @brief Checks whether the specified TIM flag is set or not. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * TIM_FLAG - specifies the flag to check. + * TIM_FLAG_Update - TIM update Flag. + * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. + * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. + * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. + * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. + * TIM_FLAG_COM - TIM Commutation Flag. + * TIM_FLAG_Trigger - TIM Trigger Flag. + * TIM_FLAG_Break - TIM Break Flag. + * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. + * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. + * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. + * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. + * + * @return none + */ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) +{ + ITStatus bitstatus = RESET; + + if((TIMx->INTFR & TIM_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn TIM_ClearFlag + * + * @brief Clears the TIMx's pending flags. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * TIM_FLAG - specifies the flag to check. + * TIM_FLAG_Update - TIM update Flag. + * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. + * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. + * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. + * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. + * TIM_FLAG_COM - TIM Commutation Flag. + * TIM_FLAG_Trigger - TIM Trigger Flag. + * TIM_FLAG_Break - TIM Break Flag. + * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. + * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. + * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. + * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. + * + * @return none + */ +void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) +{ + TIMx->INTFR = (uint16_t)~TIM_FLAG; +} + +/********************************************************************* + * @fn TIM_GetITStatus + * + * @brief Checks whether the TIM interrupt has occurred or not. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * TIM_IT - specifies the TIM interrupt source to check. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * + * @return none + */ +ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itstatus = 0x0, itenable = 0x0; + + itstatus = TIMx->INTFR & TIM_IT; + + itenable = TIMx->DMAINTENR & TIM_IT; + if((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn TIM_ClearITPendingBit + * + * @brief Clears the TIMx's interrupt pending bits. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * TIM_IT - specifies the TIM interrupt source to check. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * + * @return none + */ +void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT) +{ + TIMx->INTFR = (uint16_t)~TIM_IT; +} + +/********************************************************************* + * @fn TI1_Config + * + * @brief Configure the TI1 as Input. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC1E); + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & ((uint16_t) ~((uint16_t)TIM_IC1F))); + tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P | TIM_CC1NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); + } + + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI2_Config + * + * @brief Configure the TI2 as Input. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC2E); + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 4); + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC2S)) & ((uint16_t) ~((uint16_t)TIM_IC2F))); + tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); + tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC2E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P | TIM_CC2NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC2E); + } + + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI3_Config + * + * @brief Configure the TI3 as Input. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC3E); + tmpccmr2 = TIMx->CHCTLR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 8); + tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC3S)) & ((uint16_t) ~((uint16_t)TIM_IC3F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC3E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC3NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC3E); + } + + TIMx->CHCTLR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI4_Config + * + * @brief Configure the TI4 as Input. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC4E); + tmpccmr2 = TIMx->CHCTLR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 12); + tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CC4S) & ((uint16_t) ~((uint16_t)TIM_IC4F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC4P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC4E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3P); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC4E); + } + + TIMx->CHCTLR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_CaptureModeCmd + * + * @brief Enables or disables the TIM capture over mode. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CaptureModeCmd(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState) + { + TIMx->CTLR1 |= (1<<14); + } + else{ + TIMx->CTLR1 &= ~(1<<14); + } +} + +/********************************************************************* + * @fn TIM_IndicateCaptureLevelCmd + * + * @brief Enables or disables the TIMx capture level indication. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_IndicateCaptureLevelCmd(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState) + { + TIMx->CTLR1 |= (1<<15); + } + else{ + TIMx->CTLR1 &= ~(1<<15); + } +} + +/********************************************************************* + * @fn TIM_OC12_SupersedeModeCmd + * + * @brief Enables or disables the TIMx Channel (1 and 2) supersede mode. + * + * @param TIMx - where x can be 1 to 3 select the TIM peripheral. + * TIM_Supersede_Mode_OC1 - Channel 1 Supersede Mode invalid level. + * TIM_Supersede_Mode_OC1_H - Invalid level is high level. + * TIM_Supersede_Mode_OC1_L - Invalid level is low level. + * TIM_Supersede_Mode_OC2 - Channel 2 Supersede Mode invalid level. + * TIM_Supersede_Mode_OC2_H - Invalid level is high level. + * TIM_Supersede_Mode_OC2_L - Invalid level is low level. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_OC12_SupersedeModeCmd(TIM_TypeDef *TIMx, uint16_t TIM_Supersede_Mode_OC1, uint16_t TIM_Supersede_Mode_OC2, + FunctionalState NewState) +{ + uint32_t tmpreg = 0; + + tmpreg = TIMx->SPEC; + + tmpreg &= SPEC_OC12_Mask; + tmpreg |= TIM_Supersede_Mode_OC1 | TIM_Supersede_Mode_OC2; + + + if(NewState) + { + tmpreg |= (1<<0); + } + + TIMx->SPEC = tmpreg; +} + +/********************************************************************* + * @fn TIM_OC34_SupersedeModeCmd + * + * @brief Enables or disables the TIMx Channel (3 and 4) supersede mode. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_Supersede_Mode_OC3 - Channel 3 Supersede Mode invalid level. + * TIM_Supersede_Mode_OC3_H - Invalid level is high level. + * TIM_Supersede_Mode_OC3_L - Invalid level is low level. + * TIM_Supersede_Mode_OC4 - Channel 4 Supersede Mode invalid level. + * TIM_Supersede_Mode_OC4_H - Invalid level is high level. + * TIM_Supersede_Mode_OC4_L - Invalid level is low level. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_OC34_SupersedeModeCmd(TIM_TypeDef *TIMx, uint16_t TIM_Supersede_Mode_OC3, uint16_t TIM_Supersede_Mode_OC4, + FunctionalState NewState) +{ + uint32_t tmpreg = 0; + + tmpreg = TIMx->SPEC; + + tmpreg &= SPEC_OC34_Mask; + tmpreg |= TIM_Supersede_Mode_OC3 | TIM_Supersede_Mode_OC4; + + + if(NewState) + { + tmpreg |= (1<<1); + } + + TIMx->SPEC = tmpreg; +} diff --git a/Code/DAP_X033/Peripheral/src/ch32x035_usart.c b/Code/DAP_X033/Peripheral/src/ch32x035_usart.c new file mode 100644 index 0000000..bc0593f --- /dev/null +++ b/Code/DAP_X033/Peripheral/src/ch32x035_usart.c @@ -0,0 +1,743 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_usart.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file provides all the USART firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_usart.h" +#include "ch32x035_rcc.h" + +/* USART_Private_Defines */ +#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */ +#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */ + +#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */ + +#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ +#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ +#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ +#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CR1 Mask */ +#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */ + +#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ +#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ + +#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ +#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CR2 STOP Bits Mask */ +#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CR2 Clock Mask */ + +#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */ +#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */ + +#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */ +#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */ + +#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */ +#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ + +#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ +#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CR3 Mask */ + +#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ +#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ +#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */ +#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */ +#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */ + +/********************************************************************* + * @fn USART_DeInit + * + * @brief Deinitializes the USARTx peripheral registers to their default + * reset values. + * + * @param USARTx - where x can be 1, 2 , 3 or 4 to select the UART peripheral. + * + * @return none + */ +void USART_DeInit(USART_TypeDef *USARTx) +{ + if(USARTx == USART1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); + } + else if(USARTx == USART2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); + } + else if(USARTx == USART3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); + } + else if(USARTx == USART4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART4, DISABLE); + } +} + +/********************************************************************* + * @fn USART_Init + * + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct. + * + * @param USARTx - where x can be 1, 2 , 3 or 4 to select the UART peripheral. + * USART_InitStruct - pointer to a USART_InitTypeDef structure + * that contains the configuration information for the specified + * USART peripheral. + * + * @return none + */ +void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct) +{ + uint32_t tmpreg = 0x00, apbclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + uint32_t usartxbase = 0; + RCC_ClocksTypeDef RCC_ClocksStatus; + + if(USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) + { + } + + usartxbase = (uint32_t)USARTx; + tmpreg = USARTx->CTLR2; + tmpreg &= CTLR2_STOP_CLEAR_Mask; + tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; + + USARTx->CTLR2 = (uint16_t)tmpreg; + tmpreg = USARTx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + USARTx->CTLR1 = (uint16_t)tmpreg; + + tmpreg = USARTx->CTLR3; + tmpreg &= CTLR3_CLEAR_Mask; + tmpreg |= USART_InitStruct->USART_HardwareFlowControl; + USARTx->CTLR3 = (uint16_t)tmpreg; + + RCC_GetClocksFreq(&RCC_ClocksStatus); + + if(usartxbase == USART1_BASE) + { + apbclock = RCC_ClocksStatus.PCLK2_Frequency; + } + else + { + apbclock = RCC_ClocksStatus.PCLK1_Frequency; + } + + integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); + tmpreg = (integerdivider / 100) << 4; + + fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); + tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); + + USARTx->BRR = (uint16_t)tmpreg; +} + +/********************************************************************* + * @fn USART_StructInit + * + * @brief Fills each USART_InitStruct member with its default value. + * + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void USART_StructInit(USART_InitTypeDef *USART_InitStruct) +{ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WordLength_8b; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; +} + +/********************************************************************* + * @fn USART_ClockInit + * + * @brief Initializes the USARTx peripheral Clock according to the + * specified parameters in the USART_ClockInitStruct . + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef + * structure that contains the configuration information for the specified + * USART peripheral. + * + * @return none + */ +void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + uint32_t tmpreg = 0x00; + + tmpreg = USARTx->CTLR2; + tmpreg &= CTLR2_CLOCK_CLEAR_Mask; + tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | + USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; + USARTx->CTLR2 = (uint16_t)tmpreg; +} + +/********************************************************************* + * @fn USART_ClockStructInit + * + * @brief Fills each USART_ClockStructInit member with its default value. + * + * @param USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef + * structure which will be initialized. + * + * @return none + */ +void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; + USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; + USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; + USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; +} + +/********************************************************************* + * @fn USART_Cmd + * + * @brief Enables or disables the specified USART peripheral. + * reset values (Affects also the I2Ss). + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState: ENABLE or DISABLE. + * + * @return none + */ +void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_UE_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_UE_Reset; + } +} + +/********************************************************************* + * @fn USART_ITConfig + * + * @brief Enables or disables the specified USART interrupts. + * reset values (Affects also the I2Ss). + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_IT - specifies the USART interrupt sources to be enabled or disabled. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TXE - Transmit Data Register empty interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * USART_IT_IDLE - Idle line detection interrupt. + * USART_IT_PE - Parity Error interrupt. + * USART_IT_ERR - Error interrupt. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState) +{ + uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; + uint32_t usartxbase = 0x00; + + + usartxbase = (uint32_t)USARTx; + usartreg = (((uint8_t)USART_IT) >> 0x05); + itpos = USART_IT & IT_Mask; + itmask = (((uint32_t)0x01) << itpos); + + if(usartreg == 0x01) + { + usartxbase += 0x0C; + } + else if(usartreg == 0x02) + { + usartxbase += 0x10; + } + else + { + usartxbase += 0x14; + } + + if(NewState != DISABLE) + { + *(__IO uint32_t *)usartxbase |= itmask; + } + else + { + *(__IO uint32_t *)usartxbase &= ~itmask; + } +} + +/********************************************************************* + * @fn USART_DMACmd + * + * @brief Enables or disables the USART DMA interface. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_DMAReq - specifies the DMA request. + * USART_DMAReq_Tx - USART DMA transmit request. + * USART_DMAReq_Rx - USART DMA receive request. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= USART_DMAReq; + } + else + { + USARTx->CTLR3 &= (uint16_t)~USART_DMAReq; + } +} + +/********************************************************************* + * @fn USART_SetAddress + * + * @brief Sets the address of the USART node. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_Address - Indicates the address of the USART node. + * + * @return none + */ +void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address) +{ + USARTx->CTLR2 &= CTLR2_Address_Mask; + USARTx->CTLR2 |= USART_Address; +} + +/********************************************************************* + * @fn USART_WakeUpConfig + * + * @brief Selects the USART WakeUp method. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_WakeUp - specifies the USART wakeup method. + * USART_WakeUp_IdleLine - WakeUp by an idle line detection. + * USART_WakeUp_AddressMark - WakeUp by an address mark. + * + * @return none + */ +void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp) +{ + USARTx->CTLR1 &= CTLR1_WAKE_Mask; + USARTx->CTLR1 |= USART_WakeUp; +} + +/********************************************************************* + * @fn USART_ReceiverWakeUpCmd + * + * @brief Determines if the USART is in mute mode or not. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_RWU_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_RWU_Reset; + } +} + +/********************************************************************* + * @fn USART_LINBreakDetectLengthConfig + * + * @brief Sets the USART LIN Break detection length. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_LINBreakDetectLength - specifies the LIN break detection length. + * USART_LINBreakDetectLength_10b - 10-bit break detection. + * USART_LINBreakDetectLength_11b - 11-bit break detection. + * + * @return none + */ +void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength) +{ + USARTx->CTLR2 &= CTLR2_LBDL_Mask; + USARTx->CTLR2 |= USART_LINBreakDetectLength; +} + +/********************************************************************* + * @fn USART_LINCmd + * + * @brief Enables or disables the USART LIN mode. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR2 |= CTLR2_LINEN_Set; + } + else + { + USARTx->CTLR2 &= CTLR2_LINEN_Reset; + } +} + +/********************************************************************* + * @fn USART_SendData + * + * @brief Transmits single data through the USARTx peripheral. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * Data - the data to transmit. + * + * @return none + */ +void USART_SendData(USART_TypeDef *USARTx, uint16_t Data) +{ + USARTx->DATAR = (Data & (uint16_t)0x01FF); +} + +/********************************************************************* + * @fn USART_ReceiveData + * + * @brief Returns the most recent received data by the USARTx peripheral. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * + * @return The received data. + */ +uint16_t USART_ReceiveData(USART_TypeDef *USARTx) +{ + return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF); +} + +/********************************************************************* + * @fn USART_SendBreak + * + * @brief Transmits break characters. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * + * @return none + */ +void USART_SendBreak(USART_TypeDef *USARTx) +{ + USARTx->CTLR1 |= CTLR1_SBK_Set; +} + +/********************************************************************* + * @fn USART_SetGuardTime + * + * @brief Sets the specified USART guard time. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_GuardTime - specifies the guard time. + * + * @return none + */ +void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime) +{ + USARTx->GPR &= GPR_LSB_Mask; + USARTx->GPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); +} + +/********************************************************************* + * @fn USART_SetPrescaler + * + * @brief Sets the system clock prescaler. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_Prescaler - specifies the prescaler clock. + * + * @return none + */ +void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler) +{ + USARTx->GPR &= GPR_MSB_Mask; + USARTx->GPR |= USART_Prescaler; +} + +/********************************************************************* + * @fn USART_SmartCardCmd + * + * @brief Enables or disables the USART Smart Card mode. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_SCEN_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_SCEN_Reset; + } +} + +/********************************************************************* + * @fn USART_SmartCardNACKCmd + * + * @brief Enables or disables NACK transmission. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_NACK_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_NACK_Reset; + } +} + +/********************************************************************* + * @fn USART_HalfDuplexCmd + * + * @brief Enables or disables the USART Half Duplex communication. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_HDSEL_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_HDSEL_Reset; + } +} + +/********************************************************************* + * @fn USART_IrDAConfig + * + * @brief Configures the USART's IrDA interface. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_IrDAMode - specifies the IrDA mode. + * USART_IrDAMode_LowPower. + * USART_IrDAMode_Normal. + * + * @return none + */ +void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode) +{ + USARTx->CTLR3 &= CTLR3_IRLP_Mask; + USARTx->CTLR3 |= USART_IrDAMode; +} + +/********************************************************************* + * @fn USART_IrDACmd + * + * @brief Enables or disables the USART's IrDA interface. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_IREN_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_IREN_Reset; + } +} + +/********************************************************************* + * @fn USART_GetFlagStatus + * + * @brief Checks whether the specified USART flag is set or not. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_FLAG - specifies the flag to check. + * USART_FLAG_LBD - LIN Break detection flag. + * USART_FLAG_TXE - Transmit data register empty flag. + * USART_FLAG_TC - Transmission Complete flag. + * USART_FLAG_RXNE - Receive data register not empty flag. + * USART_FLAG_IDLE - Idle Line detection flag. + * USART_FLAG_ORE - OverRun Error flag. + * USART_FLAG_NE - Noise Error flag. + * USART_FLAG_FE - Framing Error flag. + * USART_FLAG_PE - Parity Error flag. + * + * @return bitstatus: SET or RESET + */ +FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + + + if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn USART_ClearFlag + * + * @brief Clears the USARTx's pending flags. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_FLAG - specifies the flag to clear. + * USART_FLAG_LBD - LIN Break detection flag. + * USART_FLAG_TC - Transmission Complete flag. + * USART_FLAG_RXNE - Receive data register not empty flag. + * Note- + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_STATR register (USART_GetFlagStatus()) + * followed by a read operation to USART_DATAR register (USART_ReceiveData()). + * - RXNE flag can be also cleared by a read to the USART_DATAR register + * (USART_ReceiveData()). + * - TC flag can be also cleared by software sequence: a read operation to + * USART_STATR register (USART_GetFlagStatus()) followed by a write operation + * to USART_DATAR register (USART_SendData()). + * - TXE flag is cleared only by a write to the USART_DATAR register + * (USART_SendData()). + * @return none + */ +void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG) +{ + + USARTx->STATR = (uint16_t)~USART_FLAG; +} + +/********************************************************************* + * @fn USART_GetITStatus + * + * @brief Checks whether the specified USART interrupt has occurred or not. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_IT - specifies the USART interrupt source to check. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TXE - Tansmit Data Register empty interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * USART_IT_IDLE - Idle line detection interrupt. + * USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set. + * USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set. + * USART_IT_NE - Noise Error interrupt. + * USART_IT_FE - Framing Error interrupt. + * USART_IT_PE - Parity Error interrupt. + * + * @return bitstatus: SET or RESET. + */ +ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT) +{ + uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; + ITStatus bitstatus = RESET; + + usartreg = (((uint8_t)USART_IT) >> 0x05); + itmask = USART_IT & IT_Mask; + itmask = (uint32_t)0x01 << itmask; + + if(usartreg == 0x01) + { + itmask &= USARTx->CTLR1; + } + else if(usartreg == 0x02) + { + itmask &= USARTx->CTLR2; + } + else + { + itmask &= USARTx->CTLR3; + } + + bitpos = USART_IT >> 0x08; + bitpos = (uint32_t)0x01 << bitpos; + bitpos &= USARTx->STATR; + + if((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn USART_ClearITPendingBit + * + * @brief Clears the USARTx's interrupt pending bits. + * + * @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral. + * USART_IT - specifies the interrupt pending bit to clear. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * Note- + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) pending bits are cleared by + * software sequence: a read operation to USART_STATR register + * (USART_GetITStatus()) followed by a read operation to USART_DATAR register + * (USART_ReceiveData()). + * - RXNE pending bit can be also cleared by a read to the USART_DATAR register + * (USART_ReceiveData()). + * - TC pending bit can be also cleared by software sequence: a read + * operation to USART_STATR register (USART_GetITStatus()) followed by a write + * operation to USART_DATAR register (USART_SendData()). + * - TXE pending bit is cleared only by a write to the USART_DATAR register + * (USART_SendData()). + * @return none + */ +void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT) +{ + uint16_t bitpos = 0x00, itmask = 0x00; + + bitpos = USART_IT >> 0x08; + itmask = ((uint16_t)0x01 << (uint16_t)bitpos); + USARTx->STATR = (uint16_t)~itmask; +} diff --git a/Code/DAP_X033/Peripheral/src/ch32x035_wwdg.c b/Code/DAP_X033/Peripheral/src/ch32x035_wwdg.c new file mode 100644 index 0000000..2d80561 --- /dev/null +++ b/Code/DAP_X033/Peripheral/src/ch32x035_wwdg.c @@ -0,0 +1,141 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_wwdg.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file provides all the WWDG firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_wwdg.h" +#include "ch32x035_rcc.h" + +/* CTLR register bit mask */ +#define CTLR_WDGA_Set ((uint32_t)0x00000080) + +/* CFGR register bit mask */ +#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) +#define CFGR_W_Mask ((uint32_t)0xFFFFFF80) +#define BIT_Mask ((uint8_t)0x7F) + +/********************************************************************* + * @fn WWDG_DeInit + * + * @brief Deinitializes the WWDG peripheral registers to their default reset values + * + * @return none + */ +void WWDG_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); +} + +/********************************************************************* + * @fn WWDG_SetPrescaler + * + * @brief Sets the WWDG Prescaler + * + * @param WWDG_Prescaler - specifies the WWDG Prescaler + * WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1 + * WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2 + * WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4 + * WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8 + * + * @return none + */ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) +{ + uint32_t tmpreg = 0; + tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask; + tmpreg |= WWDG_Prescaler; + WWDG->CFGR = tmpreg; +} + +/********************************************************************* + * @fn WWDG_SetWindowValue + * + * @brief Sets the WWDG window value + * + * @param WindowValue - specifies the window value to be compared to the + * downcounter,which must be lower than 0x80 + * + * @return none + */ +void WWDG_SetWindowValue(uint8_t WindowValue) +{ + __IO uint32_t tmpreg = 0; + + tmpreg = WWDG->CFGR & CFGR_W_Mask; + + tmpreg |= WindowValue & (uint32_t)BIT_Mask; + + WWDG->CFGR = tmpreg; +} + +/********************************************************************* + * @fn WWDG_EnableIT + * + * @brief Enables the WWDG Early Wakeup interrupt(EWI) + * + * @return none + */ +void WWDG_EnableIT(void) +{ + WWDG->CFGR |= (1 << 9); +} + +/********************************************************************* + * @fn WWDG_SetCounter + * + * @brief Sets the WWDG counter value + * + * @param Counter - specifies the watchdog counter value,which must be a + * number between 0x40 and 0x7F + * + * @return none + */ +void WWDG_SetCounter(uint8_t Counter) +{ + WWDG->CTLR = Counter & BIT_Mask; +} + +/********************************************************************* + * @fn WWDG_Enable + * + * @brief Enables WWDG and load the counter value + * + * @param Counter - specifies the watchdog counter value,which must be a + * number between 0x40 and 0x7F + * @return none + */ +void WWDG_Enable(uint8_t Counter) +{ + WWDG->CTLR = CTLR_WDGA_Set | Counter; +} + +/********************************************************************* + * @fn WWDG_GetFlagStatus + * + * @brief Checks whether the Early Wakeup interrupt flag is set or not + * + * @return The new state of the Early Wakeup interrupt flag (SET or RESET) + */ +FlagStatus WWDG_GetFlagStatus(void) +{ + return (FlagStatus)(WWDG->STATR); +} + +/********************************************************************* + * @fn WWDG_ClearFlag + * + * @brief Clears Early Wakeup interrupt flag + * + * @return none + */ +void WWDG_ClearFlag(void) +{ + WWDG->STATR = (uint32_t)RESET; +} diff --git a/Code/DAP_X033/Startup/startup_ch32x035.S b/Code/DAP_X033/Startup/startup_ch32x035.S new file mode 100644 index 0000000..94524bc --- /dev/null +++ b/Code/DAP_X033/Startup/startup_ch32x035.S @@ -0,0 +1,240 @@ +;/********************************** (C) COPYRIGHT ******************************* +;* File Name : startup_ch32x035.s +;* Author : WCH +;* Version : V1.0.0 +;* Date : 2023/04/06 +;* Description : vector table for eclipse toolchain. +;********************************************************************************* +;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +;* Attention: This software (modified or not) and binary are used for +;* microcontroller manufactured by Nanjing Qinheng Microelectronics. +;*******************************************************************************/ + + .section .init,"ax",@progbits + .global _start + .align 1 +_start: + j handle_reset + .section .vector,"ax",@progbits + .align 1 +_vector_base: + .option norvc; + .word _start + .word 0 + .word NMI_Handler /* NMI */ + .word HardFault_Handler /* Hard Fault */ + .word 0 + .word Ecall_M_Mode_Handler /* Ecall M Mode */ + .word 0 + .word 0 + .word Ecall_U_Mode_Handler /* Ecall U Mode */ + .word Break_Point_Handler /* Break Point */ + .word 0 + .word 0 + .word SysTick_Handler /* SysTick */ + .word 0 + .word SW_Handler /* SW */ + .word 0 + /* External Interrupts */ + .word WWDG_IRQHandler /* Window Watchdog */ + .word PVD_IRQHandler /* PVD through EXTI Line detect */ + .word FLASH_IRQHandler /* Flash */ + .word 0 + .word EXTI7_0_IRQHandler /* EXTI Line 7..0 */ + .word AWU_IRQHandler /* Auto Wake up */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word ADC1_IRQHandler /* ADC1 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word USART1_IRQHandler /* USART1 */ + .word SPI1_IRQHandler /* SPI1 */ + .word TIM1_BRK_IRQHandler /* TIM1 Break */ + .word TIM1_UP_IRQHandler /* TIM1 Update */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_UP_IRQHandler /* TIM2 Update */ + .word USART2_IRQHandler /* USART2 */ + .word EXTI15_8_IRQHandler /* EXTI Line 15..8 */ + .word EXTI25_16_IRQHandler /* EXTI Line 25..16 */ + .word USART3_IRQHandler /* USART3 */ + .word USART4_IRQHandler /* USART4 */ + .word DMA1_Channel8_IRQHandler /* DMA1 Channel8 */ + .word USBFS_IRQHandler /* USBFS Break */ + .word USBFSWakeUp_IRQHandler /* USBFS Wake up from suspend */ + .word PIOC_IRQHandler /* PIOC */ + .word OPA_IRQHandler /* OPA */ + .word USBPD_IRQHandler /* USBPD */ + .word USBPDWakeUp_IRQHandler /* USBPD Wake up */ + .word TIM2_CC_IRQHandler /* TIM2 Capture Compare */ + .word TIM2_TRG_COM_IRQHandler /* TIM2 Trigger and Commutation */ + .word TIM2_BRK_IRQHandler /* TIM2 Break */ + .word TIM3_IRQHandler /* TIM3 */ + + .option rvc; + + .section .text.vector_handler, "ax", @progbits + .weak NMI_Handler /* NMI */ + .weak HardFault_Handler /* Hard Fault */ + .weak Ecall_M_Mode_Handler /* Ecall M Mode */ + .weak Ecall_U_Mode_Handler /* Ecall U Mode */ + .weak Break_Point_Handler /* Break Point */ + .weak SysTick_Handler /* SysTick */ + .weak SW_Handler /* SW */ + .weak WWDG_IRQHandler /* Window Watchdog */ + .weak PVD_IRQHandler /* PVD through EXTI Line detect */ + .weak FLASH_IRQHandler /* Flash */ + .weak EXTI7_0_IRQHandler /* EXTI Line 7..0 */ + .weak AWU_IRQHandler /* Auto Wake up */ + .weak DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .weak DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .weak DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .weak DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .weak DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .weak DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .weak DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .weak ADC1_IRQHandler /* ADC1 */ + .weak I2C1_EV_IRQHandler /* I2C1 Event */ + .weak I2C1_ER_IRQHandler /* I2C1 Error */ + .weak USART1_IRQHandler /* USART1 */ + .weak SPI1_IRQHandler /* SPI1 */ + .weak TIM1_BRK_IRQHandler /* TIM1 Break */ + .weak TIM1_UP_IRQHandler /* TIM1 Update */ + .weak TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + .weak TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .weak TIM2_UP_IRQHandler /* TIM2 Update */ + .weak USART2_IRQHandler /* USART2 */ + .weak EXTI15_8_IRQHandler /* EXTI Line 15..8 */ + .weak EXTI25_16_IRQHandler /* EXTI Line 25..16 */ + .weak USART3_IRQHandler /* USART3 */ + .weak USART4_IRQHandler /* USART4 */ + .weak DMA1_Channel8_IRQHandler /* DMA1 Channel8 */ + .weak USBFS_IRQHandler /* USBFS Break */ + .weak USBFSWakeUp_IRQHandler /* USBFS Wake up from suspend */ + .weak PIOC_IRQHandler /* PIOC */ + .weak OPA_IRQHandler /* OPA */ + .weak USBPD_IRQHandler /* USBPD */ + .weak USBPDWakeUp_IRQHandler /* USBPD Wake up */ + .weak TIM2_CC_IRQHandler /* TIM2 Capture Compare */ + .weak TIM2_TRG_COM_IRQHandler /* TIM2 Trigger and Commutation */ + .weak TIM2_BRK_IRQHandler /* TIM2 Break */ + .weak TIM3_IRQHandler /* TIM3 */ + +NMI_Handler: 1: j 1b +HardFault_Handler: 1: j 1b +Ecall_M_Mode_Handler: 1: j 1b +Ecall_U_Mode_Handler: 1: j 1b +Break_Point_Handler: 1: j 1b +SysTick_Handler: 1: j 1b +SW_Handler: 1: j 1b +WWDG_IRQHandler: 1: j 1b +PVD_IRQHandler: 1: j 1b +FLASH_IRQHandler: 1: j 1b +EXTI7_0_IRQHandler: 1: j 1b +AWU_IRQHandler: 1: j 1b +DMA1_Channel1_IRQHandler: 1: j 1b +DMA1_Channel2_IRQHandler: 1: j 1b +DMA1_Channel3_IRQHandler: 1: j 1b +DMA1_Channel4_IRQHandler: 1: j 1b +DMA1_Channel5_IRQHandler: 1: j 1b +DMA1_Channel6_IRQHandler: 1: j 1b +DMA1_Channel7_IRQHandler: 1: j 1b +ADC1_IRQHandler: 1: j 1b +I2C1_EV_IRQHandler: 1: j 1b +I2C1_ER_IRQHandler: 1: j 1b +USART1_IRQHandler: 1: j 1b +SPI1_IRQHandler: 1: j 1b +TIM1_BRK_IRQHandler: 1: j 1b +TIM1_UP_IRQHandler: 1: j 1b +TIM1_TRG_COM_IRQHandler: 1: j 1b +TIM1_CC_IRQHandler: 1: j 1b +TIM2_UP_IRQHandler: 1: j 1b +USART2_IRQHandler: 1: j 1b +EXTI15_8_IRQHandler: 1: j 1b +EXTI25_16_IRQHandler: 1: j 1b +USART3_IRQHandler: 1: j 1b +USART4_IRQHandler: 1: j 1b +DMA1_Channel8_IRQHandler: 1: j 1b +USBFS_IRQHandler: 1: j 1b +USBFSWakeUp_IRQHandler: 1: j 1b +PIOC_IRQHandler: 1: j 1b +OPA_IRQHandler: 1: j 1b +USBPD_IRQHandler: 1: j 1b +USBPDWakeUp_IRQHandler: 1: j 1b +TIM2_CC_IRQHandler: 1: j 1b +TIM2_TRG_COM_IRQHandler: 1: j 1b +TIM2_BRK_IRQHandler: 1: j 1b +TIM3_IRQHandler: 1: j 1b + + .section .text.handle_reset,"ax",@progbits + .weak handle_reset + .align 1 +handle_reset: +.option push +.option norelax + la gp, __global_pointer$ +.option pop +1: + la sp, _eusrstack + +2: + /* Load data section from flash to RAM */ + la a0, _highcode_lma + la a1, _highcode_vma_start + la a2, _highcode_vma_end + bgeu a1, a2, 2f +1: + lw t0, (a0) + sw t0, (a1) + addi a0, a0, 4 + addi a1, a1, 4 + bltu a1, a2, 1b + +2: + /* Load data section from flash to RAM */ + la a0, _data_lma + la a1, _data_vma + la a2, _edata + bgeu a1, a2, 2f +1: + lw t0, (a0) + sw t0, (a1) + addi a0, a0, 4 + addi a1, a1, 4 + bltu a1, a2, 1b +2: + /* Clear bss section */ + la a0, _sbss + la a1, _ebss + bgeu a0, a1, 2f +1: + sw zero, (a0) + addi a0, a0, 4 + bltu a0, a1, 1b +2: + li t0, 0x1f + csrw 0xbc0, t0 + + /* Enable nested and hardware stack */ + li t0, 0x3 + csrw 0x804, t0 + + /* Enable interrupt */ + li t0, 0x88 + csrs mstatus, t0 + + la t0, _vector_base + ori t0, t0, 3 + csrw mtvec, t0 + + jal SystemInit + la t0, main + csrw mepc, t0 + mret + + diff --git a/Code/DAP_X033/User/ch32x035_conf.h b/Code/DAP_X033/User/ch32x035_conf.h new file mode 100644 index 0000000..996db41 --- /dev/null +++ b/Code/DAP_X033/User/ch32x035_conf.h @@ -0,0 +1,39 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_conf.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : Library configuration file. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_CONF_H +#define __CH32X035_CONF_H + +#include "ch32x035_adc.h" +#include "ch32x035_awu.h" +#include "ch32x035_dbgmcu.h" +#include "ch32x035_dma.h" +#include "ch32x035_exti.h" +#include "ch32x035_flash.h" +#include "ch32x035_gpio.h" +#include "ch32x035_i2c.h" +#include "ch32x035_iwdg.h" +#include "ch32x035_pwr.h" +#include "ch32x035_rcc.h" +#include "ch32x035_spi.h" +#include "ch32x035_tim.h" +#include "ch32x035_usart.h" +#include "ch32x035_wwdg.h" +#include "ch32x035_it.h" +#include "ch32x035_misc.h" + + +#endif + + + + + diff --git a/Code/DAP_X033/User/ch32x035_it.c b/Code/DAP_X033/User/ch32x035_it.c new file mode 100644 index 0000000..e4301bd --- /dev/null +++ b/Code/DAP_X033/User/ch32x035_it.c @@ -0,0 +1,42 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_it.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : Main Interrupt Service Routines. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035_it.h" + +void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); + +/********************************************************************* + * @fn NMI_Handler + * + * @brief This function handles NMI exception. + * + * @return none + */ +void NMI_Handler(void) +{ +} + +/********************************************************************* + * @fn HardFault_Handler + * + * @brief This function handles Hard Fault exception. + * + * @return none + */ +void HardFault_Handler(void) +{ + while (1) + { + } +} + + diff --git a/Code/DAP_X033/User/ch32x035_it.h b/Code/DAP_X033/User/ch32x035_it.h new file mode 100644 index 0000000..dbc1e9a --- /dev/null +++ b/Code/DAP_X033/User/ch32x035_it.h @@ -0,0 +1,20 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32x035_it.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : This file contains the headers of the interrupt handlers. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32X035_IT_H +#define __CH32X035_IT_H + +#include "ch32x035.h" + + +#endif + + diff --git a/Code/DAP_X033/User/main.c b/Code/DAP_X033/User/main.c new file mode 100644 index 0000000..b6fb980 --- /dev/null +++ b/Code/DAP_X033/User/main.c @@ -0,0 +1,29 @@ +#include "main.h" + +#include "dap_main.h" +#include "cdc_main.h" +#include "usb_desc.h" +#include "usart.h" +#include "led.h" + +int main(void) +{ + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); + SystemCoreClockUpdate(); + + DAP_Init(); + DAP_USB_Init(); + + CDC_Init(); + USART4_DMA_Init(); + USART4_Init(); + USART4_DMA_Recv(); + + LED_Init(); + + while (1) + { + DAP_Task(); + CDC_Task(); + } +} diff --git a/Code/DAP_X033/User/main.h b/Code/DAP_X033/User/main.h new file mode 100644 index 0000000..fabbd4c --- /dev/null +++ b/Code/DAP_X033/User/main.h @@ -0,0 +1,6 @@ +#ifndef _MAIN_H +#define _MAIN_H + +#include "ch32x035.h" + +#endif diff --git a/Code/DAP_X033/User/system_ch32x035.c b/Code/DAP_X033/User/system_ch32x035.c new file mode 100644 index 0000000..f6c364b --- /dev/null +++ b/Code/DAP_X033/User/system_ch32x035.c @@ -0,0 +1,241 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : system_ch32x035.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : CH32X035 Device Peripheral Access Layer System Source File. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32x035.h" + +/* +* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after +* reset the HSI is used as SYSCLK source). +*/ + +//#define SYSCLK_FREQ_8MHz_HSI 8000000 +//#define SYSCLK_FREQ_12MHz_HSI 12000000 +//#define SYSCLK_FREQ_16MHz_HSI 16000000 +//#define SYSCLK_FREQ_24MHz_HSI 24000000 +#define SYSCLK_FREQ_48MHz_HSI HSI_VALUE + +/* Clock Definitions */ +#ifdef SYSCLK_FREQ_8MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_8MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_12MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_12MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_16MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_16MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz_HSI; /* System Clock Frequency (Core Clock) */ +#else +uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */ + +#endif + +__I uint8_t AHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8}; + + +/* system_private_function_proto_types */ +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_8MHz_HSI +static void SetSysClockTo8_HSI( void ); +#elif defined SYSCLK_FREQ_12MHz_HSI +static void SetSysClockTo12_HSI( void ); +#elif defined SYSCLK_FREQ_16MHz_HSI +static void SetSysClockTo16_HSI( void ); +#elif defined SYSCLK_FREQ_24MHz_HSI +static void SetSysClockTo24_HSI( void ); +#elif defined SYSCLK_FREQ_48MHz_HSI +static void SetSysClockTo48_HSI( void ); + +#endif + +/********************************************************************* + * @fn SystemInit + * + * @brief Setup the microcontroller system Initialize the Embedded Flash Interface, + * update the SystemCoreClock variable. + * + * @return none + */ +void SystemInit (void) +{ + RCC->CTLR |= (uint32_t)0x00000001; + RCC->CFGR0 |= (uint32_t)0x00000050; + RCC->CFGR0 &= (uint32_t)0xF8FFFF5F; + SetSysClock(); +} + +/********************************************************************* + * @fn SystemCoreClockUpdate + * + * @brief Update SystemCoreClock variable according to Clock Register Values. + * + * @return none + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0; + + SystemCoreClock = HSI_VALUE; + tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)]; + + if(((RCC->CFGR0 & RCC_HPRE) >> 4) < 8) + { + SystemCoreClock /= tmp; + } + else + { + SystemCoreClock >>= tmp; + } +} + +/********************************************************************* + * @fn SetSysClock + * + * @brief Configures the System clock frequency, HCLK prescalers. + * + * @return none + */ +static void SetSysClock(void) +{ +// GPIO_IPD_Unused(); + +#ifdef SYSCLK_FREQ_8MHz_HSI + SetSysClockTo8_HSI(); +#elif defined SYSCLK_FREQ_12MHz_HSI + SetSysClockTo12_HSI(); +#elif defined SYSCLK_FREQ_16MHz_HSI + SetSysClockTo16_HSI(); +#elif defined SYSCLK_FREQ_24MHz_HSI + SetSysClockTo24_HSI(); +#elif defined SYSCLK_FREQ_48MHz_HSI + SetSysClockTo48_HSI(); + +#endif +} + + +#ifdef SYSCLK_FREQ_8MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo8_HSI + * + * @brief Sets HSE as System clock source and configure HCLK prescalers. + * + * @return none + */ +static void SetSysClockTo8_HSI(void) +{ + /* Flash 2 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; + + /* HCLK = SYSCLK = APB1 */ + RCC->CFGR0 &= (uint32_t)0xFFFFFF0F; + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV6; + + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; +} + +#elif defined SYSCLK_FREQ_12MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo12_HSI + * + * @brief Sets System clock frequency to 12MHz and configure HCLK prescalers. + * + * @return none + */ +static void SetSysClockTo12_HSI(void) +{ + /* Flash 2 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; + + /* HCLK = SYSCLK = APB1 */ + RCC->CFGR0 &= (uint32_t)0xFFFFFF0F; + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV4; + + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; +} + +#elif defined SYSCLK_FREQ_16MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo16_HSI + * + * @brief Sets System clock frequency to 16MHz and configure HCLK prescalers. + * + * @return none + */ +static void SetSysClockTo16_HSI(void) +{ + /* Flash 2 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; + + /* HCLK = SYSCLK = APB1 */ + RCC->CFGR0 &= (uint32_t)0xFFFFFF0F; + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV3; + + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1; +} + +#elif defined SYSCLK_FREQ_24MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo24_HSI + * + * @brief Sets System clock frequency to 24MHz and configure HCLK prescalers. + * + * @return none + */ +static void SetSysClockTo24_HSI(void) +{ + /* Flash 2 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; + + /* HCLK = SYSCLK = APB1 */ + RCC->CFGR0 &= (uint32_t)0xFFFFFF0F; + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2; + + /* Flash 1 wait state */ + FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1; +} + + +#elif defined SYSCLK_FREQ_48MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo48_HSI + * + * @brief Sets System clock frequency to 48MHz and configure HCLK prescalers. + * + * @return none + */ +static void SetSysClockTo48_HSI(void) +{ + /* Flash 2 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; + + /* HCLK = SYSCLK = APB1 */ + RCC->CFGR0 &= (uint32_t)0xFFFFFF0F; + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; +} + +#endif + diff --git a/Code/DAP_X033/User/system_ch32x035.h b/Code/DAP_X033/User/system_ch32x035.h new file mode 100644 index 0000000..c476797 --- /dev/null +++ b/Code/DAP_X033/User/system_ch32x035.h @@ -0,0 +1,32 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : system_ch32x035.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/04/06 + * Description : CH32X035 Device Peripheral Access Layer System Header File. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __SYSTEM_CH32X035_H +#define __SYSTEM_CH32X035_H + +#ifdef __cplusplus + extern "C" { +#endif + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/* System_Exported_Functions */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif + + + diff --git a/Code/DAP_X033/obj/Core/subdir.mk b/Code/DAP_X033/obj/Core/subdir.mk new file mode 100644 index 0000000..b87fbbb --- /dev/null +++ b/Code/DAP_X033/obj/Core/subdir.mk @@ -0,0 +1,21 @@ +################################################################################ +# MRS Version: 1.9.1 +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Core/core_riscv.c + +OBJS += \ +./Core/core_riscv.o + +C_DEPS += \ +./Core/core_riscv.d + + +# Each subdirectory must supply rules for building sources it contributes +Core/%.o: ../Core/%.c + @ @ riscv-none-elf-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -flto -Wunused -Wuninitialized -g -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\Core" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\User" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\Peripheral\inc" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\class\cdc" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\class\hid" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\common" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\core" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\port" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\DAP_Core" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + @ @ + diff --git a/Code/DAP_X033/obj/DAP/CherryUSB/class/cdc/subdir.mk b/Code/DAP_X033/obj/DAP/CherryUSB/class/cdc/subdir.mk new file mode 100644 index 0000000..e160462 --- /dev/null +++ b/Code/DAP_X033/obj/DAP/CherryUSB/class/cdc/subdir.mk @@ -0,0 +1,21 @@ +################################################################################ +# MRS Version: 1.9.1 +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../DAP/CherryUSB/class/cdc/usbd_cdc.c + +OBJS += \ +./DAP/CherryUSB/class/cdc/usbd_cdc.o + +C_DEPS += \ +./DAP/CherryUSB/class/cdc/usbd_cdc.d + + +# Each subdirectory must supply rules for building sources it contributes +DAP/CherryUSB/class/cdc/%.o: ../DAP/CherryUSB/class/cdc/%.c + @ @ riscv-none-elf-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -flto -Wunused -Wuninitialized -g -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\Core" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\User" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\Peripheral\inc" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\class\cdc" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\class\hid" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\common" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\core" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\port" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\DAP_Core" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + @ @ + diff --git a/Code/DAP_X033/obj/DAP/CherryUSB/class/hid/subdir.mk b/Code/DAP_X033/obj/DAP/CherryUSB/class/hid/subdir.mk new file mode 100644 index 0000000..f20e4a7 --- /dev/null +++ b/Code/DAP_X033/obj/DAP/CherryUSB/class/hid/subdir.mk @@ -0,0 +1,21 @@ +################################################################################ +# MRS Version: 1.9.1 +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../DAP/CherryUSB/class/hid/usbd_hid.c + +OBJS += \ +./DAP/CherryUSB/class/hid/usbd_hid.o + +C_DEPS += \ +./DAP/CherryUSB/class/hid/usbd_hid.d + + +# Each subdirectory must supply rules for building sources it contributes +DAP/CherryUSB/class/hid/%.o: ../DAP/CherryUSB/class/hid/%.c + @ @ riscv-none-elf-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -flto -Wunused -Wuninitialized -g -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\Core" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\User" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\Peripheral\inc" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\class\cdc" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\class\hid" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\common" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\core" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\port" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\DAP_Core" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + @ @ + diff --git a/Code/DAP_X033/obj/DAP/CherryUSB/core/subdir.mk b/Code/DAP_X033/obj/DAP/CherryUSB/core/subdir.mk new file mode 100644 index 0000000..ed481aa --- /dev/null +++ b/Code/DAP_X033/obj/DAP/CherryUSB/core/subdir.mk @@ -0,0 +1,21 @@ +################################################################################ +# MRS Version: 1.9.1 +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../DAP/CherryUSB/core/usbd_core.c + +OBJS += \ +./DAP/CherryUSB/core/usbd_core.o + +C_DEPS += \ +./DAP/CherryUSB/core/usbd_core.d + + +# Each subdirectory must supply rules for building sources it contributes +DAP/CherryUSB/core/%.o: ../DAP/CherryUSB/core/%.c + @ @ riscv-none-elf-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -flto -Wunused -Wuninitialized -g -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\Core" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\User" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\Peripheral\inc" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\class\cdc" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\class\hid" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\common" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\core" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\port" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\DAP_Core" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + @ @ + diff --git a/Code/DAP_X033/obj/DAP/CherryUSB/port/ch32/subdir.mk b/Code/DAP_X033/obj/DAP/CherryUSB/port/ch32/subdir.mk new file mode 100644 index 0000000..43f6df2 --- /dev/null +++ b/Code/DAP_X033/obj/DAP/CherryUSB/port/ch32/subdir.mk @@ -0,0 +1,21 @@ +################################################################################ +# MRS Version: 1.9.1 +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../DAP/CherryUSB/port/ch32/usb_ch58x_dc_usbfs.c + +OBJS += \ +./DAP/CherryUSB/port/ch32/usb_ch58x_dc_usbfs.o + +C_DEPS += \ +./DAP/CherryUSB/port/ch32/usb_ch58x_dc_usbfs.d + + +# Each subdirectory must supply rules for building sources it contributes +DAP/CherryUSB/port/ch32/%.o: ../DAP/CherryUSB/port/ch32/%.c + @ @ riscv-none-elf-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -flto -Wunused -Wuninitialized -g -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\Core" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\User" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\Peripheral\inc" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\class\cdc" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\class\hid" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\common" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\core" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\port" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\DAP_Core" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + @ @ + diff --git a/Code/DAP_X033/obj/DAP/DAP_Core/subdir.mk b/Code/DAP_X033/obj/DAP/DAP_Core/subdir.mk new file mode 100644 index 0000000..0b5baa5 --- /dev/null +++ b/Code/DAP_X033/obj/DAP/DAP_Core/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# MRS Version: 1.9.1 +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../DAP/DAP_Core/DAP.c \ +../DAP/DAP_Core/JTAG_DP.c \ +../DAP/DAP_Core/SW_DP.c + +OBJS += \ +./DAP/DAP_Core/DAP.o \ +./DAP/DAP_Core/JTAG_DP.o \ +./DAP/DAP_Core/SW_DP.o + +C_DEPS += \ +./DAP/DAP_Core/DAP.d \ +./DAP/DAP_Core/JTAG_DP.d \ +./DAP/DAP_Core/SW_DP.d + + +# Each subdirectory must supply rules for building sources it contributes +DAP/DAP_Core/%.o: ../DAP/DAP_Core/%.c + @ @ riscv-none-elf-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -flto -Wunused -Wuninitialized -g -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\Core" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\User" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\Peripheral\inc" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\class\cdc" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\class\hid" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\common" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\core" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\port" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\DAP_Core" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + @ @ + diff --git a/Code/DAP_X033/obj/DAP/subdir.mk b/Code/DAP_X033/obj/DAP/subdir.mk new file mode 100644 index 0000000..c4f613b --- /dev/null +++ b/Code/DAP_X033/obj/DAP/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# MRS Version: 1.9.1 +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../DAP/buffer.c \ +../DAP/cdc_main.c \ +../DAP/dap_main.c \ +../DAP/led.c \ +../DAP/usart.c \ +../DAP/usb_desc.c + +OBJS += \ +./DAP/buffer.o \ +./DAP/cdc_main.o \ +./DAP/dap_main.o \ +./DAP/led.o \ +./DAP/usart.o \ +./DAP/usb_desc.o + +C_DEPS += \ +./DAP/buffer.d \ +./DAP/cdc_main.d \ +./DAP/dap_main.d \ +./DAP/led.d \ +./DAP/usart.d \ +./DAP/usb_desc.d + + +# Each subdirectory must supply rules for building sources it contributes +DAP/%.o: ../DAP/%.c + @ @ riscv-none-elf-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -flto -Wunused -Wuninitialized -g -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\Core" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\User" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\Peripheral\inc" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\class\cdc" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\class\hid" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\common" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\core" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\port" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\DAP_Core" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + @ @ + diff --git a/Code/DAP_X033/obj/DAP_X033.elf b/Code/DAP_X033/obj/DAP_X033.elf new file mode 100644 index 0000000..3f0175c Binary files /dev/null and b/Code/DAP_X033/obj/DAP_X033.elf differ diff --git a/Code/DAP_X033/obj/DAP_X033.hex b/Code/DAP_X033/obj/DAP_X033.hex new file mode 100644 index 0000000..adbe3c8 --- /dev/null +++ b/Code/DAP_X033/obj/DAP_X033.hex @@ -0,0 +1,1373 @@ +:040000006F40D05726 +:100004000000000000000000083D00000C3D00005E +:1000140000000000264D0000000000000000000069 +:10002400284D00002A4D00000000000000000000E0 +:100034002C4D0000000000002E4D000000000000C8 +:10004400304D0000324D0000344D0000000000002F +:10005400364D0000384D00008C4C00003C4D000033 +:100064003E4D0000404D0000424D0000444D000054 +:10007400464D0000484D00004A4D00004C4D000024 +:100084004E4D0000504D0000524D0000544D0000F4 +:10009400564D0000584D00005A4D00005C4D0000C4 +:1000A4005E4D0000604D0000624D0000244C0000D5 +:1000B400E64C0000E44600006A4D00006C4D000070 +:1000C4006E4D0000704D0000724D0000744D000034 +:1000D400764D0000784D0000404B00000000000009 +:1000E400000000000000000000000000000000000C +:0C00F40000000000000000000000000000 +:10010000138701B8034EB7011433B71701402A888B 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+:105388000000000000000000000000000000000015 +:105398000000000000000000000000000000000005 +:1053A80000000000000000000000000000000000F5 +:1053B80000000000000000000000000000000000E5 +:1053C80000000000000000000000000000000000D5 +:1053D80000000000000000000000000000000000C5 +:1053E80000000000000000000000000000000000B5 +:1053F80000000000000000000000000000000000A5 +:105408000000000000000000000000000000000094 +:105418000000000000000000000000000000000084 +:105428000000000000000000000000000000000074 +:105438000000000000000000000000000000000064 +:105448000000000000000000000000000000000054 +:105458000000000000000000000000000000000044 +:105468000000000000000000000000000000000034 +:105478000000000000000000000000000000000024 +:105488000000000000000000000000000000000014 +:105498000000000000000000000000000000000004 +:1054A80000000000000000000000000000000000F4 +:1054B80000000000000000000000000000000000E4 +:1054C80000000000000000000000000000000000D4 +:1054D80000000000000000000000000000000000C4 +:1054E80000000000000000000000000000000000B4 +:1054F80000000000000000000000000000000000A4 +:105508000000000000000000000000000000000093 +:105518000000000000000000000000000000000083 +:105528000000000000000000000000000000000073 +:105538000000000000000000000000000000000063 +:105548000000000000000000000000000000000053 +:105558000000000000000000000000000000000043 +:105568000000000000000000000000000000000033 +:105578000000000000000000000000000000000023 +:105588000000000000000000000000000000000013 +:04559800000000000F +:00000001FF diff --git a/Code/DAP_X033/obj/Debug/subdir.mk b/Code/DAP_X033/obj/Debug/subdir.mk new file mode 100644 index 0000000..8c2e031 --- /dev/null +++ b/Code/DAP_X033/obj/Debug/subdir.mk @@ -0,0 +1,21 @@ +################################################################################ +# MRS Version: 1.9.1 +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Debug/debug.c + +OBJS += \ +./Debug/debug.o + +C_DEPS += \ +./Debug/debug.d + + +# Each subdirectory must supply rules for building sources it contributes +Debug/%.o: ../Debug/%.c + @ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"C:\Users\ASUS\Desktop\ylj\_git\DAP_X033\Code\DAP_X033\Debug" -I"C:\Users\ASUS\Desktop\ylj\_git\DAP_X033\Code\DAP_X033\Core" -I"C:\Users\ASUS\Desktop\ylj\_git\DAP_X033\Code\DAP_X033\User" -I"C:\Users\ASUS\Desktop\ylj\_git\DAP_X033\Code\DAP_X033\Peripheral\inc" -I"C:\Users\ASUS\Desktop\ylj\_git\DAP_X033\Code\DAP_X033\DAP\CherryUSB\class\cdc" -I"C:\Users\ASUS\Desktop\ylj\_git\DAP_X033\Code\DAP_X033\DAP\CherryUSB\class\hid" -I"C:\Users\ASUS\Desktop\ylj\_git\DAP_X033\Code\DAP_X033\DAP\CherryUSB\common" -I"C:\Users\ASUS\Desktop\ylj\_git\DAP_X033\Code\DAP_X033\DAP\CherryUSB\core" -I"C:\Users\ASUS\Desktop\ylj\_git\DAP_X033\Code\DAP_X033\DAP\CherryUSB\port" -I"C:\Users\ASUS\Desktop\ylj\_git\DAP_X033\Code\DAP_X033\DAP\CherryUSB" -I"C:\Users\ASUS\Desktop\ylj\_git\DAP_X033\Code\DAP_X033\DAP" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + @ @ + diff --git a/Code/DAP_X033/obj/Peripheral/src/subdir.mk b/Code/DAP_X033/obj/Peripheral/src/subdir.mk new file mode 100644 index 0000000..4d46dff --- /dev/null +++ b/Code/DAP_X033/obj/Peripheral/src/subdir.mk @@ -0,0 +1,69 @@ +################################################################################ +# MRS Version: 1.9.1 +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Peripheral/src/ch32x035_adc.c \ +../Peripheral/src/ch32x035_awu.c \ +../Peripheral/src/ch32x035_dbgmcu.c \ +../Peripheral/src/ch32x035_dma.c \ +../Peripheral/src/ch32x035_exti.c \ +../Peripheral/src/ch32x035_flash.c \ +../Peripheral/src/ch32x035_gpio.c \ +../Peripheral/src/ch32x035_i2c.c \ +../Peripheral/src/ch32x035_iwdg.c \ +../Peripheral/src/ch32x035_misc.c \ +../Peripheral/src/ch32x035_opa.c \ +../Peripheral/src/ch32x035_pwr.c \ +../Peripheral/src/ch32x035_rcc.c \ +../Peripheral/src/ch32x035_spi.c \ +../Peripheral/src/ch32x035_tim.c \ +../Peripheral/src/ch32x035_usart.c \ +../Peripheral/src/ch32x035_wwdg.c + +OBJS += \ +./Peripheral/src/ch32x035_adc.o \ +./Peripheral/src/ch32x035_awu.o \ +./Peripheral/src/ch32x035_dbgmcu.o \ +./Peripheral/src/ch32x035_dma.o \ +./Peripheral/src/ch32x035_exti.o \ +./Peripheral/src/ch32x035_flash.o \ +./Peripheral/src/ch32x035_gpio.o \ +./Peripheral/src/ch32x035_i2c.o \ +./Peripheral/src/ch32x035_iwdg.o \ +./Peripheral/src/ch32x035_misc.o \ +./Peripheral/src/ch32x035_opa.o \ +./Peripheral/src/ch32x035_pwr.o \ +./Peripheral/src/ch32x035_rcc.o \ +./Peripheral/src/ch32x035_spi.o \ +./Peripheral/src/ch32x035_tim.o \ +./Peripheral/src/ch32x035_usart.o \ +./Peripheral/src/ch32x035_wwdg.o + +C_DEPS += \ +./Peripheral/src/ch32x035_adc.d \ +./Peripheral/src/ch32x035_awu.d \ +./Peripheral/src/ch32x035_dbgmcu.d \ +./Peripheral/src/ch32x035_dma.d \ +./Peripheral/src/ch32x035_exti.d \ +./Peripheral/src/ch32x035_flash.d \ +./Peripheral/src/ch32x035_gpio.d \ +./Peripheral/src/ch32x035_i2c.d \ +./Peripheral/src/ch32x035_iwdg.d \ +./Peripheral/src/ch32x035_misc.d \ +./Peripheral/src/ch32x035_opa.d \ +./Peripheral/src/ch32x035_pwr.d \ +./Peripheral/src/ch32x035_rcc.d \ +./Peripheral/src/ch32x035_spi.d \ +./Peripheral/src/ch32x035_tim.d \ +./Peripheral/src/ch32x035_usart.d \ +./Peripheral/src/ch32x035_wwdg.d + + +# Each subdirectory must supply rules for building sources it contributes +Peripheral/src/%.o: ../Peripheral/src/%.c + @ @ riscv-none-elf-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -flto -Wunused -Wuninitialized -g -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\Core" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\User" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\Peripheral\inc" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\class\cdc" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\class\hid" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\common" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\core" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\port" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\DAP_Core" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + @ @ + diff --git a/Code/DAP_X033/obj/Startup/subdir.mk b/Code/DAP_X033/obj/Startup/subdir.mk new file mode 100644 index 0000000..d548090 --- /dev/null +++ b/Code/DAP_X033/obj/Startup/subdir.mk @@ -0,0 +1,21 @@ +################################################################################ +# MRS Version: 1.9.1 +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_UPPER_SRCS += \ +../Startup/startup_ch32x035.S + +OBJS += \ +./Startup/startup_ch32x035.o + +S_UPPER_DEPS += \ +./Startup/startup_ch32x035.d + + +# Each subdirectory must supply rules for building sources it contributes +Startup/%.o: ../Startup/%.S + @ @ riscv-none-elf-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -flto -Wunused -Wuninitialized -g -x assembler-with-cpp -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\Startup" -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + @ @ + diff --git a/Code/DAP_X033/obj/User/subdir.mk b/Code/DAP_X033/obj/User/subdir.mk new file mode 100644 index 0000000..6a91408 --- /dev/null +++ b/Code/DAP_X033/obj/User/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# MRS Version: 1.9.1 +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../User/ch32x035_it.c \ +../User/main.c \ +../User/system_ch32x035.c + +OBJS += \ +./User/ch32x035_it.o \ +./User/main.o \ +./User/system_ch32x035.o + +C_DEPS += \ +./User/ch32x035_it.d \ +./User/main.d \ +./User/system_ch32x035.d + + +# Each subdirectory must supply rules for building sources it contributes +User/%.o: ../User/%.c + @ @ riscv-none-elf-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -flto -Wunused -Wuninitialized -g -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\Core" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\User" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\Peripheral\inc" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\class\cdc" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\class\hid" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\common" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\core" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB\port" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\CherryUSB" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP" -I"C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\DAP\DAP_Core" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + @ @ + diff --git a/Code/DAP_X033/obj/makefile b/Code/DAP_X033/obj/makefile new file mode 100644 index 0000000..7917ad9 --- /dev/null +++ b/Code/DAP_X033/obj/makefile @@ -0,0 +1,80 @@ +################################################################################ +# MRS Version: 1.9.1 +# Automatically-generated file. Do not edit! +################################################################################ + +-include ../makefile.init + +RM := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include User/subdir.mk +-include Startup/subdir.mk +-include Peripheral/src/subdir.mk +-include DAP/DAP_Core/subdir.mk +-include DAP/CherryUSB/port/ch32/subdir.mk +-include DAP/CherryUSB/core/subdir.mk +-include DAP/CherryUSB/class/hid/subdir.mk +-include DAP/CherryUSB/class/cdc/subdir.mk +-include DAP/subdir.mk +-include Core/subdir.mk +-include subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(ASM_UPPER_DEPS)),) +-include $(ASM_UPPER_DEPS) +endif +ifneq ($(strip $(ASM_DEPS)),) +-include $(ASM_DEPS) +endif +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +SECONDARY_FLASH += \ +DAP_X033.hex \ + +SECONDARY_LIST += \ +DAP_X033.lst \ + +SECONDARY_SIZE += \ +DAP_X033.siz \ + + +# All Target +all: DAP_X033.elf secondary-outputs + +# Tool invocations +DAP_X033.elf: $(OBJS) $(USER_OBJS) + @ @ riscv-none-elf-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -flto -Wunused -Wuninitialized -g -T "C:\Users\ASUS\Desktop\ylj\_git\DAPLink_X033\Code\DAP_X033\Ld\Link.ld" -nostartfiles -Xlinker --gc-sections -Wl,-Map,"DAP_X033.map" --specs=nano.specs --specs=nosys.specs -o "DAP_X033.elf" $(OBJS) $(USER_OBJS) $(LIBS) + @ @ +DAP_X033.hex: DAP_X033.elf + @ riscv-none-elf-objcopy -O ihex "DAP_X033.elf" "DAP_X033.hex" + @ @ +DAP_X033.lst: DAP_X033.elf + @ riscv-none-elf-objdump --all-headers --demangle --disassemble -M xw "DAP_X033.elf" > "DAP_X033.lst" + @ @ +DAP_X033.siz: DAP_X033.elf + @ riscv-none-elf-size --format=berkeley "DAP_X033.elf" + @ @ +# Other Targets +clean: + -$(RM) $(ASM_UPPER_DEPS)$(OBJS)$(SECONDARY_FLASH)$(SECONDARY_LIST)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_DEPS)$(S_UPPER_DEPS)$(C_DEPS) DAP_X033.elf + -@ +secondary-outputs: $(SECONDARY_FLASH) $(SECONDARY_LIST) $(SECONDARY_SIZE) + +.PHONY: all clean dependents + +-include ../makefile.targets diff --git a/Code/DAP_X033/obj/objects.mk b/Code/DAP_X033/obj/objects.mk new file mode 100644 index 0000000..dde5d42 --- /dev/null +++ b/Code/DAP_X033/obj/objects.mk @@ -0,0 +1,9 @@ +################################################################################ +# MRS Version: 1.9.1 +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := + diff --git a/Code/DAP_X033/obj/sources.mk b/Code/DAP_X033/obj/sources.mk new file mode 100644 index 0000000..fc5a6c6 --- /dev/null +++ b/Code/DAP_X033/obj/sources.mk @@ -0,0 +1,36 @@ +################################################################################ +# MRS Version: 1.9.1 +# Automatically-generated file. Do not edit! +################################################################################ + +ELF_SRCS := +OBJ_SRCS := +S_SRCS := +ASM_UPPER_SRCS := +ASM_SRCS := +C_SRCS := +S_UPPER_SRCS := +O_SRCS := +ASM_UPPER_DEPS := +OBJS := +SECONDARY_FLASH := +SECONDARY_LIST := +SECONDARY_SIZE := +ASM_DEPS := +S_DEPS := +S_UPPER_DEPS := +C_DEPS := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +Core \ +DAP/CherryUSB/class/cdc \ +DAP/CherryUSB/class/hid \ +DAP/CherryUSB/core \ +DAP/CherryUSB/port/ch32 \ +DAP/DAP_Core \ +DAP \ +Peripheral/src \ +Startup \ +User \ +