infong/DAPLink_X033
1
0
Fork 0
mirror of https://github.com/ylj2000/DAPLink_X033.git synced 2026-09-26 22:16:11 +00:00
Code Issues Packages Projects Releases Wiki Activity

Update Code 20240526

Browse Source
This commit is contained in:
ylj
2024-05-26 21:22:26 +08:00
parent fefb4799b5
commit a432595606
5 changed files with 1342 additions and 1304 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Code/DAP_X033/.cproject
+1 -1
View File
@@ -148,5 +148,5 @@
</storageModule> </storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
<storageModule moduleId="refreshScope"/>
</cproject> </cproject>
Code/DAP_X033/DAP/DAP_Core/DAP_config.h
+36 -36
View File
@@ -327,12 +327,12 @@ __STATIC_INLINE void PORT_JTAG_SETUP (void) {
GPIOA->CFGLR|=0x08<<(4*3); GPIOA->CFGLR|=0x08<<(4*3);
GPIOA->BSHR=1<<3; GPIOA->BSHR=1<<3;
// if (DIR_IsEN == 1) if (DIR_IsEN == 1)
// { {
// GPIOA->CFGLR&=~(0x0F<<(4*5));//DIR,GPIOA5 GPIOA->CFGLR&=~(0x0F<<(4*5));//DIR,GPIOA5
// GPIOA->CFGLR|=0x03<<(4*5); GPIOA->CFGLR|=0x03<<(4*5);
// GPIOA->BCR=1<<5; GPIOA->BCR=1<<5;
// } }
} }
/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET. /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
@@ -355,12 +355,12 @@ __STATIC_INLINE void PORT_SWD_SETUP (void) {
GPIOA->CFGLR|=0x03<<(4*4); GPIOA->CFGLR|=0x03<<(4*4);
GPIOA->BSHR=1<<4; GPIOA->BSHR=1<<4;
// if (DIR_IsEN == 1) if (DIR_IsEN == 1)
// { {
// GPIOA->CFGLR&=~(0x0F<<(4*5));//DIR,GPIOA5 GPIOA->CFGLR&=~(0x0F<<(4*5));//DIR,GPIOA5
// GPIOA->CFGLR|=0x03<<(4*5); GPIOA->CFGLR|=0x03<<(4*5);
// GPIOA->BCR=1<<5; GPIOA->BCR=1<<5;
// } }
} }
/** Disable JTAG/SWD I/O Pins. /** Disable JTAG/SWD I/O Pins.
@@ -371,31 +371,31 @@ __STATIC_INLINE void PORT_OFF (void) {
RCC->APB2PCENR|=RCC_APB2Periph_GPIOA; RCC->APB2PCENR|=RCC_APB2Periph_GPIOA;
GPIOA->CFGHR&=~(0x0F<<(4*3));//CLK,GPIOA11 GPIOA->CFGHR&=~(0x0F<<(4*3));//CLK,GPIOA11
// GPIOA->CFGHR|=0x08<<(4*3); GPIOA->CFGHR|=0x08<<(4*3);
// GPIOA->BSHR=1<<11; GPIOA->BSHR=1<<11;
GPIOA->CFGHR&=~(0x0F<<(4*2));//DIO,GPIOA10 GPIOA->CFGHR&=~(0x0F<<(4*2));//DIO,GPIOA10
// GPIOA->CFGHR|=0x08<<(4*2); GPIOA->CFGHR|=0x08<<(4*2);
// GPIOA->BSHR=1<<10; GPIOA->BSHR=1<<10;
GPIOA->CFGLR&=~(0x0F<<(4*4));//RST,GPIOA4 GPIOA->CFGLR&=~(0x0F<<(4*4));//RST,GPIOA4
// GPIOA->CFGLR|=0x08<<(4*4); GPIOA->CFGLR|=0x08<<(4*4);
// GPIOA->BSHR=1<<4; GPIOA->BSHR=1<<4;
GPIOA->CFGLR&=~(0x0F<<(4*2));//TDI,GPIOA2 GPIOA->CFGLR&=~(0x0F<<(4*2));//TDI,GPIOA2
// GPIOA->CFGLR|=0x08<<(4*2); GPIOA->CFGLR|=0x08<<(4*2);
// GPIOA->BSHR=1<<2; GPIOA->BSHR=1<<2;
GPIOA->CFGLR&=~(0x0F<<(4*3));//TDO,GPIOA3 GPIOA->CFGLR&=~(0x0F<<(4*3));//TDO,GPIOA3
// GPIOA->CFGLR|=0x08<<(4*3); GPIOA->CFGLR|=0x08<<(4*3);
// GPIOA->BSHR=1<<3; GPIOA->BSHR=1<<3;
// if (DIR_IsEN == 1) if (DIR_IsEN == 1)
// { {
// GPIOA->CFGLR&=~(0x0F<<(4*5));//DIR,GPIOA5 GPIOA->CFGLR&=~(0x0F<<(4*5));//DIR,GPIOA5
// GPIOA->CFGLR|=0x08<<(4*5); GPIOA->CFGLR|=0x08<<(4*5);
// GPIOA->BSHR=1<<5; GPIOA->BSHR=1<<5;
// } }
} }
// SWCLK/TCK I/O pin ------------------------------------- // SWCLK/TCK I/O pin -------------------------------------
@@ -477,10 +477,10 @@ __STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE (void) {
GPIOA->CFGHR&=~(0x0F<<(4*2));//DIO,GPIOA10 GPIOA->CFGHR&=~(0x0F<<(4*2));//DIO,GPIOA10
GPIOA->CFGHR|=0x03<<(4*2); GPIOA->CFGHR|=0x03<<(4*2);
// if (DIR_IsEN == 1) if (DIR_IsEN == 1)
// { {
// GPIOA->BCR=1<<5;//DIR,GPIOA5 GPIOA->BCR=1<<5;//DIR,GPIOA5
// } }
} }
/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only). /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
@@ -491,10 +491,10 @@ __STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE (void) {
GPIOA->CFGHR&=~(0x0F<<(4*2));//DIO,GPIOA10 GPIOA->CFGHR&=~(0x0F<<(4*2));//DIO,GPIOA10
GPIOA->CFGHR|=0x08<<(4*2); GPIOA->CFGHR|=0x08<<(4*2);
// if (DIR_IsEN == 1) if (DIR_IsEN == 1)
// { {
// GPIOA->BSHR=1<<5;//DIR,GPIOA5 GPIOA->BSHR=1<<5;//DIR,GPIOA5
// } }
} }
Code/DAP_X033/DAP/dap_main.c
+26 -26
View File
@@ -61,32 +61,32 @@ void DAP_Init(void)
{ {
DAP_Setup(); DAP_Setup();
// RCC->APB2PCENR |= RCC_APB2Periph_GPIOA; RCC->APB2PCENR |= RCC_APB2Periph_GPIOA;
// GPIOA->CFGLR &= ~(0x0F << (4 * 5)); // DIR,GPIOA5 GPIOA->CFGLR &= ~(0x0F << (4 * 5)); // DIR,GPIOA5
// GPIOA->CFGLR |= 0x08 << (4 * 5); GPIOA->CFGLR |= 0x08 << (4 * 5);
// GPIOA->BCR = 1 << 5; GPIOA->BCR = 1 << 5;
//
// for (volatile uint32_t i = 0; i < 100; i++) for (volatile uint32_t i = 0; i < 100; i++)
// { {
// __NOP(); __NOP();
// } }
//
// uint8_t temp = (GPIOA->INDR >> 5) & 0x01; uint8_t temp = (GPIOA->INDR >> 5) & 0x01;
// if (temp == 0) if (temp == 0)
// { {
// DIR_IsEN = 1; DIR_IsEN = 1;
// } }
//
// if (DIR_IsEN == 0) if (DIR_IsEN == 0)
// { {
// GPIOA->CFGLR &= ~(0x0F << (4 * 5)); // DIR,GPIOA5 GPIOA->CFGLR &= ~(0x0F << (4 * 5)); // DIR,GPIOA5
// } }
// else else
// { {
// GPIOA->CFGLR &= ~(0x0F << (4 * 5)); // DIR,GPIOA5 GPIOA->CFGLR &= ~(0x0F << (4 * 5)); // DIR,GPIOA5
// GPIOA->CFGLR |= 0x03 << (4 * 5); GPIOA->CFGLR |= 0x03 << (4 * 5);
// GPIOA->BCR = 1 << 5; GPIOA->BCR = 1 << 5;
// } }
} }
void DAP_Task(void) void DAP_Task(void)
Code/DAP_X033/obj/DAP_X033.elf
BIN
View File
Binary file not shown.
Code/DAP_X033/obj/DAP_X033.hex
+1279 -1241
View File
File diff suppressed because it is too large Load Diff