mirror of
https://github.com/XIVN1987/DAPLink.git
synced 2026-09-27 14:36:22 +00:00
update CMSIS-DAP to v2.1.0
This commit is contained in:
XIVN1987
@@ -0,0 +1,561 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2021 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* ----------------------------------------------------------------------
|
||||
*
|
||||
* $Date: 16. June 2021
|
||||
* $Revision: V2.1.0
|
||||
*
|
||||
* Project: CMSIS-DAP Configuration
|
||||
* Title: DAP_config.h CMSIS-DAP Configuration File (Template)
|
||||
*
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef __DAP_CONFIG_H__
|
||||
#define __DAP_CONFIG_H__
|
||||
|
||||
|
||||
//**************************************************************************************************
|
||||
/**
|
||||
\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
|
||||
\ingroup DAP_ConfigIO_gr
|
||||
@{
|
||||
Provides definitions about the hardware and configuration of the Debug Unit.
|
||||
|
||||
This information includes:
|
||||
- Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
|
||||
- Debug Unit Identification strings (Vendor, Product, Serial Number).
|
||||
- Debug Unit communication packet size.
|
||||
- Debug Access Port supported modes and settings (JTAG/SWD and SWO).
|
||||
- Optional information about a connected Target Device (for Evaluation Boards).
|
||||
*/
|
||||
|
||||
#ifdef _RTE_
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
#else
|
||||
#include "device.h" // Debug Unit Cortex-M Processor Header File
|
||||
#endif
|
||||
|
||||
/// Processor Clock of the Cortex-M MCU used in the Debug Unit.
|
||||
/// This value is used to calculate the SWD/JTAG clock speed.
|
||||
#define CPU_CLOCK 100000000U ///< Specifies the CPU Clock in Hz.
|
||||
|
||||
/// Number of processor cycles for I/O Port write operations.
|
||||
/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
|
||||
/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
|
||||
/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses
|
||||
/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
|
||||
/// required.
|
||||
#define IO_PORT_WRITE_CYCLES 2U ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0.
|
||||
|
||||
/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
|
||||
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
|
||||
#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available.
|
||||
|
||||
/// Indicate that JTAG communication mode is available at the Debug Port.
|
||||
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
|
||||
#define DAP_JTAG 1 ///< JTAG Mode: 1 = available, 0 = not available.
|
||||
|
||||
/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
|
||||
/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
|
||||
#define DAP_JTAG_DEV_CNT 8U ///< Maximum number of JTAG devices on scan chain.
|
||||
|
||||
/// Default communication mode on the Debug Access Port.
|
||||
/// Used for the command \ref DAP_Connect when Port Default mode is selected.
|
||||
#define DAP_DEFAULT_PORT 1U ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
|
||||
|
||||
/// Default communication speed on the Debug Access Port for SWD and JTAG mode.
|
||||
/// Used to initialize the default SWD/JTAG clock frequency.
|
||||
/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
|
||||
#define DAP_DEFAULT_SWJ_CLOCK 1000000U ///< Default SWD/JTAG clock frequency in Hz.
|
||||
|
||||
/// Maximum Package Size for Command and Response data.
|
||||
/// This configuration settings is used to optimize the communication performance with the
|
||||
/// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or WinUSB,
|
||||
/// 1024 for High-speed USB HID and 512 for High-speed USB WinUSB.
|
||||
#define DAP_PACKET_SIZE 512U ///< Specifies Packet Size in bytes.
|
||||
|
||||
/// Maximum Package Buffers for Command and Response data.
|
||||
/// This configuration settings is used to optimize the communication performance with the
|
||||
/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
|
||||
/// setting can be reduced (valid range is 1 .. 255).
|
||||
#define DAP_PACKET_COUNT 8U ///< Specifies number of packets buffered.
|
||||
|
||||
/// Indicate that UART Serial Wire Output (SWO) trace is available.
|
||||
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
|
||||
#define SWO_UART 1 ///< SWO UART: 1 = available, 0 = not available.
|
||||
|
||||
/// USART Driver instance number for the UART SWO.
|
||||
#define SWO_UART_DRIVER 0 ///< USART Driver instance number (Driver_USART#).
|
||||
|
||||
/// Maximum SWO UART Baudrate.
|
||||
#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz.
|
||||
|
||||
/// Indicate that Manchester Serial Wire Output (SWO) trace is available.
|
||||
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
|
||||
#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available.
|
||||
|
||||
/// SWO Trace Buffer Size.
|
||||
#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n).
|
||||
|
||||
/// SWO Streaming Trace.
|
||||
#define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available.
|
||||
|
||||
/// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
|
||||
#define TIMESTAMP_CLOCK 100000000U ///< Timestamp clock in Hz (0 = timestamps not supported).
|
||||
|
||||
/// Indicate that UART Communication Port is available.
|
||||
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
|
||||
#define DAP_UART 1 ///< DAP UART: 1 = available, 0 = not available.
|
||||
|
||||
/// USART Driver instance number for the UART Communication Port.
|
||||
#define DAP_UART_DRIVER 1 ///< USART Driver instance number (Driver_USART#).
|
||||
|
||||
/// UART Receive Buffer Size.
|
||||
#define DAP_UART_RX_BUFFER_SIZE 1024U ///< Uart Receive Buffer Size in bytes (must be 2^n).
|
||||
|
||||
/// UART Transmit Buffer Size.
|
||||
#define DAP_UART_TX_BUFFER_SIZE 1024U ///< Uart Transmit Buffer Size in bytes (must be 2^n).
|
||||
|
||||
/// Indicate that UART Communication via USB COM Port is available.
|
||||
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
|
||||
#define DAP_UART_USB_COM_PORT 1 ///< USB COM Port: 1 = available, 0 = not available.
|
||||
|
||||
/// Debug Unit is connected to fixed Target Device.
|
||||
/// The Debug Unit may be part of an evaluation board and always connected to a fixed
|
||||
/// known device. In this case a Device Vendor, Device Name, Board Vendor and Board Name strings
|
||||
/// are stored and may be used by the debugger or IDE to configure device parameters.
|
||||
#define TARGET_FIXED 0 ///< Target: 1 = known, 0 = unknown;
|
||||
|
||||
#define TARGET_DEVICE_VENDOR "Arm" ///< String indicating the Silicon Vendor
|
||||
#define TARGET_DEVICE_NAME "Cortex-M" ///< String indicating the Target Device
|
||||
#define TARGET_BOARD_VENDOR "Arm" ///< String indicating the Board Vendor
|
||||
#define TARGET_BOARD_NAME "Arm board" ///< String indicating the Board Name
|
||||
|
||||
#if TARGET_FIXED != 0
|
||||
#include <string.h>
|
||||
static const char TargetDeviceVendor [] = TARGET_DEVICE_VENDOR;
|
||||
static const char TargetDeviceName [] = TARGET_DEVICE_NAME;
|
||||
static const char TargetBoardVendor [] = TARGET_BOARD_VENDOR;
|
||||
static const char TargetBoardName [] = TARGET_BOARD_NAME;
|
||||
#endif
|
||||
|
||||
/** Get Vendor Name string.
|
||||
\param str Pointer to buffer to store the string (max 60 characters).
|
||||
\return String length (including terminating NULL character) or 0 (no string).
|
||||
*/
|
||||
__STATIC_INLINE uint8_t DAP_GetVendorString (char *str) {
|
||||
(void)str;
|
||||
return (0U);
|
||||
}
|
||||
|
||||
/** Get Product Name string.
|
||||
\param str Pointer to buffer to store the string (max 60 characters).
|
||||
\return String length (including terminating NULL character) or 0 (no string).
|
||||
*/
|
||||
__STATIC_INLINE uint8_t DAP_GetProductString (char *str) {
|
||||
(void)str;
|
||||
return (0U);
|
||||
}
|
||||
|
||||
/** Get Serial Number string.
|
||||
\param str Pointer to buffer to store the string (max 60 characters).
|
||||
\return String length (including terminating NULL character) or 0 (no string).
|
||||
*/
|
||||
__STATIC_INLINE uint8_t DAP_GetSerNumString (char *str) {
|
||||
(void)str;
|
||||
return (0U);
|
||||
}
|
||||
|
||||
/** Get Target Device Vendor string.
|
||||
\param str Pointer to buffer to store the string (max 60 characters).
|
||||
\return String length (including terminating NULL character) or 0 (no string).
|
||||
*/
|
||||
__STATIC_INLINE uint8_t DAP_GetTargetDeviceVendorString (char *str) {
|
||||
#if TARGET_FIXED != 0
|
||||
uint8_t len;
|
||||
|
||||
strcpy(str, TargetDeviceVendor);
|
||||
len = (uint8_t)(strlen(TargetDeviceVendor) + 1U);
|
||||
return (len);
|
||||
#else
|
||||
(void)str;
|
||||
return (0U);
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Get Target Device Name string.
|
||||
\param str Pointer to buffer to store the string (max 60 characters).
|
||||
\return String length (including terminating NULL character) or 0 (no string).
|
||||
*/
|
||||
__STATIC_INLINE uint8_t DAP_GetTargetDeviceNameString (char *str) {
|
||||
#if TARGET_FIXED != 0
|
||||
uint8_t len;
|
||||
|
||||
strcpy(str, TargetDeviceName);
|
||||
len = (uint8_t)(strlen(TargetDeviceName) + 1U);
|
||||
return (len);
|
||||
#else
|
||||
(void)str;
|
||||
return (0U);
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Get Target Board Vendor string.
|
||||
\param str Pointer to buffer to store the string (max 60 characters).
|
||||
\return String length (including terminating NULL character) or 0 (no string).
|
||||
*/
|
||||
__STATIC_INLINE uint8_t DAP_GetTargetBoardVendorString (char *str) {
|
||||
#if TARGET_FIXED != 0
|
||||
uint8_t len;
|
||||
|
||||
strcpy(str, TargetBoardVendor);
|
||||
len = (uint8_t)(strlen(TargetBoardVendor) + 1U);
|
||||
return (len);
|
||||
#else
|
||||
(void)str;
|
||||
return (0U);
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Get Target Board Name string.
|
||||
\param str Pointer to buffer to store the string (max 60 characters).
|
||||
\return String length (including terminating NULL character) or 0 (no string).
|
||||
*/
|
||||
__STATIC_INLINE uint8_t DAP_GetTargetBoardNameString (char *str) {
|
||||
#if TARGET_FIXED != 0
|
||||
uint8_t len;
|
||||
|
||||
strcpy(str, TargetBoardName);
|
||||
len = (uint8_t)(strlen(TargetBoardName) + 1U);
|
||||
return (len);
|
||||
#else
|
||||
(void)str;
|
||||
return (0U);
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Get Product Firmware Version string.
|
||||
\param str Pointer to buffer to store the string (max 60 characters).
|
||||
\return String length (including terminating NULL character) or 0 (no string).
|
||||
*/
|
||||
__STATIC_INLINE uint8_t DAP_GetProductFirmwareVersionString (char *str) {
|
||||
(void)str;
|
||||
return (0U);
|
||||
}
|
||||
|
||||
///@}
|
||||
|
||||
|
||||
//**************************************************************************************************
|
||||
/**
|
||||
\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
|
||||
\ingroup DAP_ConfigIO_gr
|
||||
@{
|
||||
|
||||
Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
|
||||
and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
|
||||
interface of a device. The following I/O Pins are provided:
|
||||
|
||||
JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode
|
||||
---------------------------- | -------------------- | ---------------------------------------------
|
||||
TCK: Test Clock | SWCLK: Clock | Output Push/Pull
|
||||
TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data)
|
||||
TDI: Test Data Input | | Output Push/Pull
|
||||
TDO: Test Data Output | | Input
|
||||
nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor
|
||||
nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor
|
||||
|
||||
|
||||
DAP Hardware I/O Pin Access Functions
|
||||
-------------------------------------
|
||||
The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
|
||||
these I/O Pins.
|
||||
|
||||
For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
|
||||
This functions are provided to achieve faster I/O that is possible with some advanced GPIO
|
||||
peripherals that can independently write/read a single I/O pin without affecting any other pins
|
||||
of the same I/O port. The following SWDIO I/O Pin functions are provided:
|
||||
- \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
|
||||
- \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
|
||||
- \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
|
||||
- \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
|
||||
*/
|
||||
|
||||
|
||||
// Configure DAP I/O pins ------------------------------
|
||||
|
||||
/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
|
||||
Configures the DAP Hardware I/O pins for JTAG mode:
|
||||
- TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
|
||||
- TDO to input mode.
|
||||
*/
|
||||
__STATIC_INLINE void PORT_JTAG_SETUP (void) {
|
||||
;
|
||||
}
|
||||
|
||||
/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
|
||||
Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
|
||||
- SWCLK, SWDIO, nRESET to output mode and set to default high level.
|
||||
- TDI, nTRST to HighZ mode (pins are unused in SWD mode).
|
||||
*/
|
||||
__STATIC_INLINE void PORT_SWD_SETUP (void) {
|
||||
;
|
||||
}
|
||||
|
||||
/** Disable JTAG/SWD I/O Pins.
|
||||
Disables the DAP Hardware I/O pins which configures:
|
||||
- TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
|
||||
*/
|
||||
__STATIC_INLINE void PORT_OFF (void) {
|
||||
;
|
||||
}
|
||||
|
||||
|
||||
// SWCLK/TCK I/O pin -------------------------------------
|
||||
|
||||
/** SWCLK/TCK I/O pin: Get Input.
|
||||
\return Current status of the SWCLK/TCK DAP hardware I/O pin.
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN (void) {
|
||||
return (0U);
|
||||
}
|
||||
|
||||
/** SWCLK/TCK I/O pin: Set Output to High.
|
||||
Set the SWCLK/TCK DAP hardware I/O pin to high level.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET (void) {
|
||||
;
|
||||
}
|
||||
|
||||
/** SWCLK/TCK I/O pin: Set Output to Low.
|
||||
Set the SWCLK/TCK DAP hardware I/O pin to low level.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR (void) {
|
||||
;
|
||||
}
|
||||
|
||||
|
||||
// SWDIO/TMS Pin I/O --------------------------------------
|
||||
|
||||
/** SWDIO/TMS I/O pin: Get Input.
|
||||
\return Current status of the SWDIO/TMS DAP hardware I/O pin.
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN (void) {
|
||||
return (0U);
|
||||
}
|
||||
|
||||
/** SWDIO/TMS I/O pin: Set Output to High.
|
||||
Set the SWDIO/TMS DAP hardware I/O pin to high level.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET (void) {
|
||||
;
|
||||
}
|
||||
|
||||
/** SWDIO/TMS I/O pin: Set Output to Low.
|
||||
Set the SWDIO/TMS DAP hardware I/O pin to low level.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR (void) {
|
||||
;
|
||||
}
|
||||
|
||||
/** SWDIO I/O pin: Get Input (used in SWD mode only).
|
||||
\return Current status of the SWDIO DAP hardware I/O pin.
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN (void) {
|
||||
return (0U);
|
||||
}
|
||||
|
||||
/** SWDIO I/O pin: Set Output (used in SWD mode only).
|
||||
\param bit Output value for the SWDIO DAP hardware I/O pin.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void PIN_SWDIO_OUT (uint32_t bit) {
|
||||
;
|
||||
}
|
||||
|
||||
/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
|
||||
Configure the SWDIO DAP hardware I/O pin to output mode. This function is
|
||||
called prior \ref PIN_SWDIO_OUT function calls.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE (void) {
|
||||
;
|
||||
}
|
||||
|
||||
/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
|
||||
Configure the SWDIO DAP hardware I/O pin to input mode. This function is
|
||||
called prior \ref PIN_SWDIO_IN function calls.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE (void) {
|
||||
;
|
||||
}
|
||||
|
||||
|
||||
// TDI Pin I/O ---------------------------------------------
|
||||
|
||||
/** TDI I/O pin: Get Input.
|
||||
\return Current status of the TDI DAP hardware I/O pin.
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t PIN_TDI_IN (void) {
|
||||
return (0U);
|
||||
}
|
||||
|
||||
/** TDI I/O pin: Set Output.
|
||||
\param bit Output value for the TDI DAP hardware I/O pin.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void PIN_TDI_OUT (uint32_t bit) {
|
||||
;
|
||||
}
|
||||
|
||||
|
||||
// TDO Pin I/O ---------------------------------------------
|
||||
|
||||
/** TDO I/O pin: Get Input.
|
||||
\return Current status of the TDO DAP hardware I/O pin.
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t PIN_TDO_IN (void) {
|
||||
return (0U);
|
||||
}
|
||||
|
||||
|
||||
// nTRST Pin I/O -------------------------------------------
|
||||
|
||||
/** nTRST I/O pin: Get Input.
|
||||
\return Current status of the nTRST DAP hardware I/O pin.
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t PIN_nTRST_IN (void) {
|
||||
return (0U);
|
||||
}
|
||||
|
||||
/** nTRST I/O pin: Set Output.
|
||||
\param bit JTAG TRST Test Reset pin status:
|
||||
- 0: issue a JTAG TRST Test Reset.
|
||||
- 1: release JTAG TRST Test Reset.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void PIN_nTRST_OUT (uint32_t bit) {
|
||||
;
|
||||
}
|
||||
|
||||
// nRESET Pin I/O------------------------------------------
|
||||
|
||||
/** nRESET I/O pin: Get Input.
|
||||
\return Current status of the nRESET DAP hardware I/O pin.
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t PIN_nRESET_IN (void) {
|
||||
return (0U);
|
||||
}
|
||||
|
||||
/** nRESET I/O pin: Set Output.
|
||||
\param bit target device hardware reset pin status:
|
||||
- 0: issue a device hardware reset.
|
||||
- 1: release device hardware reset.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void PIN_nRESET_OUT (uint32_t bit) {
|
||||
;
|
||||
}
|
||||
|
||||
///@}
|
||||
|
||||
|
||||
//**************************************************************************************************
|
||||
/**
|
||||
\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
|
||||
\ingroup DAP_ConfigIO_gr
|
||||
@{
|
||||
|
||||
CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
|
||||
|
||||
It is recommended to provide the following LEDs for status indication:
|
||||
- Connect LED: is active when the DAP hardware is connected to a debugger.
|
||||
- Running LED: is active when the debugger has put the target device into running state.
|
||||
*/
|
||||
|
||||
/** Debug Unit: Set status of Connected LED.
|
||||
\param bit status of the Connect LED.
|
||||
- 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
|
||||
- 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
|
||||
*/
|
||||
__STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit) {}
|
||||
|
||||
/** Debug Unit: Set status Target Running LED.
|
||||
\param bit status of the Target Running LED.
|
||||
- 1: Target Running LED ON: program execution in target started.
|
||||
- 0: Target Running LED OFF: program execution in target stopped.
|
||||
*/
|
||||
__STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit) {}
|
||||
|
||||
///@}
|
||||
|
||||
|
||||
//**************************************************************************************************
|
||||
/**
|
||||
\defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
|
||||
\ingroup DAP_ConfigIO_gr
|
||||
@{
|
||||
Access function for Test Domain Timer.
|
||||
|
||||
The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
|
||||
default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
|
||||
|
||||
*/
|
||||
|
||||
/** Get timestamp of Test Domain Timer.
|
||||
\return Current timestamp value.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
|
||||
return (DWT->CYCCNT);
|
||||
}
|
||||
|
||||
///@}
|
||||
|
||||
|
||||
//**************************************************************************************************
|
||||
/**
|
||||
\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
|
||||
\ingroup DAP_ConfigIO_gr
|
||||
@{
|
||||
|
||||
CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
|
||||
*/
|
||||
|
||||
/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
|
||||
This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
|
||||
Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
|
||||
- I/O clock system enabled.
|
||||
- all I/O pins: input buffer enabled, output pins are set to HighZ mode.
|
||||
- for nTRST, nRESET a weak pull-up (if available) is enabled.
|
||||
- LED output pins are enabled and LEDs are turned off.
|
||||
*/
|
||||
__STATIC_INLINE void DAP_SETUP (void) {
|
||||
;
|
||||
}
|
||||
|
||||
/** Reset Target Device with custom specific I/O pin or command sequence.
|
||||
This function allows the optional implementation of a device specific reset sequence.
|
||||
It is called when the command \ref DAP_ResetTarget and is for example required
|
||||
when a device needs a time-critical unlock sequence that enables the debug port.
|
||||
\return 0 = no device specific reset sequence is implemented.\n
|
||||
1 = a device specific reset sequence is implemented.
|
||||
*/
|
||||
__STATIC_INLINE uint8_t RESET_TARGET (void) {
|
||||
return (0U); // change to '1' when a device reset sequence is implemented
|
||||
}
|
||||
|
||||
///@}
|
||||
|
||||
|
||||
#endif /* __DAP_CONFIG_H__ */
|
||||
@@ -1,7 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2020 ARM Limited. All rights reserved.
|
||||
* Copyright 2019, Cypress Semiconductor Corporation
|
||||
* or a subsidiary of Cypress Semiconductor Corporation.
|
||||
* Copyright (c) 2013-2021 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
@@ -19,8 +17,8 @@
|
||||
*
|
||||
* ----------------------------------------------------------------------
|
||||
*
|
||||
* $Date: 26. November 2019
|
||||
* $Revision: V2.0.0
|
||||
* $Date: 26. May 2021
|
||||
* $Revision: V2.1.0
|
||||
*
|
||||
* Project: CMSIS-DAP Include
|
||||
* Title: DAP.h Definitions
|
||||
@@ -33,9 +31,9 @@
|
||||
|
||||
// DAP Firmware Version
|
||||
#ifdef DAP_FW_V1
|
||||
#define DAP_FW_VER "1.2.0"
|
||||
#define DAP_FW_VER "1.3.0"
|
||||
#else
|
||||
#define DAP_FW_VER "2.0.0"
|
||||
#define DAP_FW_VER "2.1.0"
|
||||
#endif
|
||||
|
||||
// DAP Command IDs
|
||||
@@ -65,6 +63,11 @@
|
||||
#define ID_DAP_SWO_Status 0x1BU
|
||||
#define ID_DAP_SWO_ExtendedStatus 0x1EU
|
||||
#define ID_DAP_SWO_Data 0x1CU
|
||||
#define ID_DAP_UART_Transport 0x1FU
|
||||
#define ID_DAP_UART_Configure 0x20U
|
||||
#define ID_DAP_UART_Control 0x22U
|
||||
#define ID_DAP_UART_Status 0x23U
|
||||
#define ID_DAP_UART_Transfer 0x21U
|
||||
|
||||
#define ID_DAP_QueueCommands 0x7EU
|
||||
#define ID_DAP_ExecuteCommands 0x7FU
|
||||
@@ -103,11 +106,6 @@
|
||||
#define ID_DAP_Vendor30 0x9EU
|
||||
#define ID_DAP_Vendor31 0x9FU
|
||||
|
||||
// DAP Extended range of Vendor Command IDs
|
||||
|
||||
#define ID_DAP_VendorExFirst 0xA0U
|
||||
#define ID_DAP_VendorExLast 0xFEU
|
||||
|
||||
#define ID_DAP_Invalid 0xFFU
|
||||
|
||||
// DAP Status Code
|
||||
@@ -118,13 +116,16 @@
|
||||
#define DAP_ID_VENDOR 1U
|
||||
#define DAP_ID_PRODUCT 2U
|
||||
#define DAP_ID_SER_NUM 3U
|
||||
#define DAP_ID_CMSIS_DAP_VER 4U
|
||||
#define DAP_ID_FW_VER 4U // Deprecated alias of DAP_ID_CMSIS_DAP_VER for backwards compatibility.
|
||||
#define DAP_ID_DAP_FW_VER 4U
|
||||
#define DAP_ID_DEVICE_VENDOR 5U
|
||||
#define DAP_ID_DEVICE_NAME 6U
|
||||
#define DAP_ID_PRODUCT_FW_VER 7U
|
||||
#define DAP_ID_BOARD_VENDOR 7U
|
||||
#define DAP_ID_BOARD_NAME 8U
|
||||
#define DAP_ID_PRODUCT_FW_VER 9U
|
||||
#define DAP_ID_CAPABILITIES 0xF0U
|
||||
#define DAP_ID_TIMESTAMP_CLOCK 0xF1U
|
||||
#define DAP_ID_UART_RX_BUFFER_SIZE 0xFBU
|
||||
#define DAP_ID_UART_TX_BUFFER_SIZE 0xFCU
|
||||
#define DAP_ID_SWO_BUFFER_SIZE 0xFDU
|
||||
#define DAP_ID_PACKET_COUNT 0xFEU
|
||||
#define DAP_ID_PACKET_SIZE 0xFFU
|
||||
@@ -174,6 +175,30 @@
|
||||
#define DAP_SWO_STREAM_ERROR (1U<<6)
|
||||
#define DAP_SWO_BUFFER_OVERRUN (1U<<7)
|
||||
|
||||
// DAP UART Transport
|
||||
#define DAP_UART_TRANSPORT_NONE 0U
|
||||
#define DAP_UART_TRANSPORT_USB_COM_PORT 1U
|
||||
#define DAP_UART_TRANSPORT_DAP_COMMAND 2U
|
||||
|
||||
// DAP UART Control
|
||||
#define DAP_UART_CONTROL_RX_ENABLE (1U<<0)
|
||||
#define DAP_UART_CONTROL_RX_DISABLE (1U<<1)
|
||||
#define DAP_UART_CONTROL_RX_BUF_FLUSH (1U<<2)
|
||||
#define DAP_UART_CONTROL_TX_ENABLE (1U<<4)
|
||||
#define DAP_UART_CONTROL_TX_DISABLE (1U<<5)
|
||||
#define DAP_UART_CONTROL_TX_BUF_FLUSH (1U<<6)
|
||||
|
||||
// DAP UART Status
|
||||
#define DAP_UART_STATUS_RX_ENABLED (1U<<0)
|
||||
#define DAP_UART_STATUS_RX_DATA_LOST (1U<<1)
|
||||
#define DAP_UART_STATUS_FRAMING_ERROR (1U<<2)
|
||||
#define DAP_UART_STATUS_PARITY_ERROR (1U<<3)
|
||||
#define DAP_UART_STATUS_TX_ENABLED (1U<<4)
|
||||
|
||||
// DAP UART Configure Error
|
||||
#define DAP_UART_CFG_ERROR_DATA_BITS (1U<<0)
|
||||
#define DAP_UART_CFG_ERROR_PARITY (1U<<1)
|
||||
#define DAP_UART_CFG_ERROR_STOP_BITS (1U<<2)
|
||||
|
||||
// Debug Port Register Addresses
|
||||
#define DP_IDCODE 0x00U // IDCODE Register (SW Read only)
|
||||
@@ -271,17 +296,25 @@ extern void SWO_QueueTransfer (uint8_t *buf, uint32_t num);
|
||||
extern void SWO_AbortTransfer (void);
|
||||
extern void SWO_TransferComplete (void);
|
||||
|
||||
extern uint32_t UART_SWO_Mode (uint32_t enable);
|
||||
extern uint32_t UART_SWO_Baudrate (uint32_t baudrate);
|
||||
extern uint32_t UART_SWO_Control (uint32_t active);
|
||||
extern void UART_SWO_Capture (uint8_t *buf, uint32_t num);
|
||||
extern uint32_t UART_SWO_GetCount (void);
|
||||
extern uint32_t SWO_Mode_UART (uint32_t enable);
|
||||
extern uint32_t SWO_Baudrate_UART (uint32_t baudrate);
|
||||
extern uint32_t SWO_Control_UART (uint32_t active);
|
||||
extern void SWO_Capture_UART (uint8_t *buf, uint32_t num);
|
||||
extern uint32_t SWO_GetCount_UART (void);
|
||||
|
||||
extern uint32_t Manchester_SWO_Mode (uint32_t enable);
|
||||
extern uint32_t Manchester_SWO_Baudrate (uint32_t baudrate);
|
||||
extern uint32_t Manchester_SWO_Control (uint32_t active);
|
||||
extern void Manchester_SWO_Capture (uint8_t *buf, uint32_t num);
|
||||
extern uint32_t Manchester_SWO_GetCount (void);
|
||||
extern uint32_t SWO_Mode_Manchester (uint32_t enable);
|
||||
extern uint32_t SWO_Baudrate_Manchester (uint32_t baudrate);
|
||||
extern uint32_t SWO_Control_Manchester (uint32_t active);
|
||||
extern void SWO_Capture_Manchester (uint8_t *buf, uint32_t num);
|
||||
extern uint32_t SWO_GetCount_Manchester (void);
|
||||
|
||||
extern uint32_t UART_Transport (const uint8_t *request, uint8_t *response);
|
||||
extern uint32_t UART_Configure (const uint8_t *request, uint8_t *response);
|
||||
extern uint32_t UART_Control (const uint8_t *request, uint8_t *response);
|
||||
extern uint32_t UART_Status (uint8_t *response);
|
||||
extern uint32_t UART_Transfer (const uint8_t *request, uint8_t *response);
|
||||
|
||||
extern uint8_t USB_COM_PORT_Activate (uint32_t cmd);
|
||||
|
||||
extern uint32_t DAP_ProcessVendorCommand (const uint8_t *request, uint8_t *response);
|
||||
extern uint32_t DAP_ProcessCommand (const uint8_t *request, uint8_t *response);
|
||||
@@ -1,7 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2020 ARM Limited. All rights reserved.
|
||||
* Copyright 2019, Cypress Semiconductor Corporation
|
||||
* or a subsidiary of Cypress Semiconductor Corporation.
|
||||
* Copyright (c) 2013-2021 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
@@ -19,8 +17,8 @@
|
||||
*
|
||||
* ----------------------------------------------------------------------
|
||||
*
|
||||
* $Date: 1. December 2017
|
||||
* $Revision: V2.0.0
|
||||
* $Date: 16. June 2021
|
||||
* $Revision: V2.1.0
|
||||
*
|
||||
* Project: CMSIS-DAP Source
|
||||
* Title: DAP.c CMSIS-DAP Commands
|
||||
@@ -28,13 +26,8 @@
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
#include <string.h>
|
||||
#ifdef RTE_CMSIS_RTOS
|
||||
#include "cmsis_os.h"
|
||||
#endif
|
||||
#include "DAP_config.h"
|
||||
#include "DAP.h"
|
||||
//#include "info.h"
|
||||
//#include "dap_strings.h"
|
||||
|
||||
|
||||
#if (DAP_PACKET_SIZE < 64U)
|
||||
@@ -66,10 +59,6 @@ volatile uint8_t DAP_TransferAbort; // Transfer Abort Flag
|
||||
|
||||
static const char DAP_FW_Ver [] = DAP_FW_VER;
|
||||
|
||||
#if TARGET_DEVICE_FIXED
|
||||
static const char TargetDeviceVendor [] = TARGET_DEVICE_VENDOR;
|
||||
static const char TargetDeviceName [] = TARGET_DEVICE_NAME;
|
||||
#endif
|
||||
|
||||
|
||||
// Get DAP Information
|
||||
@@ -89,24 +78,24 @@ static uint8_t DAP_Info(uint8_t id, uint8_t *info) {
|
||||
case DAP_ID_SER_NUM:
|
||||
length = DAP_GetSerNumString((char *)info);
|
||||
break;
|
||||
case DAP_ID_CMSIS_DAP_VER:
|
||||
case DAP_ID_DAP_FW_VER:
|
||||
length = (uint8_t)sizeof(DAP_FW_Ver);
|
||||
memcpy(info, DAP_FW_Ver, length);
|
||||
break;
|
||||
case DAP_ID_DEVICE_VENDOR:
|
||||
#if TARGET_DEVICE_FIXED
|
||||
length = (uint8_t)sizeof(TargetDeviceVendor);
|
||||
memcpy(info, TargetDeviceVendor, length);
|
||||
#endif
|
||||
length = DAP_GetTargetDeviceVendorString((char *)info);
|
||||
break;
|
||||
case DAP_ID_DEVICE_NAME:
|
||||
#if TARGET_DEVICE_FIXED
|
||||
length = (uint8_t)sizeof(TargetDeviceName);
|
||||
memcpy(info, TargetDeviceName, length);
|
||||
#endif
|
||||
length = DAP_GetTargetDeviceNameString((char *)info);
|
||||
break;
|
||||
case DAP_ID_BOARD_VENDOR:
|
||||
length = DAP_GetTargetBoardVendorString((char *)info);
|
||||
break;
|
||||
case DAP_ID_BOARD_NAME:
|
||||
length = DAP_GetTargetBoardNameString((char *)info);
|
||||
break;
|
||||
case DAP_ID_PRODUCT_FW_VER:
|
||||
length = DAP_ProductFirmwareVerString((char *)info);
|
||||
length = DAP_GetProductFirmwareVersionString((char *)info);
|
||||
break;
|
||||
case DAP_ID_CAPABILITIES:
|
||||
info[0] = ((DAP_SWD != 0) ? (1U << 0) : 0U) |
|
||||
@@ -115,16 +104,37 @@ static uint8_t DAP_Info(uint8_t id, uint8_t *info) {
|
||||
((SWO_MANCHESTER != 0) ? (1U << 3) : 0U) |
|
||||
/* Atomic Commands */ (1U << 4) |
|
||||
((TIMESTAMP_CLOCK != 0U) ? (1U << 5) : 0U) |
|
||||
((SWO_STREAM != 0U) ? (1U << 6) : 0U);
|
||||
length = 1U;
|
||||
((SWO_STREAM != 0U) ? (1U << 6) : 0U) |
|
||||
((DAP_UART != 0U) ? (1U << 7) : 0U);
|
||||
|
||||
info[1] = ((DAP_UART_USB_COM_PORT != 0) ? (1U << 0) : 0U);
|
||||
length = 2U;
|
||||
break;
|
||||
case DAP_ID_TIMESTAMP_CLOCK:
|
||||
#if (TIMESTAMP_CLOCK != 0U)
|
||||
#if (TIMESTAMP_CLOCK != 0U)
|
||||
info[0] = (uint8_t)(TIMESTAMP_CLOCK >> 0);
|
||||
info[1] = (uint8_t)(TIMESTAMP_CLOCK >> 8);
|
||||
info[2] = (uint8_t)(TIMESTAMP_CLOCK >> 16);
|
||||
info[3] = (uint8_t)(TIMESTAMP_CLOCK >> 24);
|
||||
length = 4U;
|
||||
#endif
|
||||
break;
|
||||
case DAP_ID_UART_RX_BUFFER_SIZE:
|
||||
#if (DAP_UART != 0)
|
||||
info[0] = (uint8_t)(DAP_UART_RX_BUFFER_SIZE >> 0);
|
||||
info[1] = (uint8_t)(DAP_UART_RX_BUFFER_SIZE >> 8);
|
||||
info[2] = (uint8_t)(DAP_UART_RX_BUFFER_SIZE >> 16);
|
||||
info[3] = (uint8_t)(DAP_UART_RX_BUFFER_SIZE >> 24);
|
||||
length = 4U;
|
||||
#endif
|
||||
break;
|
||||
case DAP_ID_UART_TX_BUFFER_SIZE:
|
||||
#if (DAP_UART != 0)
|
||||
info[0] = (uint8_t)(DAP_UART_TX_BUFFER_SIZE >> 0);
|
||||
info[1] = (uint8_t)(DAP_UART_TX_BUFFER_SIZE >> 8);
|
||||
info[2] = (uint8_t)(DAP_UART_TX_BUFFER_SIZE >> 16);
|
||||
info[3] = (uint8_t)(DAP_UART_TX_BUFFER_SIZE >> 24);
|
||||
length = 4U;
|
||||
#endif
|
||||
break;
|
||||
case DAP_ID_SWO_BUFFER_SIZE:
|
||||
@@ -217,7 +227,7 @@ static uint32_t DAP_Connect(const uint8_t *request, uint8_t *response) {
|
||||
} else {
|
||||
port = *request;
|
||||
}
|
||||
|
||||
|
||||
switch (port) {
|
||||
#if (DAP_SWD != 0)
|
||||
case DAP_PORT_SWD:
|
||||
@@ -276,9 +286,9 @@ static uint32_t DAP_SWJ_Pins(const uint8_t *request, uint8_t *response) {
|
||||
uint32_t select;
|
||||
uint32_t wait;
|
||||
uint32_t timestamp;
|
||||
|
||||
|
||||
value = (uint32_t) *(request+0);
|
||||
select = (uint32_t) *(request+1);
|
||||
select = (uint32_t) *(request+1);
|
||||
wait = (uint32_t)(*(request+2) << 0) |
|
||||
(uint32_t)(*(request+3) << 8) |
|
||||
(uint32_t)(*(request+4) << 16) |
|
||||
@@ -310,7 +320,7 @@ static uint32_t DAP_SWJ_Pins(const uint8_t *request, uint8_t *response) {
|
||||
|
||||
if (wait != 0U) {
|
||||
#if (TIMESTAMP_CLOCK != 0U)
|
||||
if (wait > 3000000U) {
|
||||
if (wait > 3000000U) {
|
||||
wait = 3000000U;
|
||||
}
|
||||
#if (TIMESTAMP_CLOCK >= 1000000U)
|
||||
@@ -423,7 +433,7 @@ static uint32_t DAP_SWJ_Sequence(const uint8_t *request, uint8_t *response) {
|
||||
uint32_t count;
|
||||
|
||||
count = *request++;
|
||||
if (count == 0U) {
|
||||
if (count == 0U) {
|
||||
count = 256U;
|
||||
}
|
||||
|
||||
@@ -452,7 +462,7 @@ static uint32_t DAP_SWD_Configure(const uint8_t *request, uint8_t *response) {
|
||||
value = *request;
|
||||
DAP_Data.swd_conf.turnaround = (value & 0x03U) + 1U;
|
||||
DAP_Data.swd_conf.data_phase = (value & 0x04U) ? 1U : 0U;
|
||||
|
||||
|
||||
*response = DAP_OK;
|
||||
#else
|
||||
*response = DAP_ERROR;
|
||||
@@ -486,7 +496,7 @@ static uint32_t DAP_SWD_Sequence(const uint8_t *request, uint8_t *response) {
|
||||
while (sequence_count--) {
|
||||
sequence_info = *request++;
|
||||
count = sequence_info & SWD_SEQUENCE_CLK;
|
||||
if (count == 0U) {
|
||||
if (count == 0U) {
|
||||
count = 64U;
|
||||
}
|
||||
count = (count + 7U) / 8U;
|
||||
@@ -636,7 +646,7 @@ static uint32_t DAP_JTAG_IDCode(const uint8_t *request, uint8_t *response) {
|
||||
id_error:
|
||||
#endif
|
||||
*response = DAP_ERROR;
|
||||
return ((1U << 16) | 1U);
|
||||
return ((1U << 16) | 1U);
|
||||
}
|
||||
|
||||
|
||||
@@ -650,11 +660,11 @@ static uint32_t DAP_TransferConfigure(const uint8_t *request, uint8_t *response)
|
||||
DAP_Data.transfer.idle_cycles = *(request+0);
|
||||
DAP_Data.transfer.retry_count = (uint16_t) *(request+1) |
|
||||
(uint16_t)(*(request+2) << 8);
|
||||
DAP_Data.transfer.match_retry = (uint16_t) *(request+3) |
|
||||
DAP_Data.transfer.match_retry = (uint16_t) *(request+3) |
|
||||
(uint16_t)(*(request+4) << 8);
|
||||
|
||||
*response = DAP_OK;
|
||||
return ((5U << 16) | 1U);
|
||||
return ((5U << 16) | 1U);
|
||||
}
|
||||
|
||||
|
||||
@@ -717,7 +727,7 @@ static uint32_t DAP_SWD_Transfer(const uint8_t *request, uint8_t *response) {
|
||||
} while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);
|
||||
post_read = 0U;
|
||||
}
|
||||
if (response_value != DAP_TRANSFER_OK) {
|
||||
if (response_value != DAP_TRANSFER_OK) {
|
||||
break;
|
||||
}
|
||||
// Store previous AP data
|
||||
@@ -1392,14 +1402,14 @@ static uint32_t DAP_JTAG_TransferBlock(const uint8_t *request, uint8_t *response
|
||||
|
||||
// Device index (JTAP TAP)
|
||||
DAP_Data.jtag_dev.index = *request++;
|
||||
if (DAP_Data.jtag_dev.index >= DAP_Data.jtag_dev.count) {
|
||||
if (DAP_Data.jtag_dev.index >= DAP_Data.jtag_dev.count) {
|
||||
goto end;
|
||||
}
|
||||
|
||||
request_count = (uint32_t)(*(request+0) << 0) |
|
||||
request_count = (uint32_t)(*(request+0) << 0) |
|
||||
(uint32_t)(*(request+1) << 8);
|
||||
request += 2;
|
||||
if (request_count == 0U) {
|
||||
if (request_count == 0U) {
|
||||
goto end;
|
||||
}
|
||||
|
||||
@@ -1555,7 +1565,7 @@ static uint32_t DAP_JTAG_WriteAbort(const uint8_t *request, uint8_t *response) {
|
||||
DAP_Data.jtag_dev.index = *request;
|
||||
if (DAP_Data.jtag_dev.index >= DAP_Data.jtag_dev.count) {
|
||||
*response = DAP_ERROR;
|
||||
return (1U);
|
||||
return (1U);
|
||||
}
|
||||
|
||||
// Select JTAG chain
|
||||
@@ -1571,7 +1581,7 @@ static uint32_t DAP_JTAG_WriteAbort(const uint8_t *request, uint8_t *response) {
|
||||
JTAG_WriteAbort(data);
|
||||
|
||||
*response = DAP_OK;
|
||||
return (1U);
|
||||
return (1U);
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -1616,16 +1626,6 @@ __WEAK uint32_t DAP_ProcessVendorCommand(const uint8_t *request, uint8_t *respon
|
||||
return ((1U << 16) | 1U);
|
||||
}
|
||||
|
||||
// Process DAP Vendor extended command request and prepare response
|
||||
// Default function (can be overridden)
|
||||
// request: pointer to request data
|
||||
// response: pointer to response data
|
||||
// return: number of bytes in response (lower 16 bits)
|
||||
// number of bytes in request (upper 16 bits)
|
||||
__WEAK uint32_t DAP_ProcessVendorCommandEx(const uint8_t *request, uint8_t *response) {
|
||||
*response = ID_DAP_Invalid;
|
||||
return ((1U << 16) | 1U);
|
||||
}
|
||||
|
||||
// Process DAP command request and prepare response
|
||||
// request: pointer to request data
|
||||
@@ -1639,10 +1639,6 @@ uint32_t DAP_ProcessCommand(const uint8_t *request, uint8_t *response) {
|
||||
return DAP_ProcessVendorCommand(request, response);
|
||||
}
|
||||
|
||||
if ((*request >= ID_DAP_VendorExFirst) && (*request <= ID_DAP_VendorExLast)) {
|
||||
return DAP_ProcessVendorCommandEx(request, response);
|
||||
}
|
||||
|
||||
*response++ = *request;
|
||||
|
||||
switch (*request++) {
|
||||
@@ -1735,6 +1731,24 @@ uint32_t DAP_ProcessCommand(const uint8_t *request, uint8_t *response) {
|
||||
break;
|
||||
#endif
|
||||
|
||||
#if (DAP_UART != 0)
|
||||
case ID_DAP_UART_Transport:
|
||||
num = UART_Transport(request, response);
|
||||
break;
|
||||
case ID_DAP_UART_Configure:
|
||||
num = UART_Configure(request, response);
|
||||
break;
|
||||
case ID_DAP_UART_Control:
|
||||
num = UART_Control(request, response);
|
||||
break;
|
||||
case ID_DAP_UART_Status:
|
||||
num = UART_Status(response);
|
||||
break;
|
||||
case ID_DAP_UART_Transfer:
|
||||
num = UART_Transfer(request, response);
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
*(response-1) = ID_DAP_Invalid;
|
||||
return ((1U << 16) | 1U);
|
||||
@@ -1761,7 +1775,7 @@ uint32_t DAP_ExecuteCommand(const uint8_t *request, uint8_t *response) {
|
||||
n = DAP_ProcessCommand(request, response);
|
||||
num += n;
|
||||
request += (uint16_t)(n >> 16);
|
||||
response += (uint16_t) n;
|
||||
response += (uint16_t) n;
|
||||
}
|
||||
return (num);
|
||||
}
|
||||
@@ -1775,6 +1789,8 @@ void DAP_Setup(void) {
|
||||
|
||||
// Default settings
|
||||
DAP_Data.debug_port = 0U;
|
||||
DAP_Data.fast_clock = 0U;
|
||||
DAP_Data.clock_delay = CLOCK_DELAY(DAP_DEFAULT_SWJ_CLOCK);
|
||||
DAP_Data.transfer.idle_cycles = 0U;
|
||||
DAP_Data.transfer.retry_count = 100U;
|
||||
DAP_Data.transfer.match_retry = 0U;
|
||||
@@ -1787,22 +1803,5 @@ void DAP_Setup(void) {
|
||||
DAP_Data.jtag_dev.count = 0U;
|
||||
#endif
|
||||
|
||||
if (DAP_DEFAULT_SWJ_CLOCK >= MAX_SWJ_CLOCK(DELAY_FAST_CYCLES)) {
|
||||
DAP_Data.fast_clock = 1U;
|
||||
DAP_Data.clock_delay = 1U;
|
||||
} else {
|
||||
DAP_Data.fast_clock = 0U;
|
||||
|
||||
uint32_t delay = ((CPU_CLOCK/2U) + (DAP_DEFAULT_SWJ_CLOCK - 1U)) / DAP_DEFAULT_SWJ_CLOCK;
|
||||
if (delay > IO_PORT_WRITE_CYCLES) {
|
||||
delay -= IO_PORT_WRITE_CYCLES;
|
||||
delay = (delay + (DELAY_SLOW_CYCLES - 1U)) / DELAY_SLOW_CYCLES;
|
||||
} else {
|
||||
delay = 1U;
|
||||
}
|
||||
|
||||
DAP_Data.clock_delay = delay;
|
||||
}
|
||||
|
||||
DAP_SETUP(); // Device specific setup
|
||||
}
|
||||
@@ -0,0 +1,100 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* ----------------------------------------------------------------------
|
||||
*
|
||||
* $Date: 1. December 2017
|
||||
* $Revision: V2.0.0
|
||||
*
|
||||
* Project: CMSIS-DAP Source
|
||||
* Title: DAP_vendor.c CMSIS-DAP Vendor Commands
|
||||
*
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
#include "DAP_config.h"
|
||||
#include "DAP.h"
|
||||
|
||||
//**************************************************************************************************
|
||||
/**
|
||||
\defgroup DAP_Vendor_Adapt_gr Adapt Vendor Commands
|
||||
\ingroup DAP_Vendor_gr
|
||||
@{
|
||||
|
||||
The file DAP_vendor.c provides template source code for extension of a Debug Unit with
|
||||
Vendor Commands. Copy this file to the project folder of the Debug Unit and add the
|
||||
file to the MDK-ARM project under the file group Configuration.
|
||||
*/
|
||||
|
||||
/** Process DAP Vendor Command and prepare Response Data
|
||||
\param request pointer to request data
|
||||
\param response pointer to response data
|
||||
\return number of bytes in response (lower 16 bits)
|
||||
number of bytes in request (upper 16 bits)
|
||||
*/
|
||||
uint32_t DAP_ProcessVendorCommand(const uint8_t *request, uint8_t *response) {
|
||||
uint32_t num = (1U << 16) | 1U;
|
||||
|
||||
*response++ = *request; // copy Command ID
|
||||
|
||||
switch (*request++) { // first byte in request is Command ID
|
||||
case ID_DAP_Vendor0:
|
||||
#if 0 // example user command
|
||||
num += 1U << 16; // increment request count
|
||||
if (*request == 1U) { // when first command data byte is 1
|
||||
*response++ = 'X'; // send 'X' as response
|
||||
num++; // increment response count
|
||||
}
|
||||
#endif
|
||||
break;
|
||||
|
||||
case ID_DAP_Vendor1: break;
|
||||
case ID_DAP_Vendor2: break;
|
||||
case ID_DAP_Vendor3: break;
|
||||
case ID_DAP_Vendor4: break;
|
||||
case ID_DAP_Vendor5: break;
|
||||
case ID_DAP_Vendor6: break;
|
||||
case ID_DAP_Vendor7: break;
|
||||
case ID_DAP_Vendor8: break;
|
||||
case ID_DAP_Vendor9: break;
|
||||
case ID_DAP_Vendor10: break;
|
||||
case ID_DAP_Vendor11: break;
|
||||
case ID_DAP_Vendor12: break;
|
||||
case ID_DAP_Vendor13: break;
|
||||
case ID_DAP_Vendor14: break;
|
||||
case ID_DAP_Vendor15: break;
|
||||
case ID_DAP_Vendor16: break;
|
||||
case ID_DAP_Vendor17: break;
|
||||
case ID_DAP_Vendor18: break;
|
||||
case ID_DAP_Vendor19: break;
|
||||
case ID_DAP_Vendor20: break;
|
||||
case ID_DAP_Vendor21: break;
|
||||
case ID_DAP_Vendor22: break;
|
||||
case ID_DAP_Vendor23: break;
|
||||
case ID_DAP_Vendor24: break;
|
||||
case ID_DAP_Vendor25: break;
|
||||
case ID_DAP_Vendor26: break;
|
||||
case ID_DAP_Vendor27: break;
|
||||
case ID_DAP_Vendor28: break;
|
||||
case ID_DAP_Vendor29: break;
|
||||
case ID_DAP_Vendor30: break;
|
||||
case ID_DAP_Vendor31: break;
|
||||
}
|
||||
|
||||
return (num);
|
||||
}
|
||||
|
||||
///@}
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
|
||||
* Copyright (c) 2013-2021 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
@@ -17,8 +17,8 @@
|
||||
*
|
||||
* ----------------------------------------------------------------------
|
||||
*
|
||||
* $Date: 1. December 2017
|
||||
* $Revision: V2.0.0
|
||||
* $Date: 29. March 2021
|
||||
* $Revision: V2.0.1
|
||||
*
|
||||
* Project: CMSIS-DAP Source
|
||||
* Title: SWO.c CMSIS-DAP SWO I/O
|
||||
@@ -32,6 +32,8 @@
|
||||
#endif
|
||||
#if (SWO_STREAM != 0)
|
||||
#include "cmsis_os2.h"
|
||||
#define osObjectsExternal
|
||||
#include "osObjects.h"
|
||||
#endif
|
||||
|
||||
#if (SWO_STREAM != 0)
|
||||
@@ -42,15 +44,11 @@
|
||||
|
||||
#if (SWO_UART != 0)
|
||||
|
||||
#ifndef SWO_USART_PORT
|
||||
#define SWO_USART_PORT 0 /* USART Port Number */
|
||||
#endif
|
||||
|
||||
// USART Driver
|
||||
#define _USART_Driver_(n) Driver_USART##n
|
||||
#define USART_Driver_(n) _USART_Driver_(n)
|
||||
extern ARM_DRIVER_USART USART_Driver_(SWO_USART_PORT);
|
||||
#define pUSART (&USART_Driver_(SWO_USART_PORT))
|
||||
extern ARM_DRIVER_USART USART_Driver_(SWO_UART_DRIVER);
|
||||
#define pUSART (&USART_Driver_(SWO_UART_DRIVER))
|
||||
|
||||
static uint8_t USART_Ready = 0U;
|
||||
|
||||
@@ -150,10 +148,10 @@ static void USART_Callback (uint32_t event) {
|
||||
}
|
||||
}
|
||||
|
||||
// Enable or disable UART SWO Mode
|
||||
// Enable or disable SWO Mode (UART)
|
||||
// enable: enable flag
|
||||
// return: 1 - Success, 0 - Error
|
||||
__WEAK uint32_t UART_SWO_Mode (uint32_t enable) {
|
||||
__WEAK uint32_t SWO_Mode_UART (uint32_t enable) {
|
||||
int32_t status;
|
||||
|
||||
USART_Ready = 0U;
|
||||
@@ -177,10 +175,10 @@ __WEAK uint32_t UART_SWO_Mode (uint32_t enable) {
|
||||
return (1U);
|
||||
}
|
||||
|
||||
// Configure UART SWO Baudrate
|
||||
// Configure SWO Baudrate (UART)
|
||||
// baudrate: requested baudrate
|
||||
// return: actual baudrate or 0 when not configured
|
||||
__WEAK uint32_t UART_SWO_Baudrate (uint32_t baudrate) {
|
||||
__WEAK uint32_t SWO_Baudrate_UART (uint32_t baudrate) {
|
||||
int32_t status;
|
||||
uint32_t index;
|
||||
uint32_t num;
|
||||
@@ -223,10 +221,10 @@ __WEAK uint32_t UART_SWO_Baudrate (uint32_t baudrate) {
|
||||
return (baudrate);
|
||||
}
|
||||
|
||||
// Control UART SWO Capture
|
||||
// Control SWO Capture (UART)
|
||||
// active: active flag
|
||||
// return: 1 - Success, 0 - Error
|
||||
__WEAK uint32_t UART_SWO_Control (uint32_t active) {
|
||||
__WEAK uint32_t SWO_Control_UART (uint32_t active) {
|
||||
int32_t status;
|
||||
|
||||
if (active) {
|
||||
@@ -252,17 +250,17 @@ __WEAK uint32_t UART_SWO_Control (uint32_t active) {
|
||||
return (1U);
|
||||
}
|
||||
|
||||
// Start UART SWO Capture
|
||||
// Start SWO Capture (UART)
|
||||
// buf: pointer to buffer for capturing
|
||||
// num: number of bytes to capture
|
||||
__WEAK void UART_SWO_Capture (uint8_t *buf, uint32_t num) {
|
||||
__WEAK void SWO_Capture_UART (uint8_t *buf, uint32_t num) {
|
||||
TraceBlockSize = num;
|
||||
pUSART->Receive(buf, num);
|
||||
}
|
||||
|
||||
// Get UART SWO Pending Trace Count
|
||||
// Get SWO Pending Trace Count (UART)
|
||||
// return: number of pending trace data bytes
|
||||
__WEAK uint32_t UART_SWO_GetCount (void) {
|
||||
__WEAK uint32_t SWO_GetCount_UART (void) {
|
||||
uint32_t count;
|
||||
|
||||
if (pUSART->GetStatus().rx_busy) {
|
||||
@@ -278,36 +276,36 @@ __WEAK uint32_t UART_SWO_GetCount (void) {
|
||||
|
||||
#if (SWO_MANCHESTER != 0)
|
||||
|
||||
// Enable or disable Manchester SWO Mode
|
||||
// Enable or disable SWO Mode (Manchester)
|
||||
// enable: enable flag
|
||||
// return: 1 - Success, 0 - Error
|
||||
__WEAK uint32_t Manchester_SWO_Mode (uint32_t enable) {
|
||||
__WEAK uint32_t SWO_Mode_Manchester (uint32_t enable) {
|
||||
return (0U);
|
||||
}
|
||||
|
||||
// Configure Manchester SWO Baudrate
|
||||
// Configure SWO Baudrate (Manchester)
|
||||
// baudrate: requested baudrate
|
||||
// return: actual baudrate or 0 when not configured
|
||||
__WEAK uint32_t Manchester_SWO_Baudrate (uint32_t baudrate) {
|
||||
__WEAK uint32_t SWO_Baudrate_Manchester (uint32_t baudrate) {
|
||||
return (0U);
|
||||
}
|
||||
|
||||
// Control Manchester SWO Capture
|
||||
// Control SWO Capture (Manchester)
|
||||
// active: active flag
|
||||
// return: 1 - Success, 0 - Error
|
||||
__WEAK uint32_t Manchester_SWO_Control (uint32_t active) {
|
||||
__WEAK uint32_t SWO_Control_Manchester (uint32_t active) {
|
||||
return (0U);
|
||||
}
|
||||
|
||||
// Start Manchester SWO Capture
|
||||
// Start SWO Capture (Manchester)
|
||||
// buf: pointer to buffer for capturing
|
||||
// num: number of bytes to capture
|
||||
__WEAK void Manchester_SWO_Capture (uint8_t *buf, uint32_t num) {
|
||||
__WEAK void SWO_Capture_Manchester (uint8_t *buf, uint32_t num) {
|
||||
}
|
||||
|
||||
// Get Manchester SWO Pending Trace Count
|
||||
// Get SWO Pending Trace Count (Manchester)
|
||||
// return: number of pending trace data bytes
|
||||
__WEAK uint32_t Manchester_SWO_GetCount (void) {
|
||||
__WEAK uint32_t SWO_GetCount_Manchester (void) {
|
||||
}
|
||||
|
||||
#endif /* (SWO_MANCHESTER != 0) */
|
||||
@@ -351,13 +349,13 @@ static void ResumeTrace (void) {
|
||||
#if (SWO_UART != 0)
|
||||
case DAP_SWO_UART:
|
||||
TraceStatus = DAP_SWO_CAPTURE_ACTIVE;
|
||||
UART_SWO_Capture(&TraceBuf[index_i], 1U);
|
||||
SWO_Capture_UART(&TraceBuf[index_i], 1U);
|
||||
break;
|
||||
#endif
|
||||
#if (SWO_MANCHESTER != 0)
|
||||
case DAP_SWO_MANCHESTER:
|
||||
TraceStatus = DAP_SWO_CAPTURE_ACTIVE;
|
||||
Manchester_SWO_Capture(&TraceBuf[index_i], 1U);
|
||||
SWO_Capture_Manchester(&TraceBuf[index_i], 1U);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
@@ -379,12 +377,12 @@ static uint32_t GetTraceCount (void) {
|
||||
switch (TraceMode) {
|
||||
#if (SWO_UART != 0)
|
||||
case DAP_SWO_UART:
|
||||
count += UART_SWO_GetCount();
|
||||
count += SWO_GetCount_UART();
|
||||
break;
|
||||
#endif
|
||||
#if (SWO_MANCHESTER != 0)
|
||||
case DAP_SWO_MANCHESTER:
|
||||
count += Manchester_SWO_GetCount();
|
||||
count += SWO_GetCount_Manchester();
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
@@ -471,12 +469,12 @@ uint32_t SWO_Mode (const uint8_t *request, uint8_t *response) {
|
||||
switch (TraceMode) {
|
||||
#if (SWO_UART != 0)
|
||||
case DAP_SWO_UART:
|
||||
UART_SWO_Mode(0U);
|
||||
SWO_Mode_UART(0U);
|
||||
break;
|
||||
#endif
|
||||
#if (SWO_MANCHESTER != 0)
|
||||
case DAP_SWO_MANCHESTER:
|
||||
Manchester_SWO_Mode(0U);
|
||||
SWO_Mode_Manchester(0U);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
@@ -489,12 +487,12 @@ uint32_t SWO_Mode (const uint8_t *request, uint8_t *response) {
|
||||
break;
|
||||
#if (SWO_UART != 0)
|
||||
case DAP_SWO_UART:
|
||||
result = UART_SWO_Mode(1U);
|
||||
result = SWO_Mode_UART(1U);
|
||||
break;
|
||||
#endif
|
||||
#if (SWO_MANCHESTER != 0)
|
||||
case DAP_SWO_MANCHESTER:
|
||||
result = Manchester_SWO_Mode(1U);
|
||||
result = SWO_Mode_Manchester(1U);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
@@ -535,12 +533,12 @@ uint32_t SWO_Baudrate (const uint8_t *request, uint8_t *response) {
|
||||
switch (TraceMode) {
|
||||
#if (SWO_UART != 0)
|
||||
case DAP_SWO_UART:
|
||||
baudrate = UART_SWO_Baudrate(baudrate);
|
||||
baudrate = SWO_Baudrate_UART(baudrate);
|
||||
break;
|
||||
#endif
|
||||
#if (SWO_MANCHESTER != 0)
|
||||
case DAP_SWO_MANCHESTER:
|
||||
baudrate = Manchester_SWO_Baudrate(baudrate);
|
||||
baudrate = SWO_Baudrate_Manchester(baudrate);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
@@ -579,12 +577,12 @@ uint32_t SWO_Control (const uint8_t *request, uint8_t *response) {
|
||||
switch (TraceMode) {
|
||||
#if (SWO_UART != 0)
|
||||
case DAP_SWO_UART:
|
||||
result = UART_SWO_Control(active);
|
||||
result = SWO_Control_UART(active);
|
||||
break;
|
||||
#endif
|
||||
#if (SWO_MANCHESTER != 0)
|
||||
case DAP_SWO_MANCHESTER:
|
||||
result = Manchester_SWO_Control(active);
|
||||
result = SWO_Control_Manchester(active);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
@@ -0,0 +1,652 @@
|
||||
/*
|
||||
* Copyright (c) 2021 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* ----------------------------------------------------------------------
|
||||
*
|
||||
* $Date: 1. March 2021
|
||||
* $Revision: V1.0.0
|
||||
*
|
||||
* Project: CMSIS-DAP Source
|
||||
* Title: UART.c CMSIS-DAP UART
|
||||
*
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
#include "DAP_config.h"
|
||||
#include "DAP.h"
|
||||
|
||||
#if (DAP_UART != 0)
|
||||
|
||||
#ifdef DAP_FW_V1
|
||||
#error "UART Communication Port not supported in DAP V1!"
|
||||
#endif
|
||||
|
||||
#include "Driver_USART.h"
|
||||
|
||||
#include "cmsis_os2.h"
|
||||
#include <string.h>
|
||||
|
||||
#define UART_RX_BLOCK_SIZE 32U /* Uart Rx Block Size (must be 2^n) */
|
||||
|
||||
// USART Driver
|
||||
#define _USART_Driver_(n) Driver_USART##n
|
||||
#define USART_Driver_(n) _USART_Driver_(n)
|
||||
extern ARM_DRIVER_USART USART_Driver_(DAP_UART_DRIVER);
|
||||
#define pUSART (&USART_Driver_(DAP_UART_DRIVER))
|
||||
|
||||
// UART Configuration
|
||||
#if (DAP_UART_USB_COM_PORT != 0)
|
||||
static uint8_t UartTransport = DAP_UART_TRANSPORT_USB_COM_PORT;
|
||||
#else
|
||||
static uint8_t UartTransport = DAP_UART_TRANSPORT_NONE;
|
||||
#endif
|
||||
|
||||
// UART Flags
|
||||
static uint8_t UartConfigured = 0U;
|
||||
static uint8_t UartReceiveEnabled = 0U;
|
||||
static uint8_t UartTransmitEnabled = 0U;
|
||||
static uint8_t UartTransmitActive = 0U;
|
||||
|
||||
// UART TX Buffer
|
||||
static uint8_t UartTxBuf[DAP_UART_TX_BUFFER_SIZE];
|
||||
static volatile uint32_t UartTxIndexI = 0U;
|
||||
static volatile uint32_t UartTxIndexO = 0U;
|
||||
|
||||
// UART RX Buffer
|
||||
static uint8_t UartRxBuf[DAP_UART_RX_BUFFER_SIZE];
|
||||
static volatile uint32_t UartRxIndexI = 0U;
|
||||
static volatile uint32_t UartRxIndexO = 0U;
|
||||
|
||||
// Uart Errors
|
||||
static volatile uint8_t UartErrorRxDataLost = 0U;
|
||||
static volatile uint8_t UartErrorFraming = 0U;
|
||||
static volatile uint8_t UartErrorParity = 0U;
|
||||
|
||||
// UART Transmit
|
||||
static uint32_t UartTxNum = 0U;
|
||||
|
||||
// Function prototypes
|
||||
static uint8_t UART_Init (void);
|
||||
static void UART_Uninit (void);
|
||||
static uint8_t UART_Get_Status (void);
|
||||
static uint8_t UART_Receive_Enable (void);
|
||||
static uint8_t UART_Transmit_Enable (void);
|
||||
static void UART_Receive_Disable (void);
|
||||
static void UART_Transmit_Disable (void);
|
||||
static void UART_Receive_Flush (void);
|
||||
static void UART_Transmit_Flush (void);
|
||||
static void UART_Receive (void);
|
||||
static void UART_Transmit (void);
|
||||
|
||||
|
||||
// USART Driver Callback function
|
||||
// event: event mask
|
||||
static void USART_Callback (uint32_t event) {
|
||||
if (event & ARM_USART_EVENT_SEND_COMPLETE) {
|
||||
UartTxIndexO += UartTxNum;
|
||||
UartTransmitActive = 0U;
|
||||
UART_Transmit();
|
||||
}
|
||||
if (event & ARM_USART_EVENT_RECEIVE_COMPLETE) {
|
||||
UartRxIndexI += UART_RX_BLOCK_SIZE;
|
||||
UART_Receive();
|
||||
}
|
||||
if (event & ARM_USART_EVENT_RX_OVERFLOW) {
|
||||
UartErrorRxDataLost = 1U;
|
||||
}
|
||||
if (event & ARM_USART_EVENT_RX_FRAMING_ERROR) {
|
||||
UartErrorFraming = 1U;
|
||||
}
|
||||
if (event & ARM_USART_EVENT_RX_PARITY_ERROR) {
|
||||
UartErrorParity = 1U;
|
||||
}
|
||||
}
|
||||
|
||||
// Init UART
|
||||
// return: DAP_OK or DAP_ERROR
|
||||
static uint8_t UART_Init (void) {
|
||||
int32_t status;
|
||||
uint8_t ret = DAP_ERROR;
|
||||
|
||||
UartConfigured = 0U;
|
||||
UartReceiveEnabled = 0U;
|
||||
UartTransmitEnabled = 0U;
|
||||
UartTransmitActive = 0U;
|
||||
UartErrorRxDataLost = 0U;
|
||||
UartErrorFraming = 0U;
|
||||
UartErrorParity = 0U;
|
||||
UartTxIndexI = 0U;
|
||||
UartTxIndexO = 0U;
|
||||
UartRxIndexI = 0U;
|
||||
UartRxIndexO = 0U;
|
||||
UartTxNum = 0U;
|
||||
|
||||
status = pUSART->Initialize(USART_Callback);
|
||||
if (status == ARM_DRIVER_OK) {
|
||||
status = pUSART->PowerControl(ARM_POWER_FULL);
|
||||
}
|
||||
if (status == ARM_DRIVER_OK) {
|
||||
ret = DAP_OK;
|
||||
}
|
||||
|
||||
return (ret);
|
||||
}
|
||||
|
||||
// Un-Init UART
|
||||
static void UART_Uninit (void) {
|
||||
UartConfigured = 0U;
|
||||
|
||||
pUSART->PowerControl(ARM_POWER_OFF);
|
||||
pUSART->Uninitialize();
|
||||
}
|
||||
|
||||
// Get UART Status
|
||||
// return: status
|
||||
static uint8_t UART_Get_Status (void) {
|
||||
uint8_t status = 0U;
|
||||
|
||||
if (UartReceiveEnabled != 0U) {
|
||||
status |= DAP_UART_STATUS_RX_ENABLED;
|
||||
}
|
||||
if (UartErrorRxDataLost != 0U) {
|
||||
UartErrorRxDataLost = 0U;
|
||||
status |= DAP_UART_STATUS_RX_DATA_LOST;
|
||||
}
|
||||
if (UartErrorFraming != 0U) {
|
||||
UartErrorFraming = 0U;
|
||||
status |= DAP_UART_STATUS_FRAMING_ERROR;
|
||||
}
|
||||
if (UartErrorParity != 0U) {
|
||||
UartErrorParity = 0U;
|
||||
status |= DAP_UART_STATUS_PARITY_ERROR;
|
||||
}
|
||||
if (UartTransmitEnabled != 0U) {
|
||||
status |= DAP_UART_STATUS_TX_ENABLED;
|
||||
}
|
||||
|
||||
return (status);
|
||||
}
|
||||
|
||||
// Enable UART Receive
|
||||
// return: DAP_OK or DAP_ERROR
|
||||
static uint8_t UART_Receive_Enable (void) {
|
||||
int32_t status;
|
||||
uint8_t ret = DAP_ERROR;
|
||||
|
||||
if (UartReceiveEnabled == 0U) {
|
||||
// Flush Buffers
|
||||
UartRxIndexI = 0U;
|
||||
UartRxIndexO = 0U;
|
||||
|
||||
UART_Receive();
|
||||
status = pUSART->Control(ARM_USART_CONTROL_RX, 1U);
|
||||
if (status == ARM_DRIVER_OK) {
|
||||
UartReceiveEnabled = 1U;
|
||||
ret = DAP_OK;
|
||||
}
|
||||
} else {
|
||||
ret = DAP_OK;
|
||||
}
|
||||
|
||||
return (ret);
|
||||
}
|
||||
|
||||
// Enable UART Transmit
|
||||
// return: DAP_OK or DAP_ERROR
|
||||
static uint8_t UART_Transmit_Enable (void) {
|
||||
int32_t status;
|
||||
uint8_t ret = DAP_ERROR;
|
||||
|
||||
if (UartTransmitEnabled == 0U) {
|
||||
// Flush Buffers
|
||||
UartTransmitActive = 0U;
|
||||
UartTxIndexI = 0U;
|
||||
UartTxIndexO = 0U;
|
||||
UartTxNum = 0U;
|
||||
|
||||
status = pUSART->Control(ARM_USART_CONTROL_TX, 1U);
|
||||
if (status == ARM_DRIVER_OK) {
|
||||
UartTransmitEnabled = 1U;
|
||||
ret = DAP_OK;
|
||||
}
|
||||
} else {
|
||||
ret = DAP_OK;
|
||||
}
|
||||
|
||||
return (ret);
|
||||
}
|
||||
|
||||
// Disable UART Receive
|
||||
static void UART_Receive_Disable (void) {
|
||||
if (UartReceiveEnabled != 0U) {
|
||||
pUSART->Control(ARM_USART_CONTROL_RX, 0U);
|
||||
pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U);
|
||||
UartReceiveEnabled = 0U;
|
||||
}
|
||||
}
|
||||
|
||||
// Disable UART Transmit
|
||||
static void UART_Transmit_Disable (void) {
|
||||
if (UartTransmitEnabled != 0U) {
|
||||
pUSART->Control(ARM_USART_ABORT_SEND, 0U);
|
||||
pUSART->Control(ARM_USART_CONTROL_TX, 0U);
|
||||
UartTransmitActive = 0U;
|
||||
UartTransmitEnabled = 0U;
|
||||
}
|
||||
}
|
||||
|
||||
// Flush UART Receive buffer
|
||||
static void UART_Receive_Flush (void) {
|
||||
pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U);
|
||||
UartRxIndexI = 0U;
|
||||
UartRxIndexO = 0U;
|
||||
if (UartReceiveEnabled != 0U) {
|
||||
UART_Receive();
|
||||
}
|
||||
}
|
||||
|
||||
// Flush UART Transmit buffer
|
||||
static void UART_Transmit_Flush (void) {
|
||||
pUSART->Control(ARM_USART_ABORT_SEND, 0U);
|
||||
UartTransmitActive = 0U;
|
||||
UartTxIndexI = 0U;
|
||||
UartTxIndexO = 0U;
|
||||
UartTxNum = 0U;
|
||||
}
|
||||
|
||||
// Receive data from target via UART
|
||||
static void UART_Receive (void) {
|
||||
uint32_t index;
|
||||
|
||||
index = UartRxIndexI & (DAP_UART_RX_BUFFER_SIZE - 1U);
|
||||
pUSART->Receive(&UartRxBuf[index], UART_RX_BLOCK_SIZE);
|
||||
}
|
||||
|
||||
// Transmit available data to target via UART
|
||||
static void UART_Transmit (void) {
|
||||
uint32_t count;
|
||||
uint32_t index;
|
||||
|
||||
count = UartTxIndexI - UartTxIndexO;
|
||||
index = UartTxIndexO & (DAP_UART_TX_BUFFER_SIZE - 1U);
|
||||
|
||||
if (count != 0U) {
|
||||
if ((index + count) <= DAP_UART_TX_BUFFER_SIZE) {
|
||||
UartTxNum = count;
|
||||
} else {
|
||||
UartTxNum = DAP_UART_TX_BUFFER_SIZE - index;
|
||||
}
|
||||
UartTransmitActive = 1U;
|
||||
pUSART->Send(&UartTxBuf[index], UartTxNum);
|
||||
}
|
||||
}
|
||||
|
||||
// Process UART Transport command and prepare response
|
||||
// request: pointer to request data
|
||||
// response: pointer to response data
|
||||
// return: number of bytes in response (lower 16 bits)
|
||||
// number of bytes in request (upper 16 bits)
|
||||
uint32_t UART_Transport (const uint8_t *request, uint8_t *response) {
|
||||
uint8_t transport;
|
||||
uint8_t ret = DAP_ERROR;
|
||||
|
||||
transport = *request;
|
||||
switch (transport) {
|
||||
case DAP_UART_TRANSPORT_NONE:
|
||||
switch (UartTransport) {
|
||||
case DAP_UART_TRANSPORT_NONE:
|
||||
ret = DAP_OK;
|
||||
break;
|
||||
case DAP_UART_TRANSPORT_USB_COM_PORT:
|
||||
#if (DAP_UART_USB_COM_PORT != 0)
|
||||
USB_COM_PORT_Activate(0U);
|
||||
UartTransport = DAP_UART_TRANSPORT_NONE;
|
||||
ret = DAP_OK;
|
||||
#endif
|
||||
break;
|
||||
case DAP_UART_TRANSPORT_DAP_COMMAND:
|
||||
UART_Receive_Disable();
|
||||
UART_Transmit_Disable();
|
||||
UART_Uninit();
|
||||
UartTransport = DAP_UART_TRANSPORT_NONE;
|
||||
ret= DAP_OK;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case DAP_UART_TRANSPORT_USB_COM_PORT:
|
||||
switch (UartTransport) {
|
||||
case DAP_UART_TRANSPORT_NONE:
|
||||
#if (DAP_UART_USB_COM_PORT != 0)
|
||||
if (USB_COM_PORT_Activate(1U) == 0U) {
|
||||
UartTransport = DAP_UART_TRANSPORT_USB_COM_PORT;
|
||||
ret = DAP_OK;
|
||||
}
|
||||
#endif
|
||||
break;
|
||||
case DAP_UART_TRANSPORT_USB_COM_PORT:
|
||||
ret = DAP_OK;
|
||||
break;
|
||||
case DAP_UART_TRANSPORT_DAP_COMMAND:
|
||||
UART_Receive_Disable();
|
||||
UART_Transmit_Disable();
|
||||
UART_Uninit();
|
||||
UartTransport = DAP_UART_TRANSPORT_NONE;
|
||||
#if (DAP_UART_USB_COM_PORT != 0)
|
||||
if (USB_COM_PORT_Activate(1U) == 0U) {
|
||||
UartTransport = DAP_UART_TRANSPORT_USB_COM_PORT;
|
||||
ret = DAP_OK;
|
||||
}
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case DAP_UART_TRANSPORT_DAP_COMMAND:
|
||||
switch (UartTransport) {
|
||||
case DAP_UART_TRANSPORT_NONE:
|
||||
ret = UART_Init();
|
||||
if (ret == DAP_OK) {
|
||||
UartTransport = DAP_UART_TRANSPORT_DAP_COMMAND;
|
||||
}
|
||||
break;
|
||||
case DAP_UART_TRANSPORT_USB_COM_PORT:
|
||||
#if (DAP_UART_USB_COM_PORT != 0)
|
||||
USB_COM_PORT_Activate(0U);
|
||||
UartTransport = DAP_UART_TRANSPORT_NONE;
|
||||
#endif
|
||||
ret = UART_Init();
|
||||
if (ret == DAP_OK) {
|
||||
UartTransport = DAP_UART_TRANSPORT_DAP_COMMAND;
|
||||
}
|
||||
break;
|
||||
case DAP_UART_TRANSPORT_DAP_COMMAND:
|
||||
ret = DAP_OK;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
*response = ret;
|
||||
|
||||
return ((1U << 16) | 1U);
|
||||
}
|
||||
|
||||
// Process UART Configure command and prepare response
|
||||
// request: pointer to request data
|
||||
// response: pointer to response data
|
||||
// return: number of bytes in response (lower 16 bits)
|
||||
// number of bytes in request (upper 16 bits)
|
||||
uint32_t UART_Configure (const uint8_t *request, uint8_t *response) {
|
||||
uint8_t control, status;
|
||||
uint32_t baudrate;
|
||||
int32_t result;
|
||||
|
||||
if (UartTransport != DAP_UART_TRANSPORT_DAP_COMMAND) {
|
||||
status = DAP_UART_CFG_ERROR_DATA_BITS |
|
||||
DAP_UART_CFG_ERROR_PARITY |
|
||||
DAP_UART_CFG_ERROR_STOP_BITS;
|
||||
baudrate = 0U; // baudrate error
|
||||
} else {
|
||||
|
||||
status = 0U;
|
||||
control = *request;
|
||||
baudrate = (uint32_t)(*(request+1) << 0) |
|
||||
(uint32_t)(*(request+2) << 8) |
|
||||
(uint32_t)(*(request+3) << 16) |
|
||||
(uint32_t)(*(request+4) << 24);
|
||||
|
||||
result = pUSART->Control(control |
|
||||
ARM_USART_MODE_ASYNCHRONOUS |
|
||||
ARM_USART_FLOW_CONTROL_NONE,
|
||||
baudrate);
|
||||
if (result == ARM_DRIVER_OK) {
|
||||
UartConfigured = 1U;
|
||||
} else {
|
||||
UartConfigured = 0U;
|
||||
switch (result) {
|
||||
case ARM_USART_ERROR_BAUDRATE:
|
||||
status = 0U;
|
||||
baudrate = 0U;
|
||||
break;
|
||||
case ARM_USART_ERROR_DATA_BITS:
|
||||
status = DAP_UART_CFG_ERROR_DATA_BITS;
|
||||
break;
|
||||
case ARM_USART_ERROR_PARITY:
|
||||
status = DAP_UART_CFG_ERROR_PARITY;
|
||||
break;
|
||||
case ARM_USART_ERROR_STOP_BITS:
|
||||
status = DAP_UART_CFG_ERROR_STOP_BITS;
|
||||
break;
|
||||
default:
|
||||
status = DAP_UART_CFG_ERROR_DATA_BITS |
|
||||
DAP_UART_CFG_ERROR_PARITY |
|
||||
DAP_UART_CFG_ERROR_STOP_BITS;
|
||||
baudrate = 0U;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
*response++ = status;
|
||||
*response++ = (uint8_t)(baudrate >> 0);
|
||||
*response++ = (uint8_t)(baudrate >> 8);
|
||||
*response++ = (uint8_t)(baudrate >> 16);
|
||||
*response = (uint8_t)(baudrate >> 24);
|
||||
|
||||
return ((5U << 16) | 5U);
|
||||
}
|
||||
|
||||
// Process UART Control command and prepare response
|
||||
// request: pointer to request data
|
||||
// response: pointer to response data
|
||||
// return: number of bytes in response (lower 16 bits)
|
||||
// number of bytes in request (upper 16 bits)
|
||||
uint32_t UART_Control (const uint8_t *request, uint8_t *response) {
|
||||
uint8_t control;
|
||||
uint8_t result;
|
||||
uint8_t ret = DAP_OK;
|
||||
|
||||
if (UartTransport != DAP_UART_TRANSPORT_DAP_COMMAND) {
|
||||
ret = DAP_ERROR;
|
||||
} else {
|
||||
|
||||
control = *request;
|
||||
|
||||
if ((control & DAP_UART_CONTROL_RX_DISABLE) != 0U) {
|
||||
// Receive disable
|
||||
UART_Receive_Disable();
|
||||
} else if ((control & DAP_UART_CONTROL_RX_ENABLE) != 0U) {
|
||||
// Receive enable
|
||||
if (UartConfigured != 0U) {
|
||||
result = UART_Receive_Enable();
|
||||
if (result != DAP_OK) {
|
||||
ret = DAP_ERROR;
|
||||
}
|
||||
} else {
|
||||
ret = DAP_ERROR;
|
||||
}
|
||||
}
|
||||
if ((control & DAP_UART_CONTROL_RX_BUF_FLUSH) != 0U) {
|
||||
UART_Receive_Flush();
|
||||
}
|
||||
|
||||
if ((control & DAP_UART_CONTROL_TX_DISABLE) != 0U) {
|
||||
// Transmit disable
|
||||
UART_Transmit_Disable();
|
||||
} else if ((control & DAP_UART_CONTROL_TX_ENABLE) != 0U) {
|
||||
// Transmit enable
|
||||
if (UartConfigured != 0U) {
|
||||
result = UART_Transmit_Enable();
|
||||
if (result != DAP_OK) {
|
||||
ret = DAP_ERROR;
|
||||
}
|
||||
} else {
|
||||
ret = DAP_ERROR;
|
||||
}
|
||||
}
|
||||
if ((control & DAP_UART_CONTROL_TX_BUF_FLUSH) != 0U) {
|
||||
UART_Transmit_Flush();
|
||||
}
|
||||
}
|
||||
|
||||
*response = ret;
|
||||
|
||||
return ((1U << 16) | 1U);
|
||||
}
|
||||
|
||||
// Process UART Status command and prepare response
|
||||
// response: pointer to response data
|
||||
// return: number of bytes in response (lower 16 bits)
|
||||
// number of bytes in request (upper 16 bits)
|
||||
uint32_t UART_Status (uint8_t *response) {
|
||||
uint32_t rx_cnt, tx_cnt;
|
||||
uint32_t cnt;
|
||||
uint8_t status;
|
||||
|
||||
if ((UartTransport != DAP_UART_TRANSPORT_DAP_COMMAND) ||
|
||||
(UartConfigured == 0U)) {
|
||||
rx_cnt = 0U;
|
||||
tx_cnt = 0U;
|
||||
status = 0U;
|
||||
} else {
|
||||
|
||||
rx_cnt = UartRxIndexI - UartRxIndexO;
|
||||
rx_cnt += pUSART->GetRxCount();
|
||||
if (rx_cnt > (DAP_UART_RX_BUFFER_SIZE - (UART_RX_BLOCK_SIZE*2))) {
|
||||
// Overflow
|
||||
UartErrorRxDataLost = 1U;
|
||||
rx_cnt = (DAP_UART_RX_BUFFER_SIZE - (UART_RX_BLOCK_SIZE*2));
|
||||
UartRxIndexO = UartRxIndexI - rx_cnt;
|
||||
}
|
||||
|
||||
tx_cnt = UartTxIndexI - UartTxIndexO;
|
||||
cnt = pUSART->GetTxCount();
|
||||
if (UartTransmitActive != 0U) {
|
||||
tx_cnt -= cnt;
|
||||
}
|
||||
|
||||
status = UART_Get_Status();
|
||||
}
|
||||
|
||||
*response++ = status;
|
||||
*response++ = (uint8_t)(rx_cnt >> 0);
|
||||
*response++ = (uint8_t)(rx_cnt >> 8);
|
||||
*response++ = (uint8_t)(rx_cnt >> 16);
|
||||
*response++ = (uint8_t)(rx_cnt >> 24);
|
||||
*response++ = (uint8_t)(tx_cnt >> 0);
|
||||
*response++ = (uint8_t)(tx_cnt >> 8);
|
||||
*response++ = (uint8_t)(tx_cnt >> 16);
|
||||
*response = (uint8_t)(tx_cnt >> 24);
|
||||
|
||||
return ((0U << 16) | 9U);
|
||||
}
|
||||
|
||||
// Process UART Transfer command and prepare response
|
||||
// request: pointer to request data
|
||||
// response: pointer to response data
|
||||
// return: number of bytes in response (lower 16 bits)
|
||||
// number of bytes in request (upper 16 bits)
|
||||
uint32_t UART_Transfer (const uint8_t *request, uint8_t *response) {
|
||||
uint32_t rx_cnt, tx_cnt;
|
||||
uint32_t rx_num, tx_num;
|
||||
uint8_t *rx_data;
|
||||
const
|
||||
uint8_t *tx_data;
|
||||
uint32_t num;
|
||||
uint32_t index;
|
||||
uint8_t status;
|
||||
|
||||
if (UartTransport != DAP_UART_TRANSPORT_DAP_COMMAND) {
|
||||
status = 0U;
|
||||
rx_cnt = 0U;
|
||||
tx_cnt = 0U;
|
||||
} else {
|
||||
|
||||
// RX Data
|
||||
rx_cnt = ((uint32_t)(*(request+0) << 0) |
|
||||
(uint32_t)(*(request+1) << 8));
|
||||
|
||||
if (rx_cnt > (DAP_PACKET_SIZE - 6U)) {
|
||||
rx_cnt = (DAP_PACKET_SIZE - 6U);
|
||||
}
|
||||
rx_num = UartRxIndexI - UartRxIndexO;
|
||||
rx_num += pUSART->GetRxCount();
|
||||
if (rx_num > (DAP_UART_RX_BUFFER_SIZE - (UART_RX_BLOCK_SIZE*2))) {
|
||||
// Overflow
|
||||
UartErrorRxDataLost = 1U;
|
||||
rx_num = (DAP_UART_RX_BUFFER_SIZE - (UART_RX_BLOCK_SIZE*2));
|
||||
UartRxIndexO = UartRxIndexI - rx_num;
|
||||
}
|
||||
if (rx_cnt > rx_num) {
|
||||
rx_cnt = rx_num;
|
||||
}
|
||||
|
||||
rx_data = (response+5);
|
||||
index = UartRxIndexO & (DAP_UART_RX_BUFFER_SIZE - 1U);
|
||||
if ((index + rx_cnt) <= DAP_UART_RX_BUFFER_SIZE) {
|
||||
memcpy( rx_data, &UartRxBuf[index], rx_cnt);
|
||||
} else {
|
||||
num = DAP_UART_RX_BUFFER_SIZE - index;
|
||||
memcpy( rx_data, &UartRxBuf[index], num);
|
||||
memcpy(&rx_data[num], &UartRxBuf[0], rx_cnt - num);
|
||||
}
|
||||
UartRxIndexO += rx_cnt;
|
||||
|
||||
// TX Data
|
||||
tx_cnt = ((uint32_t)(*(request+2) << 0) |
|
||||
(uint32_t)(*(request+3) << 8));
|
||||
tx_data = (request+4);
|
||||
|
||||
if (tx_cnt > (DAP_PACKET_SIZE - 5U)) {
|
||||
tx_cnt = (DAP_PACKET_SIZE - 5U);
|
||||
}
|
||||
tx_num = UartTxIndexI - UartTxIndexO;
|
||||
num = pUSART->GetTxCount();
|
||||
if (UartTransmitActive != 0U) {
|
||||
tx_num -= num;
|
||||
}
|
||||
if (tx_cnt > (DAP_UART_TX_BUFFER_SIZE - tx_num)) {
|
||||
tx_cnt = (DAP_UART_TX_BUFFER_SIZE - tx_num);
|
||||
}
|
||||
|
||||
index = UartTxIndexI & (DAP_UART_TX_BUFFER_SIZE - 1U);
|
||||
if ((index + tx_cnt) <= DAP_UART_TX_BUFFER_SIZE) {
|
||||
memcpy(&UartTxBuf[index], tx_data, tx_cnt);
|
||||
} else {
|
||||
num = DAP_UART_TX_BUFFER_SIZE - index;
|
||||
memcpy(&UartTxBuf[index], tx_data, num);
|
||||
memcpy(&UartTxBuf[0], &tx_data[num], tx_cnt - num);
|
||||
}
|
||||
UartTxIndexI += tx_cnt;
|
||||
|
||||
if (UartTransmitActive == 0U) {
|
||||
UART_Transmit();
|
||||
}
|
||||
|
||||
status = UART_Get_Status();
|
||||
}
|
||||
|
||||
*response++ = status;
|
||||
*response++ = (uint8_t)(tx_cnt >> 0);
|
||||
*response++ = (uint8_t)(tx_cnt >> 8);
|
||||
*response++ = (uint8_t)(rx_cnt >> 0);
|
||||
*response = (uint8_t)(rx_cnt >> 8);
|
||||
|
||||
return (((4U + tx_cnt) << 16) | (5U + rx_cnt));
|
||||
}
|
||||
|
||||
#endif /* DAP_UART */
|
||||
@@ -1,147 +0,0 @@
|
||||
/**
|
||||
* @file debug_ca.h
|
||||
* @brief Access to ARM DAP (Cortex-A) using CMSIS-DAP protocol
|
||||
*
|
||||
* DAPLink Interface Firmware
|
||||
* Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef DEBUG_CA_H
|
||||
#define DEBUG_CA_H
|
||||
|
||||
#include "debug_cm.h"
|
||||
|
||||
// Debug registers
|
||||
#define DEBUG_REGSITER_BASE (0x80030000)
|
||||
|
||||
#define DBGDIDR (DEBUG_REGSITER_BASE + (0 * 4)) // Debug ID
|
||||
#define DBGWFAR (DEBUG_REGSITER_BASE + (6 * 4)) // Watchpoint Fault Address
|
||||
#define DBGVCR (DEBUG_REGSITER_BASE + (7 * 4)) // Vector Catch
|
||||
#define DBGECR (DEBUG_REGSITER_BASE + (9 * 4)) // Event Catch
|
||||
#define DBGDTRRX (DEBUG_REGSITER_BASE + (32 * 4)) // Host to Target Data Transfer
|
||||
#define DBGITR (DEBUG_REGSITER_BASE + (33 * 4)) // WO Instruction Transfer
|
||||
#define DBGDSCR (DEBUG_REGSITER_BASE + (34 * 4)) // Debug Status and Control
|
||||
#define DBGDTRTX (DEBUG_REGSITER_BASE + (35 * 4)) // Target to Host Data Transfer
|
||||
#define DBGDRCR (DEBUG_REGSITER_BASE + (36 * 4)) // Debug Run Control
|
||||
#define DBGEACR (DEBUG_REGSITER_BASE + (37 * 4)) // External Auxiliary Control
|
||||
#define DBGPCSR (DEBUG_REGSITER_BASE + (40 * 4)) // Program Counter Sampling
|
||||
#define DBGCIDSR (DEBUG_REGSITER_BASE + (41 * 4)) // Context ID Sampling
|
||||
#define DBGVIDSR (DEBUG_REGSITER_BASE + (42 * 4)) // Virtualization ID Sampling
|
||||
#define DBGBVR0 (DEBUG_REGSITER_BASE + (64 * 4)) // Breakpoint Value
|
||||
#define DBGBVR1 (DEBUG_REGSITER_BASE + (65 * 4)) // Breakpoint Value
|
||||
#define DBGBVR2 (DEBUG_REGSITER_BASE + (66 * 4)) // Breakpoint Value
|
||||
#define DBGBVR3 (DEBUG_REGSITER_BASE + (67 * 4)) // Breakpoint Value
|
||||
#define DBGBVR4 (DEBUG_REGSITER_BASE + (68 * 4)) // Breakpoint Value
|
||||
#define DBGBVR5 (DEBUG_REGSITER_BASE + (69 * 4)) // Breakpoint Value
|
||||
#define DBGBVR6 (DEBUG_REGSITER_BASE + (70 * 4)) // Breakpoint Value
|
||||
#define DBGBVR7 (DEBUG_REGSITER_BASE + (71 * 4)) // Breakpoint Value
|
||||
#define DBGBVR8 (DEBUG_REGSITER_BASE + (72 * 4)) // Breakpoint Value
|
||||
#define DBGBVR9 (DEBUG_REGSITER_BASE + (73 * 4)) // Breakpoint Value
|
||||
#define DBGBVR10 (DEBUG_REGSITER_BASE + (74 * 4)) // Breakpoint Value
|
||||
#define DBGBVR11 (DEBUG_REGSITER_BASE + (75 * 4)) // Breakpoint Value
|
||||
#define DBGBVR12 (DEBUG_REGSITER_BASE + (76 * 4)) // Breakpoint Value
|
||||
#define DBGBVR13 (DEBUG_REGSITER_BASE + (77 * 4)) // Breakpoint Value
|
||||
#define DBGBVR14 (DEBUG_REGSITER_BASE + (78 * 4)) // Breakpoint Value
|
||||
#define DBGBVR15 (DEBUG_REGSITER_BASE + (79 * 4)) // Breakpoint Value
|
||||
#define DBGBCR0 (DEBUG_REGSITER_BASE + (80 * 4)) // Breakpoint Control
|
||||
#define DBGBCR1 (DEBUG_REGSITER_BASE + (81 * 4)) // Breakpoint Control
|
||||
#define DBGBCR2 (DEBUG_REGSITER_BASE + (82 * 4)) // Breakpoint Control
|
||||
#define DBGBCR3 (DEBUG_REGSITER_BASE + (83 * 4)) // Breakpoint Control
|
||||
#define DBGBCR4 (DEBUG_REGSITER_BASE + (84 * 4)) // Breakpoint Control
|
||||
#define DBGBCR5 (DEBUG_REGSITER_BASE + (85 * 4)) // Breakpoint Control
|
||||
#define DBGBCR6 (DEBUG_REGSITER_BASE + (86 * 4)) // Breakpoint Control
|
||||
#define DBGBCR7 (DEBUG_REGSITER_BASE + (87 * 4)) // Breakpoint Control
|
||||
#define DBGBCR8 (DEBUG_REGSITER_BASE + (88 * 4)) // Breakpoint Control
|
||||
#define DBGBCR9 (DEBUG_REGSITER_BASE + (89 * 4)) // Breakpoint Control
|
||||
#define DBGBCR10 (DEBUG_REGSITER_BASE + (90 * 4)) // Breakpoint Control
|
||||
#define DBGBCR11 (DEBUG_REGSITER_BASE + (91 * 4)) // Breakpoint Control
|
||||
#define DBGBCR12 (DEBUG_REGSITER_BASE + (92 * 4)) // Breakpoint Control
|
||||
#define DBGBCR13 (DEBUG_REGSITER_BASE + (93 * 4)) // Breakpoint Control
|
||||
#define DBGBCR14 (DEBUG_REGSITER_BASE + (94 * 4)) // Breakpoint Control
|
||||
#define DBGBCR15 (DEBUG_REGSITER_BASE + (95 * 4)) // Breakpoint Control
|
||||
#define DBGWVR0 (DEBUG_REGSITER_BASE + (96 * 4)) // Watchpoint Value
|
||||
#define DBGWVR1 (DEBUG_REGSITER_BASE + (97 * 4)) // Watchpoint Value
|
||||
#define DBGWVR2 (DEBUG_REGSITER_BASE + (98 * 4)) // Watchpoint Value
|
||||
#define DBGWVR3 (DEBUG_REGSITER_BASE + (99 * 4)) // Watchpoint Value
|
||||
#define DBGWVR4 (DEBUG_REGSITER_BASE + (100 * 4)) // Watchpoint Value
|
||||
#define DBGWVR5 (DEBUG_REGSITER_BASE + (101 * 4)) // Watchpoint Value
|
||||
#define DBGWVR6 (DEBUG_REGSITER_BASE + (102 * 4)) // Watchpoint Value
|
||||
#define DBGWVR7 (DEBUG_REGSITER_BASE + (103 * 4)) // Watchpoint Value
|
||||
#define DBGWVR8 (DEBUG_REGSITER_BASE + (104 * 4)) // Watchpoint Value
|
||||
#define DBGWVR9 (DEBUG_REGSITER_BASE + (105 * 4)) // Watchpoint Value
|
||||
#define DBGWVR10 (DEBUG_REGSITER_BASE + (106 * 4)) // Watchpoint Value
|
||||
#define DBGWVR11 (DEBUG_REGSITER_BASE + (107 * 4)) // Watchpoint Value
|
||||
#define DBGWVR12 (DEBUG_REGSITER_BASE + (108 * 4)) // Watchpoint Value
|
||||
#define DBGWVR13 (DEBUG_REGSITER_BASE + (109 * 4)) // Watchpoint Value
|
||||
#define DBGWVR14 (DEBUG_REGSITER_BASE + (110 * 4)) // Watchpoint Value
|
||||
#define DBGWVR15 (DEBUG_REGSITER_BASE + (111 * 4)) // Watchpoint Value
|
||||
#define DBGWCR0 (DEBUG_REGSITER_BASE + (112 * 4)) // Watchpoint Control
|
||||
#define DBGWCR1 (DEBUG_REGSITER_BASE + (113 * 4)) // Watchpoint Control
|
||||
#define DBGWCR2 (DEBUG_REGSITER_BASE + (114 * 4)) // Watchpoint Control
|
||||
#define DBGWCR3 (DEBUG_REGSITER_BASE + (115 * 4)) // Watchpoint Control
|
||||
#define DBGWCR4 (DEBUG_REGSITER_BASE + (116 * 4)) // Watchpoint Control
|
||||
#define DBGWCR5 (DEBUG_REGSITER_BASE + (117 * 4)) // Watchpoint Control
|
||||
#define DBGWCR6 (DEBUG_REGSITER_BASE + (118 * 4)) // Watchpoint Control
|
||||
#define DBGWCR7 (DEBUG_REGSITER_BASE + (119 * 4)) // Watchpoint Control
|
||||
#define DBGWCR8 (DEBUG_REGSITER_BASE + (120 * 4)) // Watchpoint Control
|
||||
#define DBGWCR9 (DEBUG_REGSITER_BASE + (121 * 4)) // Watchpoint Control
|
||||
#define DBGWCR10 (DEBUG_REGSITER_BASE + (122 * 4)) // Watchpoint Control
|
||||
#define DBGWCR11 (DEBUG_REGSITER_BASE + (123 * 4)) // Watchpoint Control
|
||||
#define DBGWCR12 (DEBUG_REGSITER_BASE + (124 * 4)) // Watchpoint Control
|
||||
#define DBGWCR13 (DEBUG_REGSITER_BASE + (125 * 4)) // Watchpoint Control
|
||||
#define DBGWCR14 (DEBUG_REGSITER_BASE + (126 * 4)) // Watchpoint Control
|
||||
#define DBGWCR15 (DEBUG_REGSITER_BASE + (127 * 4)) // Watchpoint Control
|
||||
#define DBGBXVR0 (DEBUG_REGSITER_BASE + (144 * 4)) // Breakpoint Extended Valueb
|
||||
#define DBGBXVR1 (DEBUG_REGSITER_BASE + (145 * 4)) // Breakpoint Extended Valueb
|
||||
#define DBGBXVR2 (DEBUG_REGSITER_BASE + (146 * 4)) // Breakpoint Extended Valueb
|
||||
#define DBGBXVR3 (DEBUG_REGSITER_BASE + (147 * 4)) // Breakpoint Extended Valueb
|
||||
#define DBGBXVR4 (DEBUG_REGSITER_BASE + (148 * 4)) // Breakpoint Extended Valueb
|
||||
#define DBGBXVR5 (DEBUG_REGSITER_BASE + (149 * 4)) // Breakpoint Extended Valueb
|
||||
#define DBGBXVR6 (DEBUG_REGSITER_BASE + (150 * 4)) // Breakpoint Extended Valueb
|
||||
#define DBGBXVR7 (DEBUG_REGSITER_BASE + (151 * 4)) // Breakpoint Extended Valueb
|
||||
#define DBGBXVR8 (DEBUG_REGSITER_BASE + (152 * 4)) // Breakpoint Extended Valueb
|
||||
#define DBGBXVR9 (DEBUG_REGSITER_BASE + (153 * 4)) // Breakpoint Extended Valueb
|
||||
#define DBGBXVR10 (DEBUG_REGSITER_BASE + (154 * 4)) // Breakpoint Extended Valueb
|
||||
#define DBGBXVR11 (DEBUG_REGSITER_BASE + (155 * 4)) // Breakpoint Extended Valueb
|
||||
#define DBGBXVR12 (DEBUG_REGSITER_BASE + (156 * 4)) // Breakpoint Extended Valueb
|
||||
#define DBGBXVR13 (DEBUG_REGSITER_BASE + (157 * 4)) // Breakpoint Extended Valueb
|
||||
#define DBGBXVR14 (DEBUG_REGSITER_BASE + (158 * 4)) // Breakpoint Extended Valueb
|
||||
#define DBGBXVR15 (DEBUG_REGSITER_BASE + (159 * 4)) // Breakpoint Extended Valueb
|
||||
#define DBGOSLAR (DEBUG_REGSITER_BASE + (192 * 4)) // OS Lock Access
|
||||
#define DBGOSLSR (DEBUG_REGSITER_BASE + (193 * 4)) // OS Lock Status
|
||||
#define DBGPRCR (DEBUG_REGSITER_BASE + (196 * 4)) // Powerdown and Reset Control
|
||||
#define DBGPRSR (DEBUG_REGSITER_BASE + (197 * 4)) // Powerdown and Reset Status
|
||||
#define DBGITCTRL (DEBUG_REGSITER_BASE + (960 * 4)) // Integration Mode Control
|
||||
#define DBGCLAIMSET (DEBUG_REGSITER_BASE + (1000 * 4)) // Claim Tag Set
|
||||
#define DBGCLAIMCLR (DEBUG_REGSITER_BASE + (1001 * 4)) // Claim Tag Clear
|
||||
#define DBGLAR (DEBUG_REGSITER_BASE + (1004 * 4)) // Lock Access
|
||||
#define DBGLSR (DEBUG_REGSITER_BASE + (1005 * 4)) // Lock Status
|
||||
#define DBGAUTHSTATUS (DEBUG_REGSITER_BASE + (1006 * 4)) // Authentication Status
|
||||
#define DBGDEVID2 (DEBUG_REGSITER_BASE + (1008 * 4)) // Debug Device ID 2
|
||||
#define DBGDEVID1 (DEBUG_REGSITER_BASE + (1009 * 4)) // Debug Device ID 1
|
||||
#define DBGDEVID (DEBUG_REGSITER_BASE + (1010 * 4)) // Debug Device ID
|
||||
#define DBGDEVTYPE (DEBUG_REGSITER_BASE + (1011 * 4)) // Device Type
|
||||
#define DBGPID0 (DEBUG_REGSITER_BASE + (1012 * 4)) // Debug Peripheral ID
|
||||
#define DBGPID1 (DEBUG_REGSITER_BASE + (1013 * 4)) // Debug Peripheral ID
|
||||
#define DBGPID2 (DEBUG_REGSITER_BASE + (1014 * 4)) // Debug Peripheral ID
|
||||
#define DBGPID3 (DEBUG_REGSITER_BASE + (1015 * 4)) // Debug Peripheral ID
|
||||
#define DBGPID4 (DEBUG_REGSITER_BASE + (1016 * 4)) // Debug Peripheral ID
|
||||
#define DBGCID0 (DEBUG_REGSITER_BASE + (1020 * 4)) // Debug Component ID
|
||||
#define DBGCID1 (DEBUG_REGSITER_BASE + (1021 * 4)) // Debug Component ID
|
||||
#define DBGCID2 (DEBUG_REGSITER_BASE + (1022 * 4)) // Debug Component ID
|
||||
#define DBGCID3 (DEBUG_REGSITER_BASE + (1023 * 4)) // Debug Component ID
|
||||
|
||||
#endif
|
||||
@@ -1,168 +0,0 @@
|
||||
/**
|
||||
* @file debug_cm.h
|
||||
* @brief Access to ARM DAP (Cortex-M) using CMSIS-DAP protocol
|
||||
*
|
||||
* DAPLink Interface Firmware
|
||||
* Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef DEBUG_CM_H
|
||||
#define DEBUG_CM_H
|
||||
|
||||
#include "DAP.h"
|
||||
|
||||
// SWD register access
|
||||
#define SWD_REG_AP (1)
|
||||
#define SWD_REG_DP (0)
|
||||
#define SWD_REG_R (1<<1)
|
||||
#define SWD_REG_W (0<<1)
|
||||
#define SWD_REG_ADR(a) (a & 0x0c)
|
||||
|
||||
// Abort Register definitions
|
||||
#define DAPABORT 0x00000001 // DAP Abort
|
||||
#define STKCMPCLR 0x00000002 // Clear STICKYCMP Flag (SW Only)
|
||||
#define STKERRCLR 0x00000004 // Clear STICKYERR Flag (SW Only)
|
||||
#define WDERRCLR 0x00000008 // Clear WDATAERR Flag (SW Only)
|
||||
#define ORUNERRCLR 0x00000010 // Clear STICKYORUN Flag (SW Only)
|
||||
|
||||
// Debug Control and Status definitions
|
||||
#define ORUNDETECT 0x00000001 // Overrun Detect
|
||||
#define STICKYORUN 0x00000002 // Sticky Overrun
|
||||
#define TRNMODE 0x0000000C // Transfer Mode Mask
|
||||
#define TRNNORMAL 0x00000000 // Transfer Mode: Normal
|
||||
#define TRNVERIFY 0x00000004 // Transfer Mode: Pushed Verify
|
||||
#define TRNCOMPARE 0x00000008 // Transfer Mode: Pushed Compare
|
||||
#define STICKYCMP 0x00000010 // Sticky Compare
|
||||
#define STICKYERR 0x00000020 // Sticky Error
|
||||
#define READOK 0x00000040 // Read OK (SW Only)
|
||||
#define WDATAERR 0x00000080 // Write Data Error (SW Only)
|
||||
#define MASKLANE 0x00000F00 // Mask Lane Mask
|
||||
#define MASKLANE0 0x00000100 // Mask Lane 0
|
||||
#define MASKLANE1 0x00000200 // Mask Lane 1
|
||||
#define MASKLANE2 0x00000400 // Mask Lane 2
|
||||
#define MASKLANE3 0x00000800 // Mask Lane 3
|
||||
#define TRNCNT 0x001FF000 // Transaction Counter Mask
|
||||
#define CDBGRSTREQ 0x04000000 // Debug Reset Request
|
||||
#define CDBGRSTACK 0x08000000 // Debug Reset Acknowledge
|
||||
#define CDBGPWRUPREQ 0x10000000 // Debug Power-up Request
|
||||
#define CDBGPWRUPACK 0x20000000 // Debug Power-up Acknowledge
|
||||
#define CSYSPWRUPREQ 0x40000000 // System Power-up Request
|
||||
#define CSYSPWRUPACK 0x80000000 // System Power-up Acknowledge
|
||||
|
||||
// Debug Select Register definitions
|
||||
#define CTRLSEL 0x00000001 // CTRLSEL (SW Only)
|
||||
#define APBANKSEL 0x000000F0 // APBANKSEL Mask
|
||||
#define APSEL 0xFF000000 // APSEL Mask
|
||||
|
||||
// Access Port Register Addresses
|
||||
#define AP_CSW 0x00 // Control and Status Word
|
||||
#define AP_TAR 0x04 // Transfer Address
|
||||
#define AP_DRW 0x0C // Data Read/Write
|
||||
#define AP_BD0 0x10 // Banked Data 0
|
||||
#define AP_BD1 0x14 // Banked Data 1
|
||||
#define AP_BD2 0x18 // Banked Data 2
|
||||
#define AP_BD3 0x1C // Banked Data 3
|
||||
#define AP_ROM 0xF8 // Debug ROM Address
|
||||
#define AP_IDR 0xFC // Identification Register
|
||||
|
||||
// AP Control and Status Word definitions
|
||||
#define CSW_SIZE 0x00000007 // Access Size: Selection Mask
|
||||
#define CSW_SIZE8 0x00000000 // Access Size: 8-bit
|
||||
#define CSW_SIZE16 0x00000001 // Access Size: 16-bit
|
||||
#define CSW_SIZE32 0x00000002 // Access Size: 32-bit
|
||||
#define CSW_ADDRINC 0x00000030 // Auto Address Increment Mask
|
||||
#define CSW_NADDRINC 0x00000000 // No Address Increment
|
||||
#define CSW_SADDRINC 0x00000010 // Single Address Increment
|
||||
#define CSW_PADDRINC 0x00000020 // Packed Address Increment
|
||||
#define CSW_DBGSTAT 0x00000040 // Debug Status
|
||||
#define CSW_TINPROG 0x00000080 // Transfer in progress
|
||||
#define CSW_HPROT 0x02000000 // User/Privilege Control
|
||||
#define CSW_MSTRTYPE 0x20000000 // Master Type Mask
|
||||
#define CSW_MSTRCORE 0x00000000 // Master Type: Core
|
||||
#define CSW_MSTRDBG 0x20000000 // Master Type: Debug
|
||||
#define CSW_RESERVED 0x01000000 // Reserved Value
|
||||
|
||||
// Core Debug Register Address Offsets
|
||||
#define DBG_OFS 0x0DF0 // Debug Register Offset inside NVIC
|
||||
#define DBG_HCSR_OFS 0x00 // Debug Halting Control & Status Register
|
||||
#define DBG_CRSR_OFS 0x04 // Debug Core Register Selector Register
|
||||
#define DBG_CRDR_OFS 0x08 // Debug Core Register Data Register
|
||||
#define DBG_EMCR_OFS 0x0C // Debug Exception & Monitor Control Register
|
||||
|
||||
// Core Debug Register Addresses
|
||||
#define DBG_HCSR (DBG_Addr + DBG_HCSR_OFS)
|
||||
#define DBG_CRSR (DBG_Addr + DBG_CRSR_OFS)
|
||||
#define DBG_CRDR (DBG_Addr + DBG_CRDR_OFS)
|
||||
#define DBG_EMCR (DBG_Addr + DBG_EMCR_OFS)
|
||||
|
||||
// Debug Halting Control and Status Register definitions
|
||||
#define C_DEBUGEN 0x00000001 // Debug Enable
|
||||
#define C_HALT 0x00000002 // Halt
|
||||
#define C_STEP 0x00000004 // Step
|
||||
#define C_MASKINTS 0x00000008 // Mask Interrupts
|
||||
#define C_SNAPSTALL 0x00000020 // Snap Stall
|
||||
#define S_REGRDY 0x00010000 // Register R/W Ready Flag
|
||||
#define S_HALT 0x00020000 // Halt Flag
|
||||
#define S_SLEEP 0x00040000 // Sleep Flag
|
||||
#define S_LOCKUP 0x00080000 // Lockup Flag
|
||||
#define S_RETIRE_ST 0x01000000 // Sticky Retire Flag
|
||||
#define S_RESET_ST 0x02000000 // Sticky Reset Flag
|
||||
#define DBGKEY 0xA05F0000 // Debug Key
|
||||
|
||||
// Debug Exception and Monitor Control Register definitions
|
||||
#define VC_CORERESET 0x00000001 // Reset Vector Catch
|
||||
#define VC_MMERR 0x00000010 // Debug Trap on MMU Fault
|
||||
#define VC_NOCPERR 0x00000020 // Debug Trap on No Coprocessor Fault
|
||||
#define VC_CHKERR 0x00000040 // Debug Trap on Checking Error Fault
|
||||
#define VC_STATERR 0x00000080 // Debug Trap on State Error Fault
|
||||
#define VC_BUSERR 0x00000100 // Debug Trap on Bus Error Fault
|
||||
#define VC_INTERR 0x00000200 // Debug Trap on Interrupt Error Fault
|
||||
#define VC_HARDERR 0x00000400 // Debug Trap on Hard Fault
|
||||
#define MON_EN 0x00010000 // Monitor Enable
|
||||
#define MON_PEND 0x00020000 // Monitor Pend
|
||||
#define MON_STEP 0x00040000 // Monitor Step
|
||||
#define MON_REQ 0x00080000 // Monitor Request
|
||||
#define TRCENA 0x01000000 // Trace Enable (DWT, ITM, ETM, TPIU)
|
||||
|
||||
// NVIC: Interrupt Controller Type Register
|
||||
#define NVIC_ICT (NVIC_Addr + 0x0004)
|
||||
#define INTLINESNUM 0x0000001F // Interrupt Line Numbers
|
||||
|
||||
// NVIC: CPUID Base Register
|
||||
#define NVIC_CPUID (NVIC_Addr + 0x0D00)
|
||||
#define CPUID_PARTNO 0x0000FFF0 // Part Number Mask
|
||||
#define CPUID_REVISION 0x0000000F // Revision Mask
|
||||
#define CPUID_VARIANT 0x00F00000 // Variant Mask
|
||||
|
||||
// NVIC: Application Interrupt/Reset Control Register
|
||||
#define NVIC_AIRCR (NVIC_Addr + 0x0D0C)
|
||||
#define VECTRESET 0x00000001 // Reset Cortex-M (except Debug)
|
||||
#define VECTCLRACTIVE 0x00000002 // Clear Active Vector Bit
|
||||
#define SYSRESETREQ 0x00000004 // Reset System (except Debug)
|
||||
#define VECTKEY 0x05FA0000 // Write Key
|
||||
|
||||
// NVIC: Debug Fault Status Register
|
||||
#define NVIC_DFSR (NVIC_Addr + 0x0D30)
|
||||
#define HALTED 0x00000001 // Halt Flag
|
||||
#define BKPT 0x00000002 // BKPT Flag
|
||||
#define DWTTRAP 0x00000004 // DWT Match
|
||||
#define VCATCH 0x00000008 // Vector Catch Flag
|
||||
#define EXTERNAL 0x00000010 // External Debug Request
|
||||
|
||||
// Data Watchpoint and Trace unit
|
||||
#define DWT_PCSR 0xe000101c // DWT PC Sampling Register
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user