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433 lines
11 KiB
433 lines
11 KiB
/** |
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****************************************************************************** |
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* @file stm32f10x_cec.c |
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* @author MCD Application Team |
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* @version V3.5.0 |
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* @date 11-March-2011 |
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* @brief This file provides all the CEC firmware functions. |
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****************************************************************************** |
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* @attention |
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* |
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
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* |
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* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> |
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****************************************************************************** |
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*/ |
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/* Includes ------------------------------------------------------------------*/ |
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#include "stm32f10x_cec.h" |
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#include "stm32f10x_rcc.h" |
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/** @addtogroup STM32F10x_StdPeriph_Driver |
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* @{ |
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*/ |
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/** @defgroup CEC |
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* @brief CEC driver modules |
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* @{ |
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*/ |
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/** @defgroup CEC_Private_TypesDefinitions |
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* @{ |
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*/ |
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/** |
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* @} |
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*/ |
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/** @defgroup CEC_Private_Defines |
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* @{ |
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*/ |
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/* ------------ CEC registers bit address in the alias region ----------- */ |
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#define CEC_OFFSET (CEC_BASE - PERIPH_BASE) |
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/* --- CFGR Register ---*/ |
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/* Alias word address of PE bit */ |
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#define CFGR_OFFSET (CEC_OFFSET + 0x00) |
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#define PE_BitNumber 0x00 |
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#define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4)) |
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/* Alias word address of IE bit */ |
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#define IE_BitNumber 0x01 |
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#define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4)) |
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/* --- CSR Register ---*/ |
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/* Alias word address of TSOM bit */ |
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#define CSR_OFFSET (CEC_OFFSET + 0x10) |
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#define TSOM_BitNumber 0x00 |
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#define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4)) |
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/* Alias word address of TEOM bit */ |
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#define TEOM_BitNumber 0x01 |
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#define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4)) |
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#define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */ |
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#define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */ |
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/** |
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* @} |
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*/ |
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/** @defgroup CEC_Private_Macros |
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* @{ |
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*/ |
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/** |
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* @} |
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*/ |
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/** @defgroup CEC_Private_Variables |
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* @{ |
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*/ |
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/** |
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* @} |
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*/ |
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/** @defgroup CEC_Private_FunctionPrototypes |
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* @{ |
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*/ |
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/** |
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* @} |
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*/ |
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/** @defgroup CEC_Private_Functions |
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* @{ |
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*/ |
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/** |
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* @brief Deinitializes the CEC peripheral registers to their default reset |
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* values. |
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* @param None |
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* @retval None |
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*/ |
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void CEC_DeInit(void) |
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{ |
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/* Enable CEC reset state */ |
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE); |
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/* Release CEC from reset state */ |
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); |
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} |
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/** |
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* @brief Initializes the CEC peripheral according to the specified |
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* parameters in the CEC_InitStruct. |
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* @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that |
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* contains the configuration information for the specified |
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* CEC peripheral. |
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* @retval None |
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*/ |
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void CEC_Init(CEC_InitTypeDef* CEC_InitStruct) |
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{ |
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uint16_t tmpreg = 0; |
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/* Check the parameters */ |
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assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode)); |
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assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode)); |
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/*---------------------------- CEC CFGR Configuration -----------------*/ |
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/* Get the CEC CFGR value */ |
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tmpreg = CEC->CFGR; |
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/* Clear BTEM and BPEM bits */ |
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tmpreg &= CFGR_CLEAR_Mask; |
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/* Configure CEC: Bit Timing Error and Bit Period Error */ |
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tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode); |
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/* Write to CEC CFGR register*/ |
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CEC->CFGR = tmpreg; |
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} |
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/** |
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* @brief Enables or disables the specified CEC peripheral. |
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* @param NewState: new state of the CEC peripheral. |
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* This parameter can be: ENABLE or DISABLE. |
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* @retval None |
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*/ |
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void CEC_Cmd(FunctionalState NewState) |
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{ |
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/* Check the parameters */ |
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assert_param(IS_FUNCTIONAL_STATE(NewState)); |
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*(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState; |
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if(NewState == DISABLE) |
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{ |
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/* Wait until the PE bit is cleared by hardware (Idle Line detected) */ |
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while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET) |
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{ |
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} |
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} |
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} |
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/** |
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* @brief Enables or disables the CEC interrupt. |
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* @param NewState: new state of the CEC interrupt. |
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* This parameter can be: ENABLE or DISABLE. |
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* @retval None |
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*/ |
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void CEC_ITConfig(FunctionalState NewState) |
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{ |
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/* Check the parameters */ |
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assert_param(IS_FUNCTIONAL_STATE(NewState)); |
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*(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState; |
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} |
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/** |
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* @brief Defines the Own Address of the CEC device. |
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* @param CEC_OwnAddress: The CEC own address |
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* @retval None |
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*/ |
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void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress) |
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{ |
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/* Check the parameters */ |
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assert_param(IS_CEC_ADDRESS(CEC_OwnAddress)); |
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/* Set the CEC own address */ |
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CEC->OAR = CEC_OwnAddress; |
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} |
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/** |
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* @brief Sets the CEC prescaler value. |
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* @param CEC_Prescaler: CEC prescaler new value |
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* @retval None |
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*/ |
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void CEC_SetPrescaler(uint16_t CEC_Prescaler) |
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{ |
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/* Check the parameters */ |
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assert_param(IS_CEC_PRESCALER(CEC_Prescaler)); |
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/* Set the Prescaler value*/ |
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CEC->PRES = CEC_Prescaler; |
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} |
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/** |
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* @brief Transmits single data through the CEC peripheral. |
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* @param Data: the data to transmit. |
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* @retval None |
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*/ |
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void CEC_SendDataByte(uint8_t Data) |
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{ |
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/* Transmit Data */ |
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CEC->TXD = Data ; |
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} |
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/** |
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* @brief Returns the most recent received data by the CEC peripheral. |
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* @param None |
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* @retval The received data. |
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*/ |
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uint8_t CEC_ReceiveDataByte(void) |
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{ |
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/* Receive Data */ |
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return (uint8_t)(CEC->RXD); |
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} |
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/** |
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* @brief Starts a new message. |
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* @param None |
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* @retval None |
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*/ |
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void CEC_StartOfMessage(void) |
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{ |
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/* Starts of new message */ |
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*(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1; |
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} |
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/** |
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* @brief Transmits message with or without an EOM bit. |
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* @param NewState: new state of the CEC Tx End Of Message. |
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* This parameter can be: ENABLE or DISABLE. |
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* @retval None |
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*/ |
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void CEC_EndOfMessageCmd(FunctionalState NewState) |
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{ |
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/* Check the parameters */ |
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assert_param(IS_FUNCTIONAL_STATE(NewState)); |
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/* The data byte will be transmitted with or without an EOM bit*/ |
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*(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState; |
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} |
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/** |
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* @brief Gets the CEC flag status |
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* @param CEC_FLAG: specifies the CEC flag to check. |
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* This parameter can be one of the following values: |
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* @arg CEC_FLAG_BTE: Bit Timing Error |
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* @arg CEC_FLAG_BPE: Bit Period Error |
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* @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error |
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* @arg CEC_FLAG_SBE: Start Bit Error |
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* @arg CEC_FLAG_ACKE: Block Acknowledge Error |
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* @arg CEC_FLAG_LINE: Line Error |
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* @arg CEC_FLAG_TBTFE: Tx Block Transfer Finished Error |
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* @arg CEC_FLAG_TEOM: Tx End Of Message |
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* @arg CEC_FLAG_TERR: Tx Error |
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* @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished |
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* @arg CEC_FLAG_RSOM: Rx Start Of Message |
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* @arg CEC_FLAG_REOM: Rx End Of Message |
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* @arg CEC_FLAG_RERR: Rx Error |
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* @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished |
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* @retval The new state of CEC_FLAG (SET or RESET) |
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*/ |
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FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG) |
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{ |
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FlagStatus bitstatus = RESET; |
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uint32_t cecreg = 0, cecbase = 0; |
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/* Check the parameters */ |
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assert_param(IS_CEC_GET_FLAG(CEC_FLAG)); |
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/* Get the CEC peripheral base address */ |
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cecbase = (uint32_t)(CEC_BASE); |
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/* Read flag register index */ |
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cecreg = CEC_FLAG >> 28; |
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/* Get bit[23:0] of the flag */ |
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CEC_FLAG &= FLAG_Mask; |
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if(cecreg != 0) |
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{ |
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/* Flag in CEC ESR Register */ |
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CEC_FLAG = (uint32_t)(CEC_FLAG >> 16); |
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/* Get the CEC ESR register address */ |
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cecbase += 0xC; |
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} |
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else |
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{ |
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/* Get the CEC CSR register address */ |
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cecbase += 0x10; |
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} |
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if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET) |
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{ |
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/* CEC_FLAG is set */ |
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bitstatus = SET; |
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} |
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else |
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{ |
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/* CEC_FLAG is reset */ |
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bitstatus = RESET; |
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} |
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/* Return the CEC_FLAG status */ |
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return bitstatus; |
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} |
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/** |
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* @brief Clears the CEC's pending flags. |
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* @param CEC_FLAG: specifies the flag to clear. |
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* This parameter can be any combination of the following values: |
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* @arg CEC_FLAG_TERR: Tx Error |
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* @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished |
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* @arg CEC_FLAG_RSOM: Rx Start Of Message |
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* @arg CEC_FLAG_REOM: Rx End Of Message |
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* @arg CEC_FLAG_RERR: Rx Error |
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* @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished |
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* @retval None |
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*/ |
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void CEC_ClearFlag(uint32_t CEC_FLAG) |
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{ |
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uint32_t tmp = 0x0; |
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/* Check the parameters */ |
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assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG)); |
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tmp = CEC->CSR & 0x2; |
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/* Clear the selected CEC flags */ |
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CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp); |
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} |
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/** |
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* @brief Checks whether the specified CEC interrupt has occurred or not. |
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* @param CEC_IT: specifies the CEC interrupt source to check. |
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* This parameter can be one of the following values: |
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* @arg CEC_IT_TERR: Tx Error |
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* @arg CEC_IT_TBTF: Tx Block Transfer Finished |
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* @arg CEC_IT_RERR: Rx Error |
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* @arg CEC_IT_RBTF: Rx Block Transfer Finished |
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* @retval The new state of CEC_IT (SET or RESET). |
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*/ |
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ITStatus CEC_GetITStatus(uint8_t CEC_IT) |
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{ |
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ITStatus bitstatus = RESET; |
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uint32_t enablestatus = 0; |
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/* Check the parameters */ |
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assert_param(IS_CEC_GET_IT(CEC_IT)); |
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/* Get the CEC IT enable bit status */ |
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enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ; |
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/* Check the status of the specified CEC interrupt */ |
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if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus) |
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{ |
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/* CEC_IT is set */ |
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bitstatus = SET; |
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} |
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else |
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{ |
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/* CEC_IT is reset */ |
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bitstatus = RESET; |
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} |
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/* Return the CEC_IT status */ |
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return bitstatus; |
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} |
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/** |
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* @brief Clears the CEC's interrupt pending bits. |
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* @param CEC_IT: specifies the CEC interrupt pending bit to clear. |
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* This parameter can be any combination of the following values: |
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* @arg CEC_IT_TERR: Tx Error |
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* @arg CEC_IT_TBTF: Tx Block Transfer Finished |
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* @arg CEC_IT_RERR: Rx Error |
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* @arg CEC_IT_RBTF: Rx Block Transfer Finished |
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* @retval None |
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*/ |
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void CEC_ClearITPendingBit(uint16_t CEC_IT) |
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{ |
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uint32_t tmp = 0x0; |
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/* Check the parameters */ |
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assert_param(IS_CEC_GET_IT(CEC_IT)); |
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tmp = CEC->CSR & 0x2; |
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/* Clear the selected CEC interrupt pending bits */ |
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CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp); |
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} |
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/** |
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* @} |
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*/ |
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/** |
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* @} |
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*/ |
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/** |
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* @} |
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*/ |
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/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
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