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rushxrushx
2022-07-13 16:43:04 +08:00
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DAP.c
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DAP.h
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/******************************************************************************
* @file DAP.h
* @brief CMSIS-DAP Definitions
* @version V1.00
* @date 31. May 2012
*
* @note
* Copyright (C) 2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __DAP_H__
#define __DAP_H__
// DAP Command IDs
#define ID_DAP_Info 0x00
#define ID_DAP_LED 0x01
#define ID_DAP_Connect 0x02
#define ID_DAP_Disconnect 0x03
#define ID_DAP_TransferConfigure 0x04
#define ID_DAP_Transfer 0x05
#define ID_DAP_TransferBlock 0x06
#define ID_DAP_TransferAbort 0x07
#define ID_DAP_WriteABORT 0x08
#define ID_DAP_Delay 0x09
#define ID_DAP_ResetTarget 0x0A
#define ID_DAP_SWJ_Pins 0x10
#define ID_DAP_SWJ_Clock 0x11
#define ID_DAP_SWJ_Sequence 0x12
#define ID_DAP_SWD_Configure 0x13
#define ID_DAP_JTAG_Sequence 0x14
#define ID_DAP_JTAG_Configure 0x15
#define ID_DAP_JTAG_IDCODE 0x16
// DAP Vendor Command IDs
#define ID_DAP_Vendor0 0x80
#define ID_DAP_Vendor1 0x81
#define ID_DAP_Vendor2 0x82
#define ID_DAP_Vendor3 0x83
#define ID_DAP_Vendor4 0x84
#define ID_DAP_Vendor5 0x85
#define ID_DAP_Vendor6 0x86
#define ID_DAP_Vendor7 0x87
#define ID_DAP_Vendor8 0x88
#define ID_DAP_Vendor9 0x89
#define ID_DAP_Vendor10 0x8A
#define ID_DAP_Vendor11 0x8B
#define ID_DAP_Vendor12 0x8C
#define ID_DAP_Vendor13 0x8D
#define ID_DAP_Vendor14 0x8E
#define ID_DAP_Vendor15 0x8F
#define ID_DAP_Vendor16 0x90
#define ID_DAP_Vendor17 0x91
#define ID_DAP_Vendor18 0x92
#define ID_DAP_Vendor19 0x93
#define ID_DAP_Vendor20 0x94
#define ID_DAP_Vendor21 0x95
#define ID_DAP_Vendor22 0x96
#define ID_DAP_Vendor23 0x97
#define ID_DAP_Vendor24 0x98
#define ID_DAP_Vendor25 0x99
#define ID_DAP_Vendor26 0x9A
#define ID_DAP_Vendor27 0x9B
#define ID_DAP_Vendor28 0x9C
#define ID_DAP_Vendor29 0x9D
#define ID_DAP_Vendor30 0x9E
#define ID_DAP_Vendor31 0x9F
#define ID_DAP_Invalid 0xFF
// DAP Status Code
#define DAP_OK 0
#define DAP_ERROR 0xFF
// DAP ID
#define DAP_ID_VENDOR 1
#define DAP_ID_PRODUCT 2
#define DAP_ID_SER_NUM 3
#define DAP_ID_FW_VER 4
#define DAP_ID_DEVICE_VENDOR 5
#define DAP_ID_DEVICE_NAME 6
#define DAP_ID_CAPABILITIES 0xF0
#define DAP_ID_PACKET_COUNT 0xFE
#define DAP_ID_PACKET_SIZE 0xFF
// DAP LEDs
#define DAP_LED_DEBUGGER_CONNECTED 0
#define DAP_LED_TARGET_RUNNING 1
// DAP Port
#define DAP_PORT_AUTODETECT 0 // Autodetect Port
#define DAP_PORT_DISABLED 0 // Port Disabled (I/O pins in High-Z)
#define DAP_PORT_SWD 1 // SWD Port (SWCLK, SWDIO) + nRESET
#define DAP_PORT_JTAG 2 // JTAG Port (TCK, TMS, TDI, TDO, nTRST) + nRESET
// DAP SWJ Pins
#define DAP_SWJ_SWCLK_TCK 0 // SWCLK/TCK
#define DAP_SWJ_SWDIO_TMS 1 // SWDIO/TMS
#define DAP_SWJ_TDI 2 // TDI
#define DAP_SWJ_TDO 3 // TDO
#define DAP_SWJ_nTRST 5 // nTRST
#define DAP_SWJ_nRESET 7 // nRESET
// DAP Transfer Request
#define DAP_TRANSFER_APnDP (1 << 0)
#define DAP_TRANSFER_RnW (1 << 1)
#define DAP_TRANSFER_A2 (1 << 2)
#define DAP_TRANSFER_A3 (1 << 3)
#define DAP_TRANSFER_MATCH_VALUE (1 << 4)
#define DAP_TRANSFER_MATCH_MASK (1 << 5)
// DAP Transfer Response
#define DAP_TRANSFER_OK (1 << 0)
#define DAP_TRANSFER_WAIT (1 << 1)
#define DAP_TRANSFER_FAULT (1 << 2)
#define DAP_TRANSFER_ERROR (1 << 3)
#define DAP_TRANSFER_MISMATCH (1 << 4)
// Debug Port Register Addresses
#define DP_IDCODE 0x00 // IDCODE Register (SW Read only)
#define DP_ABORT 0x00 // Abort Register (SW Write only)
#define DP_CTRL_STAT 0x04 // Control & Status
#define DP_WCR 0x04 // Wire Control Register (SW Only)
#define DP_SELECT 0x08 // Select Register (JTAG R/W & SW W)
#define DP_RESEND 0x08 // Resend (SW Read Only)
#define DP_RDBUFF 0x0C // Read Buffer (Read Only)
// JTAG IR Codes
#define JTAG_ABORT 0x08
#define JTAG_DPACC 0x0A
#define JTAG_APACC 0x0B
#define JTAG_IDCODE 0x0E
#define JTAG_BYPASS 0x0F
// JTAG Sequence Info
#define JTAG_SEQUENCE_TCK 0x3F // TCK count
#define JTAG_SEQUENCE_TMS 0x40 // TMS value
#define JTAG_SEQUENCE_TDO 0x80 // TDO capture
#include <stddef.h>
#include <stdint.h>
// DAP Data structure
typedef struct
{
uint8_t debug_port; // Debug Port
uint8_t fast_clock; // Fast Clock Flag
uint32_t clock_delay; // Clock Delay
struct { // Transfer Configuration
uint8_t idle_cycles; // Idle cycles after transfer
uint16_t retry_count; // Number of retries after WAIT response
uint16_t match_retry; // Number of retries if read value does not match
uint32_t match_mask; // Match Mask
} transfer;
#if (DAP_SWD != 0)
struct { // SWD Configuration
uint8_t turnaround; // Turnaround period
uint8_t data_phase; // Always generate Data Phase
} swd_conf;
#endif
#if (DAP_JTAG != 0)
struct { // JTAG Device Chain
uint8_t count; // Number of devices
uint8_t index; // Device index (device at TDO has index 0)
#if (DAP_JTAG_DEV_CNT != 0)
uint8_t ir_length[DAP_JTAG_DEV_CNT]; // IR Length in bits
uint16_t ir_before[DAP_JTAG_DEV_CNT]; // Bits before IR
uint16_t ir_after [DAP_JTAG_DEV_CNT]; // Bits after IR
#endif
} jtag_dev;
#endif
} DAP_Data_t;
extern DAP_Data_t DAP_Data; // DAP Data
extern volatile uint8_t DAP_TransferAbort; // Transfer Abort Flag
// Functions
extern void SWJ_Sequence (uint32_t count, uint8_t *data);
extern void JTAG_Sequence (uint32_t info, uint8_t *tdi, uint8_t *tdo);
extern void JTAG_IR (uint32_t ir);
extern uint32_t JTAG_ReadIDCode (void);
extern void JTAG_WriteAbort (uint32_t data);
extern uint8_t JTAG_Transfer (uint8_t request, uint32_t *data);
extern uint8_t SWD_Transfer (uint8_t request, uint32_t *data);
extern void Delayms (uint32_t delay);
extern uint32_t DAP_ProcessVendorCommand(uint8_t *request, uint8_t *response);
extern uint32_t DAP_ProcessCommand(uint8_t *request, uint8_t *response);
extern void DAP_Setup(void);
// Configurable delay for clock generation
#define DELAY_SLOW_CYCLES 3 // Number of cycles for one iteration
static __forceinline void PIN_DELAY_SLOW (uint32_t delay)
{
volatile int32_t count;
count = delay;
while (--count)
{ }
}
// Fixed delay for fast clock generation
#define DELAY_FAST_CYCLES 0 // Number of cycles
static __forceinline void PIN_DELAY_FAST (void)
{
//__nop();
}
#endif /* __DAP_H__ */
JTAG_DP.c
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/******************************************************************************
* @file JTAG_DP.c
* @brief CMSIS-DAP JTAG DP I/O
* @version V1.00
* @date 31. May 2012
*
* @note
* Copyright (C) 2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include "DAP_config.h"
#include "DAP.h"
// JTAG Macros
#define PIN_TCK_SET PIN_SWCLK_TCK_SET
#define PIN_TCK_CLR PIN_SWCLK_TCK_CLR
#define PIN_TMS_SET PIN_SWDIO_TMS_SET
#define PIN_TMS_CLR PIN_SWDIO_TMS_CLR
#define JTAG_CYCLE_TCK() \
PIN_TCK_CLR(); \
PIN_DELAY(); \
PIN_TCK_SET(); \
PIN_DELAY()
#define JTAG_CYCLE_TDI(tdi) \
PIN_TDI_OUT(tdi); \
PIN_TCK_CLR(); \
PIN_DELAY(); \
PIN_TCK_SET(); \
PIN_DELAY()
#define JTAG_CYCLE_TDO(tdo) \
PIN_TCK_CLR(); \
PIN_DELAY(); \
tdo = PIN_TDO_IN(); \
PIN_TCK_SET(); \
PIN_DELAY()
#define JTAG_CYCLE_TDIO(tdi,tdo) \
PIN_TDI_OUT(tdi); \
PIN_TCK_CLR(); \
PIN_DELAY(); \
tdo = PIN_TDO_IN(); \
PIN_TCK_SET(); \
PIN_DELAY()
#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)
#if (DAP_JTAG != 0)
// Generate JTAG Sequence
// info: sequence information
// tdi: pointer to TDI generated data
// tdo: pointer to TDO captured data
// return: none
void JTAG_Sequence (uint32_t info, uint8_t *tdi, uint8_t *tdo) {
uint32_t i_val;
uint32_t o_val;
uint32_t bit;
uint32_t n, k;
n = info & JTAG_SEQUENCE_TCK;
if (n == 0) n = 64;
if (info & JTAG_SEQUENCE_TMS) {
PIN_TMS_SET();
} else {
PIN_TMS_CLR();
}
while (n) {
i_val = *tdi++;
o_val = 0;
for (k = 8; k && n; k--, n--) {
JTAG_CYCLE_TDIO(i_val, bit);
i_val >>= 1;
o_val >>= 1;
o_val |= bit << 7;
}
o_val >>= k;
if (info & JTAG_SEQUENCE_TDO) {
*tdo++ = o_val;
}
}
}
// JTAG Set IR
// ir: IR value
// return: none
#define JTAG_IR_Function(speed) /**/ \
void JTAG_IR_##speed (uint32_t ir) { \
uint32_t n; \
\
PIN_TMS_SET(); \
JTAG_CYCLE_TCK(); /* Select-DR-Scan */ \
JTAG_CYCLE_TCK(); /* Select-IR-Scan */ \
PIN_TMS_CLR(); \
JTAG_CYCLE_TCK(); /* Capture-IR */ \
JTAG_CYCLE_TCK(); /* Shift-IR */ \
\
PIN_TDI_OUT(1); \
for (n = DAP_Data.jtag_dev.ir_before[DAP_Data.jtag_dev.index]; n; n--) { \
JTAG_CYCLE_TCK(); /* Bypass before data */ \
} \
for (n = DAP_Data.jtag_dev.ir_length[DAP_Data.jtag_dev.index] - 1; n; n--) { \
JTAG_CYCLE_TDI(ir); /* Set IR bits (except last) */ \
ir >>= 1; \
} \
n = DAP_Data.jtag_dev.ir_after[DAP_Data.jtag_dev.index]; \
if (n) { \
JTAG_CYCLE_TDI(ir); /* Set last IR bit */ \
PIN_TDI_OUT(1); \
for (--n; n; n--) { \
JTAG_CYCLE_TCK(); /* Bypass after data */ \
} \
PIN_TMS_SET(); \
JTAG_CYCLE_TCK(); /* Bypass & Exit1-IR */ \
} else { \
PIN_TMS_SET(); \
JTAG_CYCLE_TDI(ir); /* Set last IR bit & Exit1-IR */ \
} \
\
JTAG_CYCLE_TCK(); /* Update-IR */ \
PIN_TMS_CLR(); \
JTAG_CYCLE_TCK(); /* Idle */ \
PIN_TDI_OUT(1); \
}
// JTAG Transfer I/O
// request: A[3:2] RnW APnDP
// data: DATA[31:0]
// return: ACK[2:0]
#define JTAG_TransferFunction(speed) /**/ \
uint8_t JTAG_Transfer##speed (uint32_t request, uint32_t *data) { \
uint32_t ack; \
uint32_t bit; \
uint32_t val; \
uint32_t n; \
\
PIN_TMS_SET(); \
JTAG_CYCLE_TCK(); /* Select-DR-Scan */ \
PIN_TMS_CLR(); \
JTAG_CYCLE_TCK(); /* Capture-DR */ \
JTAG_CYCLE_TCK(); /* Shift-DR */ \
\
for (n = DAP_Data.jtag_dev.index; n; n--) { \
JTAG_CYCLE_TCK(); /* Bypass before data */ \
} \
\
JTAG_CYCLE_TDIO(request >> 1, bit); /* Set RnW, Get ACK.0 */ \
ack = bit << 1; \
JTAG_CYCLE_TDIO(request >> 2, bit); /* Set A2, Get ACK.1 */ \
ack |= bit << 0; \
JTAG_CYCLE_TDIO(request >> 3, bit); /* Set A3, Get ACK.2 */ \
ack |= bit << 2; \
\
if (ack != DAP_TRANSFER_OK) { \
/* Exit on error */ \
PIN_TMS_SET(); \
JTAG_CYCLE_TCK(); /* Exit1-DR */ \
goto exit; \
} \
\
if (request & DAP_TRANSFER_RnW) { \
/* Read Transfer */ \
val = 0; \
for (n = 31; n; n--) { \
JTAG_CYCLE_TDO(bit); /* Get D0..D30 */ \
val |= bit << 31; \
val >>= 1; \
} \
n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1; \
if (n) { \
JTAG_CYCLE_TDO(bit); /* Get D31 */ \
for (--n; n; n--) { \
JTAG_CYCLE_TCK(); /* Bypass after data */ \
} \
PIN_TMS_SET(); \
JTAG_CYCLE_TCK(); /* Bypass & Exit1-DR */ \
} else { \
PIN_TMS_SET(); \
JTAG_CYCLE_TDO(bit); /* Get D31 & Exit1-DR */ \
} \
val |= bit << 31; \
if (data) *data = val; \
} else { \
/* Write Transfer */ \
val = *data; \
for (n = 31; n; n--) { \
JTAG_CYCLE_TDI(val); /* Set D0..D30 */ \
val >>= 1; \
} \
n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1; \
if (n) { \
JTAG_CYCLE_TDI(val); /* Set D31 */ \
for (--n; n; n--) { \
JTAG_CYCLE_TCK(); /* Bypass after data */ \
} \
PIN_TMS_SET(); \
JTAG_CYCLE_TCK(); /* Bypass & Exit1-DR */ \
} else { \
PIN_TMS_SET(); \
JTAG_CYCLE_TDI(val); /* Set D31 & Exit1-DR */ \
} \
} \
\
exit: \
JTAG_CYCLE_TCK(); /* Update-DR */ \
PIN_TMS_CLR(); \
JTAG_CYCLE_TCK(); /* Idle */ \
PIN_TDI_OUT(1); \
\
/* Idle cycles */ \
n = DAP_Data.transfer.idle_cycles; \
while (n--) { \
JTAG_CYCLE_TCK(); /* Idle */ \
} \
\
return (ack); \
}
#undef PIN_DELAY
#define PIN_DELAY() PIN_DELAY_FAST()
JTAG_IR_Function(Fast);
JTAG_TransferFunction(Fast);
#undef PIN_DELAY
#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)
JTAG_IR_Function(Slow);
JTAG_TransferFunction(Slow);
// JTAG Read IDCODE register
// return: value read
uint32_t JTAG_ReadIDCode (void) {
uint32_t bit;
uint32_t val;
uint32_t n;
PIN_TMS_SET();
JTAG_CYCLE_TCK(); /* Select-DR-Scan */
PIN_TMS_CLR();
JTAG_CYCLE_TCK(); /* Capture-DR */
JTAG_CYCLE_TCK(); /* Shift-DR */
for (n = DAP_Data.jtag_dev.index; n; n--) {
JTAG_CYCLE_TCK(); /* Bypass before data */
}
val = 0;
for (n = 31; n; n--) {
JTAG_CYCLE_TDO(bit); /* Get D0..D30 */
val |= bit << 31;
val >>= 1;
}
PIN_TMS_SET();
JTAG_CYCLE_TDO(bit); /* Get D31 & Exit1-DR */
val |= bit << 31;
JTAG_CYCLE_TCK(); /* Update-DR */
PIN_TMS_CLR();
JTAG_CYCLE_TCK(); /* Idle */
return (val);
}
// JTAG Write ABORT register
// data: value to write
// return: none
void JTAG_WriteAbort (uint32_t data) {
uint32_t n;
PIN_TMS_SET();
JTAG_CYCLE_TCK(); /* Select-DR-Scan */
PIN_TMS_CLR();
JTAG_CYCLE_TCK(); /* Capture-DR */
JTAG_CYCLE_TCK(); /* Shift-DR */
for (n = DAP_Data.jtag_dev.index; n; n--) {
JTAG_CYCLE_TCK(); /* Bypass before data */
}
PIN_TDI_OUT(0);
JTAG_CYCLE_TCK(); /* Set RnW=0 (Write) */
JTAG_CYCLE_TCK(); /* Set A2=0 */
JTAG_CYCLE_TCK(); /* Set A3=0 */
for (n = 31; n; n--) {
JTAG_CYCLE_TDI(data); /* Set D0..D30 */
data >>= 1;
}
n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1;
if (n) {
JTAG_CYCLE_TDI(data); /* Set D31 */
for (--n; n; n--) {
JTAG_CYCLE_TCK(); /* Bypass after data */
}
PIN_TMS_SET();
JTAG_CYCLE_TCK(); /* Bypass & Exit1-DR */
} else {
PIN_TMS_SET();
JTAG_CYCLE_TDI(data); /* Set D31 & Exit1-DR */
}
JTAG_CYCLE_TCK(); /* Update-DR */
PIN_TMS_CLR();
JTAG_CYCLE_TCK(); /* Idle */
PIN_TDI_OUT(1);
}
// JTAG Set IR
// ir: IR value
// return: none
void JTAG_IR (uint32_t ir) {
if (DAP_Data.fast_clock) {
JTAG_IR_Fast(ir);
} else {
JTAG_IR_Slow(ir);
}
}
// JTAG Transfer I/O
// request: A[3:2] RnW APnDP
// data: DATA[31:0]
// return: ACK[2:0]
uint8_t JTAG_Transfer(uint8_t request, uint32_t *data)
{
if (DAP_Data.fast_clock)
{
return JTAG_TransferFast(request, data);
} else {
return JTAG_TransferSlow(request, data);
}
}
#endif /* (DAP_JTAG != 0) */
SW_DP.c
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/******************************************************************************
* @file SW_DP.c
* @brief CMSIS-DAP SW DP I/O
* @version V1.00
* @date 31. May 2012
*
* @note
* Copyright (C) 2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include "DAP_config.h"
#include "DAP.h"
// SW Macros
#define PIN_SWCLK_SET() PIN_SWCLK_TCK_SET()
#define PIN_SWCLK_CLR() PIN_SWCLK_TCK_CLR()
#define SW_CLOCK_CYCLE() \
PIN_SWCLK_CLR(); \
PIN_DELAY(); \
PIN_SWCLK_SET(); \
PIN_DELAY()
#define SW_WRITE_BIT(bit) \
PIN_SWDIO_OUT(bit); \
PIN_SWCLK_CLR(); \
PIN_DELAY(); \
PIN_SWCLK_SET(); \
PIN_DELAY()
#define SW_READ_BIT(bit) \
PIN_SWCLK_CLR(); \
PIN_DELAY(); \
bit = PIN_SWDIO_IN(); \
PIN_SWCLK_SET(); \
PIN_DELAY()
#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)
// Generate SWJ Sequence
// count: sequence bit count
// data: pointer to sequence bit data
// return: none
#if ((DAP_SWD != 0) || (DAP_JTAG != 0))
void SWJ_Sequence (uint32_t count, uint8_t *data)
{
uint8_t val;
uint8_t n = 0;
DEBUG("DATA:");
while (count != 0)
{
count--;
if (n == 0)
{
val = *data++;
DEBUG(" %02X", val);
n = 8;
}
if (val & 1)
{
PIN_SWDIO_TMS_SET();
}
else
{
PIN_SWDIO_TMS_CLR();
}
SW_CLOCK_CYCLE();
val >>= 1;
n--;
}
DEBUG("\n");
}
#endif
#if (DAP_SWD != 0)
// SWD Transfer I/O
// request: A[3:2] RnW APnDP
// data: DATA[31:0]
// return: ACK[2:0]
#define SWD_TransferFunction(speed) /**/ \
uint8_t SWD_Transfer##speed (uint8_t request, uint32_t *data) \
{ \
uint8_t ack; \
uint8_t bit; \
uint32_t val; \
uint8_t parity; \
uint8_t n; \
\
/* Packet Request */ \
parity = 0; \
SW_WRITE_BIT(1); /* Start Bit */ \
\
bit = request >> 0; \
SW_WRITE_BIT(bit); /* APnDP Bit */ \
parity += bit; \
\
bit = request >> 1; \
SW_WRITE_BIT(bit); /* RnW Bit */ \
parity += bit; \
\
bit = request >> 2; \
SW_WRITE_BIT(bit); /* A2 Bit */ \
parity += bit; \
\
bit = request >> 3; \
SW_WRITE_BIT(bit); /* A3 Bit */ \
parity += bit; \
\
SW_WRITE_BIT(parity); /* Parity Bit */ \
SW_WRITE_BIT(0); /* Stop Bit */ \
SW_WRITE_BIT(1); /* Park Bit */ \
\
/* Turnaround */ \
PIN_SWDIO_OUT_DISABLE(); \
for (n = DAP_Data.swd_conf.turnaround; n != 0; n--) \
{ \
SW_CLOCK_CYCLE(); \
} \
\
/* Acknowledge response */ \
SW_READ_BIT(bit); \
ack = bit << 0; \
\
SW_READ_BIT(bit); \
ack |= bit << 1; \
\
SW_READ_BIT(bit); \
ack |= bit << 2; \
\
if (ack == DAP_TRANSFER_OK) \
{ /* OK response */ \
/* Data transfer */ \
if (request & DAP_TRANSFER_RnW) \
{ /* Read data */ \
val = 0; \
parity = 0; \
for (n = 32; n; n--) \
{ \
SW_READ_BIT(bit); /* Read RDATA[0:31] */ \
parity += bit; \
val >>= 1; \
val |= bit << 31; \
} \
SW_READ_BIT(bit); /* Read Parity */ \
if ((parity ^ bit) & 1) \
{ \
ack = DAP_TRANSFER_ERROR; \
} \
if (data) *data = val; \
/* Turnaround */ \
for (n = DAP_Data.swd_conf.turnaround; n != 0; n--) \
{ \
SW_CLOCK_CYCLE(); \
} \
\
PIN_SWDIO_OUT_ENABLE(); \
} \
else \
{ \
/* Turnaround */ \
for (n = DAP_Data.swd_conf.turnaround; n != 0; n--) \
{ \
SW_CLOCK_CYCLE(); \
} \
\
PIN_SWDIO_OUT_ENABLE(); \
/* Write data */ \
val = *data; \
parity = 0; \
for (n = 32; n; n--) { \
SW_WRITE_BIT(val); /* Write WDATA[0:31] */ \
parity += val; \
val >>= 1; \
} \
SW_WRITE_BIT(parity); /* Write Parity Bit */ \
} \
/* Idle cycles */ \
n = DAP_Data.transfer.idle_cycles; \
if (n != 0) \
{ \
PIN_SWDIO_OUT(0); \
for (; n != 0; n--) \
{ \
SW_CLOCK_CYCLE(); \
} \
} \
PIN_SWDIO_OUT(1); \
return (ack); \
} \
\
if (ack == DAP_TRANSFER_WAIT || ack == DAP_TRANSFER_FAULT) \
{ \
/* WAIT or FAULT response */ \
if (DAP_Data.swd_conf.data_phase && (request & DAP_TRANSFER_RnW) != 0) \
{ \
for (n = 32+1; n; n--) \
{ \
SW_CLOCK_CYCLE(); /* Dummy Read RDATA[0:31] + Parity */ \
} \
} \
/* Turnaround */ \
for (n = DAP_Data.swd_conf.turnaround; n != 0; n--) \
{ \
SW_CLOCK_CYCLE(); \
} \
\
PIN_SWDIO_OUT_ENABLE(); \
if (DAP_Data.swd_conf.data_phase && (request & DAP_TRANSFER_RnW) == 0) \
{ \
PIN_SWDIO_OUT(0); \
for (n = 32 + 1; n != 0; n--) \
{ \
SW_CLOCK_CYCLE(); /* Dummy Write WDATA[0:31] + Parity */ \
} \
} \
PIN_SWDIO_OUT(1); \
return (ack); \
} \
\
/* Protocol error */ \
for (n = DAP_Data.swd_conf.turnaround + 32 + 1; n != 0; n--) \
{ \
SW_CLOCK_CYCLE(); /* Back off data phase */ \
} \
\
PIN_SWDIO_OUT(1); \
return (ack); \
}
#undef PIN_DELAY
#define PIN_DELAY() PIN_DELAY_FAST()
SWD_TransferFunction(Fast);
#undef PIN_DELAY
#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)
SWD_TransferFunction(Slow);
// SWD Transfer I/O
// request: A[3:2] RnW APnDP
// data: DATA[31:0]
// return: ACK[2:0]
uint8_t SWD_Transfer(uint8_t request, uint32_t *data)
{
if (DAP_Data.fast_clock)
return SWD_TransferFast(request, data);
else
return SWD_TransferSlow(request, data);
}
#endif /* (DAP_SWD != 0) */
readme.md
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本工程从“技新”开源的DAPLINK修改来。
修改 by：rush
1，解决了原工程缺文件无法编译问题。测试使用MDK474编译.由于某个文件RTL.h戳中了keil的G点，你需要注册机给keil注册下RTOS的功能！
2，原工程居然想当然去修改了设备名字！！！！导致了很多版本MDK无法识别！！
3，原工程注释掉部分描述符，不知道是不是复合设备不兼容他们的win7，总之这导致了在win10下复合设备不识别(看到只有串口没有HID)
4，原工程USBlib使用lib，但是提供了一份源码，为了完全开源我们改用源码编译，其中部分inline导致无法编译，已去除。
5，那个USBlib库不兼容GD等国产单片机，请老实花钱购买正常STM32芯片。
6，电路图就是常见的老古董STLINK2.0，还能刷JLINK OB的那种。我晶振是12M，用8M自行修改。